CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2014

Transcription

1 CS DIGITAL LOGIC & STATE MACHINE DESIGN SPRING DUE : April 7, HOMEWOR V READ : Relted portions of Chpters III, IV, VI, VII nd VIII ASSIGNMENT : There re seven questions Solve ll homework nd exm problems s shown in clss nd pst exm solutions ) Consider the vending mchine controller digitl system designed in clss nd lso worked on in Homework Remember tht it is modified so tht it ccepts qurters : Q D N G C Amount Inputs DG DC RetDime RetNickel Q : Qurter is input D : Dime is input N : Nickel is input G : Gum is selected C : Chips is selected Outputs Amount : Vlue of gum nd chips (35 cents) or the coin input so fr shown on two 7-segment displys DG : Deliver Gum DC : Deliver chips RetDime : Return cents RetNickel : Return 5 cents Textul Input/Output Reltionship clock After receiving the necessry mount (35 cents to 5 cents) nd the selection is mde deliver gum or chips nd return 5 or cents if necessry Strt with the feedbck you received in Homework bout the opertion digrm nd the highlevel stte digrm Then : Modify the dtpth ) Solve Problem 6 (b) You will obtin the miniml SOP expression Drw the miniml circuit, ssuming tht doubleril inputs re vilble Remember to write down the postulte or theorem used for the expression simplifiction, not the number of the postulte or theorem 3) Solve Problem 7 (h) NYU School of Engineering Pge of Hndout No : 5 April 3,

2 The order of the inputs on the truth tble is importnt The order is (A, B, C, D) You will show n output column for ech opertor (AND, OR, NOT) Note tht you will ssume there is no NOR gte in the circuit nd will not simplify the expression in this question Drw the circuit of the originl expression given in the textbook : (((A + B ) + C) + D), ssuming tht single-ril inputs re vilble nd with AND, OR, NOT gtes How mny gte levels does the originl expression hve? Then convert the originl circuit (with AND, OR, NOT) to miniml circuit with only NAND gtes, s done in clss ) Solve Problem 9 (d) The question is sking you to obtin cnonicl SOP nd POS expressions Show lso the missing minterm list The order of inputs is (W, X, Y) 5) Solve Problem (e) Solve it for only the cnonicl SOP expression Do not obtin the cnonicl POS expression Show the minterm list The order of the inputs is (X, Y, Z) The expression in the problem hs three terms, the lst two of which re identicl Use relevnt postultes nd theorems to hndle tht Ech term in the expression is not cnonicl Thus, they hve to be expnded to include ll the inputs of the function s done in clss 6) Develop non-priority -to- encoder shown below Non-priority mens tht it is gurnteed tht t ny time either ll inputs re or only one input is Provide n output nmed vlid which is, when n encoder input is The vlid output is, when ll inputs re I9 I I7 I6 I5 I I3 I I I -to- Encoder msb vlid Y3 Y Y Y First, show the opertion tble of the encoder, which is simplified truth-tble since t ny time no more thn one input is From the opertion tble, you will derive the miniml equtions Then, drw the corresponding gte networks for the five outputs Then, indicte the generic gte usge, ie which gtes, how mny of ech nd the totl generic gte count Students cn tke look t the implementtion of the 7LS7 TTL MSI chip which is -to- priority encoder with ctive-low inputs, ctive-low dt outputs nd no vlid output 7) Consider the blck box view nd input/output reltionship of BCD ADDer, combintionl circuit, shown below : NYU School of Engineering Pge of CS Hndout No : 5 April 3,

3 + M + c in BCD S For exmple : M ADDer = (3) c c out in S = 3 nd c out is Develop the BCD ADDer for PCB Tht is, implement the BCD ADDer tht will be eventully implemented with chips on PCB Use the following notes s you implement the BCD ADDer : i) The circuit is combintionl circuit! The Digitl Product Development hndout indictes tht first the precise input/output reltionship must be obtined : the truth tble! This is imprcticl for the BCD ADDer since there re nine inputs! Therefore, we hve to obtin the opertion tble Then, we would proceed with the implementtion step below ii) According to the Digitl Product Development hndout, we try to implement the BCD ADDer immeditely We nswer the following questions (from Digitl Product Development) : Í Is it implementble by using or few gtes on one or few SSI chips? No! Í Is there single high-density chip, or few high-density chips tht implements the bove blck box with the given opertion tble? No! Í Any progrmmble chip or chips? Yes, but for the ske of this problem, we will sy No, Í A few SSI chips? No! Í A custom chip implementtion? We could try it, but for the ske of this problem, we will sy No too, Í Since there is no immeditte implementtion, we hve to prtition the BCD ADDer bsed on the mjor opertions on the opertion tble The BCD ADDer is not very complex which ensures tht ech block is immeditely implementble Í After the prtitioning, for ech block, do the following : Get the input/output reltionship, n opertion tble Then, sk the implementtion questions bove One of them will be Yes, so you will not prtition nymore Agin, you hve three tsks : (i) you will get the opertion tble of the bove blck box, then (ii) determine the mjor opertions nd (iii) prtition the blck box into blocks tht re immeditely implementble by chips tht we hve discussed in clss! Drw the blocks by hnd nd clerly lbel wires Precisely indicte which input of block is connected to which output of block Do not implement the blocks (do not implement with chips) When you prtition, you will stop, if ech block is immeditely implementble by the first or third questions bove Tht is, ech block is implementble by using severl TTL LS chips nd perhps few SSI chips if necessry Hint : Try to mke use of your nswers to Question nd Question 3 in Homewrok II NYU School of Engineering Pge 3 of CS Hndout No : 5 April 3,

4 RELEVANT QUESTIONS AND ANSWERS Q) Consider the following digitl system whose blck-box view, dtpth nd high-level stte digrm re shown below : M Strt End clock OUT Done End = A ; B M ; C A = 3 A A - C Strt = C + B A = Done = End = Strt = clock Store B M clock Store C Sel p clock -bit -to- MUX Store A C L Q D B D C C Q L D C C L A D Q (-) Cler C OUT q Sel -bit -to- MUX r Sel -bit -to- MUX To Control Unit Done -bit ADD Over From Control Unit NYU School of Engineering Pge of CS Hndout No : 5 April 3,

5 ) Consider the tble below tht shows the initil vlues of number of signls in the dtpth with respect to time : Time Stte Strt End M A B C OUT Done t 5??? t 5 Continue tn 7 Continue with the tble until the control returns to stte s shown s the lst row on the bove tble Assume tht End is until Done is It returns to, one clock period fter Done becomes nd M re until Strt becomes gin b) Drw the low-level stte digrm of the digitl system Signl Over is control signl, besides other control signls Register A is checked by the Control Unit nd so its outputs re sttus signls A) ) The tble is completed s follows : Time Stte Strt End M A B C OUT Done t 5??? t 5 t NS NS t3 NS NS 5 5 t NS NS 5 t5 3 NS NS A A t6 7 NS NS NS A b) The low-level stte digrm of the digitl system is below Store A = ; Store B = ; Cler C = ; p = Strt = p = ; q = ; r = ; Store A = Strt = End = A = q = ; r = ; Store C = 3 Over = A = End = NYU School of Engineering Pge 5 of CS Hndout No : 5 April 3,

6 Q) Consider the following digitl system whose blck-box view, dtpth nd high-level stte digrm re shown below : A ; B clock OUT Done 3 If > A then A & B If > A then A & B If > A then A & B Done = Store A A -bit Store B ENCPOS clock C L Q D A Unsigned Binry Comprtor clock C L Q D B B OUT AgtB Over Done ) Consider the following tble tht shows the vlues of number signls in the dtpth Time Stte A AgtB B OUT Done t A????? t 3F A t C t3 3 9 t 57 t5 E NYU School of Engineering Pge 6 of CS Hndout No : 5 April 3,

7 Time Stte A AgtB B OUT Done t6 6A t7 39 t 3 F t9 7 t F t Continue with the tble b) Drw the low-level stte digrm of the digitl system Signls Over nd ENCPOS (Encoded Position) re control signls, besides other control signls AgtB is sttus signl A) ) The tble is completed s follows : Time Stte A gta B OUT Done t A???? t 3F A t C 3F t3 3 9 C t 57 NS NS t5 E NS NS t6 6A E t7 39 6A t 3 F NS NS t9 7 NS NS t F 6A t F b) The low-level stte digrm of the digitl system is s follows : NYU School of Engineering Pge 7 of CS Hndout No : 5 April 3,

8 Store A = ; Store B = ; ENCPOS = ENCPOS = ; If AgtB then ; Store A = ; Store B = ENCPOS = ; If AgtB then ; Store A = ; Store B = ENCPOS = ; If AgtB then ; Store A = ; Store B = 3 Over = Q3) Simplify the following expression by using Switching Algebr : bc + (bc + c)[b( + c) + bc + b c] A3) = bc + (bc + c)[b + bc + bc + b c] k(m + p) = km + kp = bc + (bc + c)[b + c + b c] k(m + p) = km + kp & k + k = & k = k = bc + (bc + c)[b + c + b] k + km = k + m = bc + (bc + c)[ + c] k(m + p) = km + kp & k + k = & k = k = bc + bc + c k(m + p) = km + kp & kk = k & k k = & k + = k = bc + c k + k = k Q) Consider the following switching expression : f(, b, c, d) = (bc + bc) + (c + d) + bcd + cd( + c) Simplify the expression by using Switching Algebr nd then drw the corresponding -level AND/OR gte network, ssuming there re only single-ril inputs A) The solution is below : NYU School of Engineering Pge of CS Hndout No : 5 April 3,

9 f(, b, c, d) = (bc + bc) + (c + d) + bcd + cd( + c) = (bc + bc) + (c + d) + bcd + cd k + km = k = (b(c + c)) + (c + d) + bcd + cd k(m + p) = km + kp = b + (c + d) + bcd + cd k + k = & k = k = b + cd + bcd + cd (k + m) = k m & k = k = b + cd( + b) + cd k(m + p) = km + kp = b + cd+ cd k + = & k = k b b The miniml -level AND/OR gte network contins seven gtes d d c cd f(, b, c, d) = b + cd + cd c c d cd Q5) Consider the following gte network : B A A B (logic one) C B A f(a, B, C, D) Simplify the gte network to obtin miniml SOP expression, by using Switching Algebr A5) We first write down the expression t the output of ech gte to obtin the switching expression : B B A A AB AB C AB + AB (AB + AB) + A B A B C [(AB + AB) + ] +A B C f(a, B, C, D) NYU School of Engineering Pge 9 of CS Hndout No : 5 April 3,

10 We then minimize the switching expression : f(a, B, C, D) = [(A B + A B) + ] + A B C = [k +] + A B C k = A B + A B = k + k + A B C k + m = k m + km = k + A B C = & m = & m = m & m+ = m = ((AB) + (AB)) + A B C k = A B + A B = ((AB) (AB)) + A B C (k + m) = k m There is yet nother = ((A + B)(A + B)) + A B C (km) = k + m = ((A + B)(A + B)) + A B C k = k = A A + AB + A B + B B + A B C k(m + p) = km + kp = AB + A B + A B C kk = & k + = k = B(A + AC) + AB k(m + p) = km + kp = B(A + C) + AB k + km = k + m = A B + B C + AB k(m + p) = km + kp miniml expression : (A B + AC + AB), which is impossible to notice during the simplifiction The fct tht the lgebr does not enble us to relize there re multiple miniml expressions, is one of min drwbcks of using Switching Algebr for circuit minimiztion Q6) Consider the following miniml SOP expression : f(, b, c, d) = b c d + d i) Drw the corresponding -level NAND-NAND gte network, ssuming single-ril inputs nd s done in clss ii) Obtin the cnonicl SOP expression of the function lgebriclly s done in clss iii) Obtin the minterm nd mxterm lists of the function A6) i) We know tht n SOP expression is implemented by -level AND-OR gte network We lso know tht -level AND-OR gte network is immeditely implemented by -level NAND-NAND gte network c d b d f(, b, c, d) = b c d + d ii) f(, b, c, d) = bcd + d = bcd( + ) + d(b + b)(c + c) k + k = & k = k = bcd + bcd + d(bc + bc + bc + b c) k(m+p) = km + kp NYU School of Engineering Pge of CS Hndout No : 5 April 3,

11 = bcd + bcd + bcd + bcd + bcd + b cd k(m+p) = km +kp = bcd + bcd + bcd + bcd + b cd k + k = k iii) bcd bcd bcd bcd b cd f(,b,c,d) = m(5,9,,3,5) f(,b,c,d) = M(,,,3,,6,7,,,,) Q7) Simplify the following switching expression by using Switching Algebr s shown in clss : f(a, B, C, D) = ((A C D) + (B C)) (A + (B D)) + A B C + (A C + A C) + (A B (C + D)) Then, drw the miniml -level AND/OR gte network, ssuming tht there re double-ril inputs A7) = ((A C D) + (B C)) (A + (B D)) + A B C + (A C + A C) + (A B (C + D)) = (A C D) (B C) (A (B D)) + A B C + ((AC) (A C)) + (A B (C D)) (k m) = k + m & (k + m) = k m = (A C D) (B C) (A (B D)) + A B C + ((AC) (A C)) + (A B (C D)) k = k = (A C D) (B + C) (A B D) + A B C + (A + C)(A + C) + A B C D (k m) = k + m & (k + m) = k m = (A C D) (B + C) (A (B D) + A B C + (A + C)(A + C) + A B C D k = k = (A B C D +A C D)(A B D)+A B C+A A+A C+A C+C C+A B C D k(m + p) = km + kp & kk = k = (A B C D + A C D)(A B D) + A B C + A C + A C + A B C D k k = & k + =k = (AABBCDD + A A BCDD) + A B C + A C + A C + A B C D k(m + p) = km + kp = A B C + A C + A C + A B C D k k = & k+ = k & k k = k = A B C + A C + A C k + km = k = A C + A C k + km = k A C AC AC + AC A C AC f(a, B, C, D) NYU School of Engineering Pge of CS Hndout No : 5 April 3,

12 Q) Consider the following expression : f(, b, c, d) = ( + b) + c(d( + ) + (bb)) + c(b + + b)d (i) Simplify the expression to obtin the miniml SOP expression by using Switching Algebr s shown in clss (ii) Then, drw the corresponding miniml -level NAND-NAND gte network, by ssuming single-ril inputs A) i) The simplifiction to obtin the miniml SOP expression : f(, b, c, d) = ( + b) + c(d( + ) + (bb)) + c(b + + b)d = ( + b) + c(d + ) + c(b + + b)d k + k = & kk = = ( + b) + cd + c(b + + b)d k = k & k + = k = ( + b) + cd + c(b + + b)d k + km = k + m = ( + b) + cd + cd k + k = & k = k = ( b) + cd + cd (k + m) = k + m = b + cd + cd k = k ii) We know tht n SOP expression is directly implemented by -level AND-OR gte network nd -level AND- OR gte network cn be immeditely converted to -level NAND-NAND gte network : Single-ril inputs c b d c c d d f(, b, c, d) = b + cd + cd Q9) Determine if the following two functions, y(, b, c), z(, b, c), re equivlent : b b c b y(, b, c) z(, b, c) = m(,, ) NYU School of Engineering Pge of CS Hndout No : 5 April 3,

13 A9) We obtin the switching expression for the y(, b, c) function In order to do tht we first plce the term tht corresponds to the output of ech gte nd the full expression for function y(, b, c) : y(, b, c) = ( b + b + b c) b b c b b b bc b + b + bc (b + b + bc) y(, b, c) = (b ( + ) + b c) k(m + p) = km + kp = (b () + b c) k + k = = (b + b c) k = k = (b + c) k + km = k + m = b + c k(m + p) = km + kp The miniml SOP expression cn now be converted to cnonicl SOP expression : = b (c + c) + c (b + b) k + k = & k = k = b c + b c + b c + b c k(m + p) = km + kp = b c + b c + b c k + k = k The bove three cnonicl product terms correspond to minterms, nd, respectively : b c + b c + b c y(,b,c) = m(,,) given tht z(,b,c) = m(,,) y(, b, c) = z(, b, c) Q) By using truth tble, show if the following two expressions re equivlent : f(, b, c) = ( + ((b+c) ) g(, b, c) = ( + b + c) A) 3 5 b c ( + ((b + c) ) ( + b + c) On the output columns section, there is column for ech opertion The order of obtining the output columns is bsed on the precedence rules nd is shown by the numbered rrows Function f(, b, c) is column Function g(, b, c) is column 5 Since the f(, b, c) nd g(, b, c) columnsre not equivlent, the two functions re not equivlent NYU School of Engineering Pge 3 of CS Hndout No : 5 April 3,

14 Q) Consider the following combintionl circuit with four inputs nd two outputs : b c d msb y(, b, c, d) z(, b, c, d) is -bit s Complement Binry number y = if > (3) z = if < (-5) (i) Obtin the truth tble of the circuit bsed on the textul input/output reltionship (ii) Then, obtin the minterm lists of the outputs from the truth tble (iii) Then, obtin the cnonicl SOP expression of output y(, b, c, d) s shown in clss A) The truth tble nd the minterm lists : y z The Minterm lists : y(, b, c, d) = m(, 5, 6, 7) z(, b, c, d) = m(, 9, ) The cnonicl SOP expression for y(, b, c, d) : y(, b, c, d) = Q) The blck-box view nd purpose of specil purpose comprtor circuit re shown below : msb is -bit unsigned binry number b y(, b, c, d) c y = if is equl to or or 6 or d or or 5 i) Obtin the truth tble of the function y(, b, c, d) s done in clss NYU School of Engineering Pge of CS Hndout No : 5 April 3,

15 ii) Obtin the minterm list of the function s done in clss iii) Consider the following miniml SOP expression : f(, b, c, d) = d + d Prove/disprove if function f(, b, c, d) is equivlent to function y(, b, c, d) by first obtining the truth tble of f(, b, c, d) s done in clss nd then the minterm list of f(, b, c, d) from its truth tble A) Truth tbles nd minterm lists : y(,b,c,d) d d d d + d The Minterm list : y(,b,c,d) = m(,,6,,,5) The minterm list for f(, b, c, d) : f(,b,c,d) = m(,,,6,9,,3,5) Since the two functions do NOT hve identicl minterm lists, they re NOT equivlent to ech other! Q3) Consider the combintionl circuit with four inputs nd four outputs below (i) Obtin the truth tble of the combintionl circuit bsed on the textul input/output reltionship G b c d msb msb z3(, b, c, d) z(, b, c, d) z(, b, c, d) z(, b, c, d) Z G is 3-bit s Complement Binry number Z is -bit s Complement Binry number If = then Z = G - else Z = G + In order for G to hve four bits so tht it hs the sme bits s Z, ssume tht G hs n invisible fourth (leftmost) bit whose vlue is obtined vi sign extension on G Then perform the necessry opertion on G Nme this invisible leftmost bit s e nd show it on your truth tble NYU School of Engineering Pge 5 of CS Hndout No : 5 April 3,

16 (ii) Then, obtin the minterm lists of the outputs from the truth tble (iii) Then, obtin the cnonicl SOP expression of output z3 s shown in clss A3) The truth tble, the minterm lists nd the cnonicl SOP expression : G Z G Z e z3 z z z The Minterm lists : z3(,b,c,d) = m(,, 5, 6, 7,, 3, ) z(,b,c,d) = m(, 5, 6, 7,,, 3, ) z(,b,c,d) = m(, 3,, 7, 9,, 3, ) z(,b,c,d) = m(,,, 6,,,, ) The cnonicl SOP expression for z3 : z3(, b, c, d) = Q) Consider the following combintionl circuit with four inputs nd four outputs : & R re s Complement Binry numbers b c d msb msb w(, b, c, d) x(, b, c, d) y(, b, c, d) z(, b, c, d) R b Opertion R = - (negte ) R = * (two times ) R = * (four times ) R = * ( times ) (i) Obtin the truth tble of the circuit bsed on the opertion tble Use sign extensions to obtin bits of R from bits of s done in the homework (ii) Then, obtin the minterm lists of the outputs from the truth tble (iii) Then, obtin the cnonicl SOP expression of output z(, b, c, d) s shown in clss NYU School of Engineering Pge 6 of CS Hndout No : 5 April 3,

17 A) The truth tble nd the minterm lists : e f w x y z The Minterm lists : w(, b, c, d) = m(, 6, 7,, ) x(, b, c, d) = m(, 6, 7, 9,, ) y(, b, c, d) = m(,, 5, 7) z(, b, c, d) = m(, 3, 3, 5) The cnonicl SOP expression for z(, b, c, d) : 3 3 z(, b, c, d) = Since input hs two bits nd output R hs bits, we sign extend input by two bits These new leftmost two bits of re e nd f nd their vlues re shown on the truth tble bove Q5) Consider the combintionl circuit with four inputs nd three outputs below : & R re s Complement Binry numbers b c d msb msb vlid(, b, c, d) y(, b, c, d) R z(, b, c, d) b Opertion R = + ; vlid = if overflow R = - ; vlid = if overflow y = d ; z = c ; vlid = y = d ; z = ; vlid = (i) Obtin the truth tble of the circuit bsed on the opertion tble (ii) Then, obtin the minterm lists of the outputs from the truth tble (iii) Then, obtin the cnonicl SOP expression of output z(, b, c, d) s shown in clss A5) The truth tble nd the minterm lists : NYU School of Engineering Pge 7 of CS Hndout No : 5 April 3,

18 vlid y z The Minterm lists : vlid(, b, c, d) = m(,, 3,, 5, 7,, 9,,,, 3,, 5) y(, b, c, d) = m(,,, 7, 9,, 3, 5) z(, b, c, d) = m(,,, 6,, ) The cnonicl SOP expression for z(, b, c, d) : 6 z(, b, c, d) = Q6) Consider Block 6, the Mchine Ply Block, of the term project Assume tht the mchine plyer hs the following plying strtegy : Ply on the (rightmost) lrgest disply position with n ddition ) Assume tht the code is 5 The tble below shows the rndom digit, position displys before nd fter the mchine plyer plys, if the mchine plyer is hed (PGTP = Yes) before the ply, whether the rndom digit is plyed directly or dded, the number of djcencies, the points erned by the mchine plyer nd if the mchine plyer plys gin Complete the rows of the tble You will circle the position plyed : RD Displys before ply PD3 PD PD PD PGTP Displys fter ply PD3 PD PD PD D/A Adjcency Rewrd Points (Deciml) Plys Agin? 5 7 Yes C No 6 E 6 No 3 A E 6 3 Yes 7 F E 3 No NYU School of Engineering Pge of CS Hndout No : 5 April 3,

19 b) Assume tht the bove mchine plyer is modified to hve different strtegy The dtpth of the circuit tht implements the modified mchine plyer for the new plying strtegy is below : DISP5 DISP Rightmost Lrgest Disply Position Circuit (M) LRDP LRDP LRRP LRRP LRDP LRDP A A B B Sel -bit -to- MUX Y Y I I -to- DCD Y3 Y Y Y Ply Test3 Test Test Test PSEL3 PSEL PSEL PSEL RD3 RD Rightmost Lrgest Regulr Rewrd Position Circuit LRRP LRRP RDLT PPT PPT RDLT PGTP A B PGTP Pcnply -bit Unsigned Binry Comprtor AGtB Ply PGTP Pcnply Ply Pcnply Ply Pdd Pplyed Pskip In the figure, M is Mcro of Block 6, s designed in the lb PGTP mens PPT > PPT This is the cse before the ply Pcnply is in the lst Plyer stte RD3 nd RD re the leftmost two bits of the rndom digit i) Drw the flowchrt of the plying strtegy of the modified mchine plyer ii) How mny clock periods does the mchine plyer tke to ply? Explin iii) Assume gin tht the code is 5 The tble below shows the sme vlues s the tble bove : The rndom digit, position displys before nd fter the mchine plyer plys, if the mchine plyer is hed (PGTP = Yes) before the ply, whether the rndom digit is plyed directly or dded, the number of djcencies, the points erned by the mchine plyer nd if the mchine plyer plys gin NYU School of Engineering Pge 9 of CS Hndout No : 5 April 3,

20 RD Displys before ply PD3 PD PD PD PGTP Displys fter ply PD3 PD PD PD D/A Adjcency Rewrd Points (Deciml) Plys Agin? 5 7 Yes C No 6 E 6 No 3 A E 6 3 Yes 7 F E 3 No Complete the rows of the tble You will circle the position plyed : A6) ) The tble is completed s follows : RD Displys before ply PD3 PD PD PD PGTP Displys fter ply PD3 PD PD PD D/A Adjcency Rewrd Points (Deciml) Plys Agin? 5 7 Yes C A N C No E A N 6 E 6 No 6 A N 3 A E 6 3 Yes A 6 3 A N 7 F E 3 No 6 E 3 A 6 N b) i) N PPT > PPT Y Ply on the (rightmost) lrgest regulr rewrd points position with n ddition N RD < Y Skip Ply on the (rightmost) lrgest disply position with n dition ii) The mchine plyer tkes five clock periodto ply It does only dditions, hence it tkes four clock periods to collect the four regulr rewrd points nd then one clock period to ply NYU School of Engineering Pge of CS Hndout No : 5 April 3,

21 iii) The tble is completed s follows : RD Displys before ply PD3 PD PD PD PGTP Displys fter ply PD3 PD PD PD D/A Adjcency Rewrd Points (Deciml) Plys Agin? 5 7 Yes 7 Skip Skip Skip Skip C No E A N 6 E 6 No E E 6 A Y 3 A E 6 3 Yes D 6 3 A N 7 F E 3 No F E F 3 A 5 N Q7) Consider Block 6, the Mchine Ply Block, of the term project Assume tht its strtegy is s follow : Ply on the (rightmost) lrgest djcency position (directly if equl) The dtpth of the circuit tht implements the bove strtegy is shown below : Rightmost Lrgest Adjcency Position (RLAP) Circuit RLAP RLAP RLAPdd LRGADJ LRGADJ RLAP RLAP I I RLAPdd -to- DCD Ply Y3 Y Y Y Ply Test3 Test Test Test Testdd Ply PSEL3 PSEL PSEL PSEL Pdd Pplyed Pskip In the figure, RLAPdd is if n ddition is needed to ply on the rightmost lrgest djcency position Ply is in the lst Plyer stte ) i) Assume tht the code is A7 The tble below shows the rndom digit, position displys before nd fter the mchine plyer plys, whether the rndom digit is plyed directly or dded, the number of djcencies, the points erned by the mchine plyer nd if the mchine plyer plys gin Complete the rows of the tble You will circle the position plyed : NYU School of Engineering Pge of CS Hndout No : 5 April 3,

22 RD Displys before ply PD3 PD PD PD Displys fter ply PD3 PD PD PD D/A Adjcency Rewrd Points (Deciml) Plys Agin? F F F F 6 F A E E ii) How mny clock periods does the mchine plyer tke to ply? Explin b) i) Assume tht the bove mchine plyer is modified to hve the following new strtegy : N The lrgest djcency is? Y Ply on the (rightmost) lrgest djcency position (directly if equl) Ply directly either on position if the rndom digit is even nd on position if the rndom digit is odd Assume gin tht the code is A7 The tble below shows the rndom digit, position displys before nd fter the mchine plyer plys, whether the rndom digit is plyed directly or dded, the number of djcencies, the points erned by the mchine plyer nd if the mchine plyer plys gin Complete the rows of the tble You will circle the position plyed : RD Displys before ply PD3 PD PD PD Displys fter ply PD3 PD PD PD D/A Adjcency Rewrd Points (Deciml) Plys Agin? F F F F 6 F A E E ii) Modify the bove circuit (the dtpth) to implement the new strtegy (two rectngles nd one ovl)you cn just show the modified portion of the circuit, not the whole circuit A7) ) i) The tble is completed below : NYU School of Engineering Pge of CS Hndout No : 5 April 3,

23 RD Displys before ply PD3 PD PD PD Displys fter ply PD3 PD PD PD D/A Adjcency Rewrd Points (Deciml) Plys Agin? F F F F F F F D N 6 F A 3 Y 6 A A A 7 A 7 Y 7 7 D 63 N 3 E E E A Y The strtegy does not check for code digits nd so misses to ern code rewrd points when the rndom digit is However, it erns code rewrd points by coincidence when the rndom digit is nd 7ii) The mchine plyer tkes nine clock periodto ply It does direct plying nd dditions, hence it tkes eight clock periods to collect the eight djcencies nd then one clock period to ply b) i) The tble is completed s follows : RD Displys before ply PD3 PD PD PD Displys fter ply PD3 PD PD PD D/A Adjcency Rewrd Points (Deciml) Plys Agin? F F F F F F F D N 6 F A 3 Y 6 A A A 7 A 7 Y 7 7 D 7 N 3 E E E A Y The strtegy lso does not check for code digits nd so gin misses to ern code rewrd points when the rndom digit is It lso misses to ern code rewrd points when the rndom digit is 7 However, it gin erns code rewrd points by coincidence when the rndom digit is ii) We know tht the Rightmost Lrgest Adjcency circuit keeps the lrgest djcency when it determines which position hs it The lrgest djcency lines, LRGADJ nd LRGADJ re used to determine if the djcency is : NYU School of Engineering Pge 3 of CS Hndout No : 5 April 3,

24 Rightmost RLAP RD A Lrgest Adjcency Position (RLAP) Circuit RLAP RLAPdd LRGADJ LRGADJ RLAP RLAP Adj B A B -bit -to- MUX Sel Y Y I I -to- DCD Y3 Y Y Y RLAPdd Adj Ply Ply Test3 Test Test Test Testdd Ply PSEL3 PSEL PSEL PSEL Pdd Pplyed Pskip Q) Consider the following digitl system whose blck-box view nd high-level stte digrm re shown below : Go Clr clock W Y Z Vlid Y = ; W = A ; Vlid = ; Z = ; A ; B Go Go Y = ; W = A ; Vlid = ; Z = ; If > A then {A ; B } Y = ; W = A ; Vlid = ; Z = ; If > A then {A ; B } 3 Y = ; W = A ; Vlid = ; Z = ; If > A then {A ; B } Y = ; W = A ; Vlid = ; Z = B The Clr input is n synchronous input tht forces the system to return to stte from ny stte t ny time nd keeps it t stte s long s Clr is ctive ) Consider Block 6, the Mchine Ply Block, of the term project Assume tht the digitl system bove is used for the mchine plyer s shown below NYU School of Engineering Pge of CS Hndout No : 5 April 3,

25 NSD Psturn Clerpffs Go Clr W Y Z Z Z Z Z3 Vlid Y Y Y Y3 PSEL PSEL PSEL PSEL3 Pdd Pclk clock Vlid Vlid Pplyed Pskip The tble below shows the rndom digit, position displys before nd fter the mchine plyer plys, whether the rndom digit is plyed directly or dded, the number of djcencies, the points erned by the mchine plyer nd if the mchine plyer plys gin RD Displys before ply PD3 PD PD PD Displys fter ply PD3 PD PD PD D/A Adjcency Rewrd Points (Deciml) Plys Agin? C 3 F C E The mening of D/A is Direct/Add which is whether the mchine plyer plys the rndom digit directly on position or by dding to position Note tht the cses on the tble re independent of ech other Tht is, they do not follow ech other with respect to time Complete the rows of the tble below You will circle the position plyed Assume tht the code is 93 b) Assume tht the bove mchine plyer is modified to hve new strtegy shown below : NYU School of Engineering Pge 5 of CS Hndout No : 5 April 3,

26 N There is n djcency? Y Ply on the (rightmost) lrgest disply with n ddition Ply on the (rightmost) lrgest djcency position directly Design the modified mchine plyer to implement the new strtegy Use the digitl system on the second pge nd the Rightmost Lrgest Disply Position circuit designed in Experiment s well s other circuits Describe the new signls you use Drw your design below PSEL W PSEL Go PSEL Clr Y PSEL3 Z clock Vlid Pdd Pplyed DISP 6 Rightmost Lrgest Disply Position Circuit z y I I msb -to- DCD Y Y Y Y3 DPOS DPOS DPOS DPOS3 Pskip How mny clock periods does the mchine plyer tke to ply? Explin NYU School of Engineering Pge 6 of CS Hndout No : 5 April 3,

27 A) ) The tble is completed s shown below : RD Displys before ply PD3 PD PD PD Displys fter ply PD3 PD PD PD D/A Adjcency Rewrd Points (Deciml) Plys Agin? C C D N 3 F C 6 3 F C 3 3 D 6 Y 9 E E D 36 Y D 3 Y D N The strtegy does not check for code digits nd so misses to ern code rewrd points when RD is 3 nd 9 b) The modified mchine plyer is shown below There re no new signls The mchine plyer tkes five clock periods to ply since the digitl system tkes clock periods to collect informtion nd one clock period to ply NYU School of Engineering Pge 7 of CS Hndout No : 5 April 3,

28 NSD Go Psturn Clr Clerpffs clock Pclk Rightmost DISP Lrgest 6 Disply Position Circuit W Y Z Vlid z y W I I msb W -to- DCD DPOS Z DPOS Z DPOS Z DPOS3 Z3 Y Y Y Y3 Adj A B A B A B A3 B3 Sel DPOS DPOS DPOS DPOS3 E -bit -to- MUX Y Y Y Y3 Vlid Y Y Y Y3 Adj Vlid Vlid PSEL PSEL PSEL PSEL3 Pdd Pplyed Pskip NYU School of Engineering Pge of CS Hndout No : 5 April 3,