Embedded System Design

Transcription

1 Dec. 2013/Jan th Semester B.E. Degree Examination Embedded System Design Time: 3 hrs. Max. Marks: 100 Note: 1. Answer any FIVE full questions, selecting at least two questions from each part. PART - A 1. a. Explain i) Embedded system ii) Hard RTS iii) Watch dog timer with an example for each. (06 Marks) Ans: i) Embedded system: An a combination of hard ware and software parts, as well as other components that we being together into products, such as a cell phone, a music player, a network router, or an air craft guidance systems. They are systems with in systems. Embedded systems techniques allow us to make products that are smaller, faster more reliable and cheaper. ii) Hard RTS: A hard RTS real time systems guarantees that critical tasks complete on time. This goal requires that all delay, in the system be bounded from the retrieval of the stored data to the time that to takes the operating system to finish any request made of it. If any time constraint is not met in hand real time system, the system is said to have failed. Such a failure may be seen as catastrophic. If it can result in considerable risk to people, to the environment or to a system being monitored or controlled. iii) Watch dog timer: When operating in electrically harsh environments such as the engine compartment of an automobile or the cockpit of an air craft, there is a high probability that electro magnetic noise may cause the system to behave essentially. To address the problems, we add a timer called watch dog timer. Periodically the microprocessor may reset the timer. If it fails to do so, the timer will reset the microprocessor, which generally solves the problems. 1. b. With a block diagram, explain briefly the various components in a micro processor hand embedded systems. (06 Marks) Ans: Microprocessor: Firmware Memory Memory Microprocessor Input/ output device Outside world signals Real time clock Input /output device Hosting application Input /output device 7-Embedded system design Dec 2013.indd /08/ :02:09 AM

2 Dec.2013/Jan.2014 Embedded System Design Block diagram for a micro processor based system is as shown in figure. A microprocessor is an integrated implementation of the central processing unit portion of the machine it is often simply referred to as a cpu or data path. Registers as small amounts of high speed memory that are used to temporarily store frequently used values such as a loop index or the index into a buffer. Input output subsystems the external memory system, clock or timing reference are the basis for timing, scheduling or measuring clasped time are included in computer system. All such components are connected via a system bus or buses. External to the microprocessor to different memory block are present. a) The firmware or program store contains the application code, and b) store: Contains data that is being manipulated, sent to or brought in from the external world. 1. c. Differentiate between the two design approaches for an embedded system development. Explain the various stages with a flow diagram. (08 Marks) Ans: User inputs Hardware Architecture Specification Block Diagram Schematic and logic Prototype(s) Hardware design Hardware implementation Hardware Testing Requirements Analysis Specification System Architecture Requirements Definition Functional Specification Software design Software implementation Software Testing Software Architecture Specification Module Specifications Module object Code Verified Hardware System Integration System validation Operation and Maintenance Verified system Validated system The Embedded system Life cycle Verified software 7-Embedded system design Dec 2013.indd /08/ :02:13 AM

3 Embedded System Design Dec.2013/Jan.2014 Figure above shows the high level flow through the development process and identifies the major elements of the development type cycle. The hard ware portion of life cycle involves the design, development and test of the physical system architecture, packaging, printed current boards and ultimately the individual component. The software portion deals with the algorithm portion of the application. Such software may be written in a high level language, assembler or mixture two. There are two design approaches for an embedded system development. 1. Traditional Design approach 2. Contemporary methodologies. Steps followed in traditional Design approach 1. Design the hard ware component 2. Design the software component. 3. Bring the two together 4. Spend time testing and Debugging the system. Where as in contemporary methodologies favour the combined and simultaneous, design of both hardware and software components. With the objectives of meeting system level requirements through trade - off. The major area of this design process 1. Ensuring a sound hardware and software specification and input to the process 2. Formulating the architecture for the system to be designed. 3. Partitioning the hard ware and software. 4. Providing an iterative approach to the design of hardware and software. Since the contemporary methodologies favour iterative design and develop both aspects of the system concurrently, we see that compared to traditional design this method has increased productivity - reduced design cycle time as well as improved product quality. 2. a. Compare: i) Big Endian abd Little Endian formats. ii) Risk and Cisc Registers iii) Juncation and surrounding errors. (06 Marks) Ans: i) Big Endian and little Endian formats: A word consists of four byte. The bits can be interpreted so as to place the most significant byte on the left and significant on the right or vise versa. LSB Big Endian MSB 31 0 fig (1) LSB Little Endian MSB 0 31 fig (2) ii) A word interpreted as in the fig.(1) is said to be written in Big Endian format. Rise and Cisc Registers: Depending on the architecture of the micro processor, it may have a few register - 16 to 256 or so or it may have Those microprocessors in the former category are reffered to as RISK and those in the later are called CISC. 7-Embedded system design Dec 2013.indd /08/ :02:14 AM

4 Dec.2013/Jan.2014 Embedded System Design iii) Function and rounding errors: Since word size limit one's ability to express numbers, eventually we go for either rounding or truncation. Whether we round or truncate, the resulting number will have an error. For example, consider a real number, N. following either truncation or rounding of the original number to fit the microprocessors word size, the number will have a fractional component of a bits. The value of the least significant bit is 2 -n. The graph shown below plot the original number closer in the truncated or rounded number. N truncated N Rounded 2-n 2 2-n N 2-n N Truncation Rounding Range of errors: Truncation: 2 n < E T 0 1 n 1 n Sounding: 2 < ER < Range of errors is same in both however, in case of sounding, the error is more evenly distributed and the maximum error is less. 2. b. Explain direct and register indirect addressing modes with diagrams. Also write the timing diagram for a serial write operation with an 8 bit register. (06 Marks) Ans: When using the direct and indirect addressing modes, we works with the operand, address rather than operand values. In both cases, the first level of address information is contained in the instruction. The difference between the two modes is that, in the direct mode, the contents of the operand failed in the instruction are the address of the derived operands, where as in the indirect case, the failed contains the address of the operand. In both mode, the major disadvantage is the additional memory accesses necessary to retrieve an operand. memory MSB 31 LSB 0 operation operand 1 operand 0 Direct MOVE*OPR1,*OPR0 *xptr=*yptr; memory MSB 31 LSB 0 Address operation Indirect operand 1 operand 0 Address MOVE**OPR1,*OPR0 *xptrptr=*yptrptr; 7-Embedded system design Dec 2013.indd /08/ :02:14 AM

5 Embedded System Design Dec.2013/Jan.2014 Figure above shows two different data transfer operation. For direct operation, at the C/C++ level, the value pointed to by one variable, if yptr, ptr, is assigned to a second variable pointed to by a second pointer variable xptr, ptr. At the assembly language level, the MOVE instruction directs that the contents referenced by operand, be copied to the location referenced by operand 0. For the indirect operation, at the C/C++ level, the value of now variable stored in memory and pointed to by the pointer variable by yptr ptr, is assigned to a second variable pointed to by a second pointed variable, xptr ptr. At the assembly language level, the MOVE instructional none direct that the contents of one memory location serve as the address in memory of the operand that is to be assigned to the location in memory identified by the second operand. Serial write operation: For a serial write operation, a write signal must accompany each data but that is interned. In the figure shown below the write operation, the contents of the register are changed to reflect the new values of the input data. write Read 2. c. Write the block diagram of RTN model for a microprocessor data path and memory interface. Also explain fetch, execute and next control operations with RTL instructions. (08 Marks) Ans: Program Counter path Memory subsystem Temp Register Arithmetic and Logical Unit Flag Register R 0 R n-1 General Purpose Register Instruction Register Instruction Decoder and Control Memory Interface Write Read Memory Register Memory Memory Address Register RTN model for a Microprocessor path and Memory Interface The control of the microprocessor data path comprises four fundamental operation defined as the instruction cycle. Then steps are as follows. 7-Embedded system design Dec 2013.indd /08/ :02:14 AM

6 Dec.2013/Jan.2014 Embedded System Design Fetch Decode Execute The instruction cycle Next a. Fetch fetch instruction b. Decode Decode current instruction c. Execute Execute current instruction d. Next Compute address of next instruction Fetch: The fetch operation retrieves an instruction from memory. The instruction is identified by its address, which is the contents of the program counter, PC. Thus at the ISA level, the fetch operation is written as MOVE IR, * PC; Move the memory word identified by the address contained in the program counter into the instruction register. At RTL level: At RTL level, the fetch decomposes into the sequence of steps given below. (1) MAR PC; i.e. PC enabled out to bus and MAR captures value. (2) MDR memory [MAR] The content of specified memory location is placed into MDR. (3) IR MDR MDR enabled out to bus and IR captures value. Execute: Based on the value contained in the op-code field, the control logic performs the sequence of steps necessary to execute the instruction. For example to store the contents of a register in a named location in memory, following instruction should be written at RTL level. (1) MAR R1 R1 enabled out to buy and MAR captures the value. (2) MDR memory [MAR] Contents of specified memory location placed into MDR. (3) R 2 MDR MDR value enabled out to bus and R2 captures value. NEXT: The address of the next instruction to be executed is dependent on the type of instruction to be executed and potentially, on the state of the condition flags as modified by the recently completed instructions. At RTL level, the next step decomposes into the sequence of steps given below. (1) TRo 1R < n.. m> The offset failed of the instruction enabled out to bus and TRo captures value. (2) TR1 TRO + PC; PC enabled out to bus, ALU adds TRo and PC (3) PC TR1 TR1 enabled out to bus, PC captures value. 7-Embedded system design Dec 2013.indd /08/ :02:14 AM

7 Embedded System Design Dec.2013/Jan a. Explain the external diagram of SRAM and write the timing diagram for read operation. (06 Marks) Ans: SRAM (static RAM) Supports lead as well as write operation. Fig. shown below presents the major I/O signals and a typical cell in an SRAM away. Then an six transistor per cell, two access transistors enable the cell for read and _ write. Write operation: A value is written into the cell by applying a signal to b i and b i through the write/ sense amplifiers. Asserting the world time causes the value to be written into the latch. _ Read operation: A value is read from the cell by first purchasing b i and b i to a voltage that is half way between a0 and a1. Asserting the word lines driver b i and b i to high and low or low and high depending on the value that has been stored. 1/0 V 1b b DD 1 1 Address OE CS R/W The SRAM Oustside and Inside Word Line Column Select R/W Chip Select Sense Amplifiers The values as sensed and amplified by the write /sense amplifier. Typical terming for read and a write operation is as shown below. SRAM Read Memory Address Read/Write Chip Select t read SRAM Write Memory Address Read/Write Chip Select t write Timing for the SRAM Read and Write Operations 7-Embedded system design Dec 2013.indd /08/ :02:14 AM

8 Dec.2013/Jan.2014 Embedded System Design 3. b. Explain associative mapping cache implementation. (06 Marks) Ans: The associative mapping cache implementation combines some of the simplicity of the direct mapping algorithm with some of the flexibility of the association algorithm. In this implementation, the entity at a specific index is expanded from a single block to multiple blocks, such a collection is called a set. The cache for a two way implementation takes on the form as illustrated in the figures below. Block 1 Block m Set 0 Set 1 Set 2 Set 3 Set n-1 Block set association cache Main memory address space is just organised as a collection of m blocks. The m blocks are then organized in a collection of a groups. The group member to which each block in assigned is computed as group Number = m mod n The set number in the cache corresponds to the main memory group number. Any block from main memory group i can be placed into cache set j. A ht is now searched associatively, the search in far less complex because of much smaller space. For current system Cache: 64 k with k blocks organized as 64 two - block bits. Main memory: 256 k words organized as 512 blocks. The resulting groups are as shown below. 256 K main memory organized into 64 groups comprising 512 blocks Block Group The tag tables will have 121 entries. Table show below illustrates the way main memory addresses are mapped to the cache memory. Set Number Tag Table Cache Main Memory Group Number Each Tag is 3 bits Tag Number 450 mod 64 = 2 Main memory to cache mapping 7-Embedded system design Dec 2013.indd /08/ :02:14 AM

9 Embedded System Design Dec.2013/Jan c. Write the inside and outside diagram for DRAM along with read and write operation also explain refresh operation. (08 Marks) Ans: Dynamic cell Word Line Column Select R/W Chip Select Sense Amplifier The DRAM inside In DRAM, there is only one transistor per cell. The lead and write operations use a single bit line. THE DRAM OUTSIDE I/O Address RAS CAS OE CS R/W The DRAM outside CAS or column address state is a clock and in a dynamic memories to control the input of column address to the memory. RAS or row address state in a clock used in dynamic memories to control the input of row addresses to the memory. Read operation: A value is read from the cell by first pre-changing bit to a voltage that is half way between a 0 and a 1. Asserting the world time enables the stored signal into bit. If the stored value is a logical 1, through change sharing, the value in line bit, will increases. Conversely, if the stored value is a logical 0, change sharing will cause the value on bit to decreases. The change in value is sensed and amplified by the write / sense amplifier. The read operation causes the capacitor to discharge. The sensed and amplified value is placed back on to the bit line. This is called a rewrite operation. Write operation: A value is written into the cell by applying a logical 0 or logical 1 to be through the writ sense amplifiers. Asserting the word line changes the capacitor if a logical 1 is to be stored and discharges it if a logical 0 is to be stored. 7-Embedded system design Dec 2013.indd /08/ :02:14 AM

10 Dec.2013/Jan.2014 Embedded System Design The timing diagram of DRAM read and write cycle is shown below: DRAM Read Memory Address Row Address Column Address RAS t RAS CAS t precharge R/W t access t cycle DRAM write Memory Address RAS Row Address t RAS Column Address CAS t precharge R/W Refresh operation: Dynamic memories only store data for short periods on time on the pararitis capacitor associated with a MOS transistor. If the charge stored on the capacitor is not replaced periodically, it will leak away, then by losing the data stored in the memory. Replacement is implemented by executing a read operation followed by a rewrite of the data back into the cell. Such replacement is called refresh cycles. The time between two refresh operations is called refresh time interval. 4. a. Write the flow diagram for waterfall and v life cycle models and briefly explain waterfall steps. (06 Marks) Ans: Common life cycle models are: a) Water fall b) V Cycle c) Spiral d) Rapid prototype Water fall model : The water fall modal represents a cycle specifically a series of steps appearing much like a water fall sequentially one below the next as shown in fig. below. Specification Review and Revise Primary Design Review and Revise Detailed Design Review and Revise Implementation Review and Revise 7-Embedded system design Dec 2013.indd /08/ :02:14 AM

11 Embedded System Design Dec.2013/Jan.2014 Successive steps are linked in a chain manner and each step is connected to the previous phase. Reverse connection provides an essential clarification backwards to ensure that the solution agree with and follows from the specification. With the water fall model, the recognition of problems can be delayed until late states of development when the cost of repair in higher. b) The V cycle model: specification Requirement Design development Verification and Validation Test and evaluation Implementation and maintains System Test Decompression Verification System integration System Specification Verification Performance test Design Primary Design Verification Integration test Implementation Verification Detailed Design Until test Code The V cycle is similar to the waterfall model except that it places greater emphasise on the importance of addressing testing activities up front instead of later in the life cycle. Each stage associates the development activity for that phase with a test or validation at the same level. Here if one fellows the sequence down the left hand side of the drawing, one can see that the specification and design procedure utilizes a top down model, when as implementation and test proceed from a bottom up as is reflected on the right hand side of the drawing shown below. The development concluder the design and design related test portion of the development cycle of the system with both a verification and a validation test against the original specification. c) The spiral model: The spiral model brings with good specification of the requirements. It then initiatively completes a little of each phase. Its philosophy is to start small enplou the risks develop a plan to deal with the risks and commit to an approach for the next iteration. The cycle continues until the product is complete. A simplified version of a spiral by cycle is as shown below. 7-Embedded system design Dec 2013.indd /08/ :02:15 AM

12 Dec.2013/Jan.2014 Embedded System Design Determine objectives cost Identify and Resolve risks start Evaluate alternatives Plan Next Iteration Release Develop Deliverable The spiral model is an improvement on the waterfall and V models because it provides for multiple builds as well as several opportunities for risk assessment and customer involvement. On the negative side it is elaborate, difficult to manage and does not keep all developers occupied during all of the phases. d) Rapid prototyping: The Rapid prototyping model is intended to provide rapid implementation of high level portion of both the software and hardware and the hardware only in the project. The approach allows developers to construct working portion of the hardware and software in incremental stages. Each stage consists of design code and unit test, integration test and delivery. The proto type is useful for both the designer and the customer. For the designer, it enables the early development of major prices of the intended functionality of system. The prototype can be either evolutionary or throw anyway. It has the advantages of having a working system early in the development process. To the effective however the rapid protyping approach requires careful planning at both the project management and designer levels. 4. b. Explain the characterizing and identifying the requirements of a system with respect to a digital counter. (06 Marks) Ans: Characterizing of any system begins with the following steps. 1. System input and outputs 2. Responsibilities Activities 3. Safety and Reliability System input and output: The system interacts with the real world through the entities. The inputs to the system are the outputs from environmental entities and the outputs from the system are the inputs to the environmental entities. Responsibilities Activities: Then the internal behaviour of the system is defined. It characterizes the effects of the system outputs on the environmental entities and the system's. Intended response to input from the environmental entities. It collaborates on how the system is used and to be used by the user. Safety and Reliability: Safety consideration should address: Safety guidelines, rules, or regulations under the governing agencies identified under the environment position of the specification. With respect to reliability one can specify The system uptime goals 7-Embedded system design Dec 2013.indd /08/ :02:15 AM

13 Embedded System Design Dec.2013/Jan.2014 Potential risks, factures and failure modes failure management strategy. System Requirement: Then the Basic Requirement of any system in described. Digital Counter Characterization: 1. The counter must have the ability to measure time intervals and frequency and to count events. 2. The frequencies are fixed but span a range of values. 3. The time intervals span a range of values and may be either periods or aperiodic, but they cannot be both. 4. The counter will support the users ability to manually select mode and measurement range for all inputs signals. 5. The counter will continue to make and display the selected attribute of the signal until power of the system is turned off or until the user makes another selection. 6. The counter will measure only one signal at a time. 7. An event can be modelled as a aperiodic time signal. 8. The design will be sufficiently flexible to allow futures inclusion. Counter Requirement 1. The counter should be manually operated with the ability to support remote operation in future. 2. Counter is to be low cost and flexible, so that it may be utilized in a variety of applications. 4. c. Write the hard ware architecture and data and control flow diagrams of a counter system and explain briefly the flow diagram. (08 Marks) Ans: The hardware architecture of counter is shown below. Display formattedmeas measvalueraw Microprocessor ROM RAM cmdfreq cmdtime cmdedge:(start,stop) Counter - Divider Chain and Control Clock system edge range mode Front Panel Controls Reset Signal to measure Power system The Hardware architecture of the Counter In the above design, the microprocessor, the display, the front panel controls, and the power system are hardware, were as the counter - divider chain and associated control could be implemented in software. Figures shown below is the data and control flow diagram for the counter system. 7-Embedded system design Dec 2013.indd /08/ :02:15 AM

14 Dec.2013/Jan.2014 Embedded System Design User Input Front Panel Input cmdavailable User Commands Measurement control cmdfreq cmdtime cmdedge meas Value Raw dataavailable meanvalueraw Master Control Output formattedmeas dataavailable Display Controls cmdavailable A data and control flow diagram for the counter system Figure above shows the major software tasks stand data and I/O in a data and control flow diagram. The front panel task is continuously checking the state of the port panel for unit input. A change in input is captured and passed to the display task and to the measurement task. The measurement task issues the appropriate commands to the external counter - divider chain control block. At the end of each measurement, the raw data is read from the counter - divider and passed to the output task. The output task properly formats the data and sends it to the display task for display on the front panel. The master control task manages the scheduling of all tasks and perform any necessary to use keeping or other duties. PART - B 5. a. Differentiate between, i) Program and process; ii) Process and threads iii) Light weight and heavy wight threads. (06 Marks) Ans: i) Program and process: A program is a set of instructions that are to perform a designated task, where as the process is a operation which takes the given instruction and performs the manipulations as per the code, called execution of instruction. A process is entirely dependent of a program. A process is a module that executes modules concurrently. They are separate loadable modules. Where as the program performs the tasks directly relating to an operation of a user like word processing, executing presentation software etc. ii) Process and threads: Both process and threads are independent sequences of execution. The only difference is that threads run in shared memory space, while processes run in separate memory spaces. iii) Light weight and heavy weigh threads: Heavy weight thread are enated to perform the work in parallel. Each heavy weight thread contains its own address space. Where as light weight thread used the same code section, data section and as resources. Therefore less over all resource is used but one draw back with light weight thread is that it may step on each other. 5. b. Describe: i) Reentrant code ii) Fore ground/back ground 7-Embedded system design Dec 2013.indd /08/ :02:15 AM

15 Embedded System Design Dec.2013/Jan.2014 iii) Multi threading system. (06 Marks) Ans: i) Reentrant code: Child process and consequently then thread share the same firm ware memory area. As a result, two different thread can be executing the same function at the same time. Functions using only local variables an inherently reentrant is they can be simultaneously called and executed in two or more contexts. Local variables are copied to the stack, and each invocation will get new copies. On the other hand functions that use global variables local to the process, variables passed by references, or shared resources are not reentrant. One must be particularly careful to ensure that all accesses to any common resources are co-ordinated. While designing one must be very careful to ensure that all accesser to any common resources are coordinated when designing application, one must make certain that one thread cannot corrupt the values of the variables in a second. It is good practice to make certain that all functions are reentrant. ii) Fore ground / Back ground system: The fore ground/back ground model for managing task execution, decompress the set of tasks comprising the application into two subsets called back ground tasks and fore ground tasks. The fore ground task are those initiated by interrupt or by a real - time constraint that must be write. They will be assigned to highest priority level in the system. In constant back ground tasks are non interrupted driven and are assigned the lower priority. Once started, the background task will typically run to completion, however, they can be interrupted or preempted by any fore ground tasks at time. The back ground tasks should includes all those that do not have time constraints. iii) Multi threading system: A process may execute multiple threads. When doing so, that parent process shares most of its resources with each of the threads. They are not separate processes but separate threads of execution within the same process. Each thread will have its own stack and status information. 5. c. Describe the task state transition with a diagram and TCB structure. Explain the function of the scheduled and dispatcher. (08 Marks) Ans: In a tasked band approach each process is represented in the operating system by a date structure called task control block. The TCB contain all the important information about the task and the block diagram of TCB is as shown below. Pointer State Process ID Program Counter Register contents Memory limits Open files etc A typical TCB contains following information Pointer Process ID and state Program counter CPU Register Scheduling information Memory management information 7-Embedded system design Dec 2013.indd /08/ :02:15 AM

16 Dec.2013/Jan.2014 Embedded System Design Scheduling information I/O states information In a tasked brand approach, each process is represented in the operating system by a data structure called a task control block (TCB). TCB allocation may by static or dynamic. Static allocation: This type of allocation is typically used in embedded systems with no memory management. Then an fined number of task control blocks, the memory is allocated at system generation time and placed in a dormant or unused static. When a task is initiated a TCB is created and the appropriate information is entered. The TCB is then placed into the ready state by the scheduler. From the ready state it will be moved to the execute static by the dispatcher. When the task terminates, the associated TCB is returned to the dormant state. Dynamic allocation: With dynamic allocation, a variable number of task control blocks can be allocated from the heap at run time. When a task is created, as was done with static allocation, the TCB is created, initialized, and placed into the ready static and scheduled by the scheduler. From the ready state, it will be moved to the execute state and given the cpu by dispatcher. When a Task is terminated the TCB memory is returned to heap storage. Dynamic allocation suggests an unlimited supply of TCB's. 1. Scheduler: The scheduler determine which task will run and when it will do so. 2. Despatcher: The despatcher performs the necessary operations to start the task. 6. a. Explain any 6 functions of an operating systems in brief. (06 Marks) Ans: The Kernal is the smallest portions of operating system that provides these functions: i) Process or task management: The central component of task management entails the creation and deletion of user and system processes as well as the suspension and resumption of such processes. ii) Memory management: Services include the tracking and control of which tasks an loaded into memory, monitoring which parts of memory are being used and by whom, administering dynamic memory if it is used, and managing caching schemes. iii) I/O system management: Management of system input and output can include a wide range of responsibilities. An embedded application must interact with grate variety of different devices. In more complex systems, such interactions occurs through a special piece of software called device driver. iv) File system management: File system management responsibility are diverted towards the creation, deletion and management of files and directories. v) System protection: Ensuring the protection of data and resources in the content of concurrent processes is an important and essential duty for the operating system. vi) Networking: Here it takes on the responsibility of managing distributed intra system communication and the remote scheduling of tasks. vii) Command Interputation: In embedded applications that support provisions for user interaction, the task is implemented via a variety of software devices supported by the OS that interact with the hardware I/O devices. As commands and directives come into the system, they must be passed, checked from grammatically accuracy, and diverted to the target task. 6. b. Describe initial model and high level model for OS architecture. (06 Marks) Ans: The operating system can be designed and implemented in following ways. 7-Embedded system design Dec 2013.indd /08/ :02:15 AM

17 Embedded System Design Dec.2013/Jan ) Operating system virtual machine. 2) Typical High level operating system architecture. 1) Operating system virtual machines. Most contemporary operating systems are designed and implemented as a hierarchy of what are called virtual machine, as shown in fig above. The only real machine that the various pieces of functionality with in the operating system see in the underlying physical microprocessor, specifically, the OS bus the cpu, the memory, and the concrete I/O devices. The hierarchy is designed such that each layer user the functions / operations and services of lower layer. The primary advantage of such an approach is increased modularity. (Embedded Application) Command Interface system I/O System and user memory management Inter task common CPU and resource scheduling / Dispatching Thread management Microprocessor Hardware and Hardware Resources. High level operating system architecture: (Embedded) application Command interface system 1/0 System and user memory management Inter task communication cpu and Resource scheduling / Despatching Third management Microprocessor Hardware and Hardware Resources A typical architecture for an operating system is as shown above. The higher level layers have access to lower levels through system calls and hardware instructions. The inirting calling interface between level is retained which providing access to the physical hardware below. With such capability, an interface can be made to appear as if it is a machine executing a specific set of instructions as defined by the API. 6. c. Write the algorithm for a simple OS kernal, using 1 language notation for 3 synchronous task using TCB only. The 3 tasks use a common data buffer for read, increment and display operation. (08 Marks) Ans: // Building a simple OS kernel-step 1 #include <stdlo.h> // Declare the prototypes for the tasks 7-Embedded system design Dec 2013.indd /08/ :02:15 AM

18 Dec.2013/Jan.2014 Embedded System Design Void get (void* anumber); void increment (void*anumber); void display (void*anumber); void main (void) { Int 1 = 0; Int data; Int*aPtr = &data; //Input task //computation task // output task //queue index // declare a shared data //point to it void (*queue [3])(void); //declare queue as an array of pointer to // functions taking an arg of type void* queue [0] = get; //enter the tasks into the queue queue [1] = increment; queue[2] = display; while(1) { queue [1] ((void*) aptr); // dispatch each task in turn 1 = (1 + 1) % 3; } return; } void get (void* anumber) // perform Input operation { printf ("Enter a number 0..9"); *(int*) anumber = getchar ( ); get char ( ); // discard cr *(int*) anumber = '0'; // convert to decimal from ascii return; } void increment (void* anumber) //perform computation { int*aptr = (int*) a Number; (*aptr)++; return; } void display (void* anumber) //perform output operation { printf("the result is: %d\n", *(int*) anumber); 7-Embedded system design Dec 2013.indd /08/ :02:15 AM

19 Embedded System Design Dec.2013/Jan.2014 return; } 7. a. Write the Amdahl's law limitations for performance improvement / optimization. Consider a system with the following characteristics. i) The task to be improved takes 200 time units and the goal is to reduce the execution time to 160 time units. The algorithm under consideration takes so time units. Determine the unknown parameter value in the equation and write the inference. ii) If the goal is to reduce the execution time to 100 time units for the values in case (i). Then determine the value unknown parameter values in the equation and write the inference. (06 Marks) Ans: Ttotal Ttotal = Timproved ( Ttotal Tcomponent ) + Tcomponent T total = system metric prior to improvement. T improved = system metric after improvement T component = contribution of the component to be improved to the system metric. n = The amount of the improvement i) = ( ) + n n = 2 The analysis shows that to meet the new performance goal the algorithm execution speed will have to be demand ii) = ( ) + n n = 4 The algorithm will have to run in negative time to meet the new specification. Clearly this is a non casual system. 7. b. Write a C function to determine the sense of the element of an array and analyze it line by line for its time complexity. (06 Marks) Ans: 1. int total (int my Array [ ], int n) 2. { 3. int sum = 0; 4. int i = 0; 5. for (i = 0; i < n; i ++) 6. { 7. sum = sum + my Array [ i ]; 8. } 9. return sum; 7-Embedded system design Dec 2013.indd /08/ :02:15 AM

20 Dec.2013/Jan.2014 Embedded System Design 10. } Analysis of code: Line 1: Two push onto the stack operations - This happens once. 2 operations Line 3: One assignment operation - This happens once 1 operation. Line 4: One assignment operation - This happens once 1 operation Line 5: Three operation - the initialization of i happens one time, the comparison against n happens n times, and the increment of i happens n times. 2 * n + 1 operations. Line 7: Three operations - The index operations, the sum calculations, and the assignment to sum. Each operation happens n times. 3 * n operations Line 9: One return operation- This happens 1 time 1 operation Final: 5 * n + 6 operations. The number of operations to execute the algorithm depends directly on the size of the container. Thus we can write a complexity function as. f(n) = 5 n c. Explain the Big - O notation used comparing the algorithms, common bounds Big O - arithmetic. (08 Marks) Ans: Big O arithmetic is hand on following rules order common function from smallest to longest 1, log (N), N, N log(n), N 2, N 3,...2 N, 3 N Ignore constant multipliers 300 N + SN N = 0 (N + N N ) Ignore every thing except the higher order times N + N N = 0(2 N ) 8. a. Write and analyze a linear search algorithm for its term complexity. (06 Marks) Ans: The linear search algorithm is given below //Return index of x if found, or - 1 if not 1. int find (int) A[ ], int size, int (x) { 2. unsigned char gotit = 1; 3. unsigned int 1; 4. for (1 = 0; i < size & & gotit < 0; i ++) { 5. if (A [i] = = x) 6. gotit = 1; 7-Embedded system design Dec 2013.indd /08/ :02:16 AM

21 Embedded System Design Dec.2013/Jan.2014 } 7. return gotit; } Figure: Analyzing a linear search Algorithm. The worst case performance of the algorithm will be assessed first. Line 1: Three push onto stack operations - this happens once. 3 operations Line 2: One assignment operation - this happens once. 1 operation Line 3: Once assignment operation - this happens once 1 operation Line 4: Five operations - the initialization of i happens one time against size, the comparison against 0, the AND operation size times each, and the increment of i happen size times. 3 + size + 2 operations Line 5: One comparison operation - this happens size times. size operations Line 6: One assignment operation - this happens once. 1 operation Line 7: One return operation - this happens once. 1 operation Final 5 * size + 8 operations The worst case complexity is 0(N) when N is the size of the contains. The best case is performance is achieved when the target value is always the first entry in the container. 8. b. The operation to be performed is i) C = a + b ii) C = d + e if a = = b else C = d - e. Write the C language construct and assembly language statement for the above 2 cases separately and calculate the total tense required if push / pop takes 800 nsec, arithmetic operation/load/store/cmp takes 100 nsec and the conditional branch takes 700 nsec. (06 Marks) Ans: i) C = a + b C language construct: int a = 10; int b = 20; C = a + b; Assembly language statement 1dbse R0, #0AH. load 10 into a temp reg 100 ns Push R0. Push the local variable onto stack 800 ns 1dbse R3, #1HH. load 20 into a temp variable 100 ns Push R2 Push the local variable onto the stack 800 ns add R0, R2 C a + b 100 ns Push R0. Push the local variable onto stack. 800 ns Total: 2700 ns ii) C level statement if (a = = b) 7-Embedded system design Dec 2013.indd /08/ :02:16 AM

22 Dec.2013/Jan.2014 Embedded System Design C = d + e; else C = d e; The assembler level cmp R 1, R 2 compare R 1 and R nsec 002 if they are not equal branch to lable nsec if Branch taken 100ns if branch not taken add R3, R4, R5 R3 R4 + R5 100 nsec 0003 go 700 nsec Sub R3, R4, R5 R3 R nsec Total : 1700 (if Branch taken failed) (if branch not taken) 8. c. Describe memory loading with equation, figure and an example. (08 Marks) Ans: Memory loading is define as the percentage of usable memory being devoted to that application. The memory map is one useful step for allocation and usage of available memory. A typical memory map is as shown below. Memory mapped I/O and DMA Instruction (Firm vace) Ram Stack space System memory A Typical memory map The total memory loading will be the sum of the individual loading for instructions, stack and RAM. The loading is given by MT = M i.pi + M R.PR + M S.PS The value M i reflect - the memory loading for each of portion of memory. The values P i represents the percentage of total memory allocated for the program. M T will be expressed as a percentage. For example: Let the system be implemented as follows M J - 15 mega bytes M R kilo bytes M S kilo bytes P 1-55 % P R - 33% P S - 10% MT = MT = 54% 7-Embedded system design Dec 2013.indd /08/ :02:16 AM