Concocting an Instruction Set

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1 Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter L03 Instruction Set 1

2 A General-Purpose Computer The von Neumann Model Many architectural approaches to the general purpose computer have been explored. The one on which nearly all modern, practical computers is based was proposed by John von Neumann in the late 1940s. Its major components are: L03 Instruction Set 2

3 A General-Purpose Computer The von Neumann Model Many architectural approaches to the general purpose computer have been explored. The one on which nearly all modern, practical computers is based was proposed by John von Neumann in the late 1940s. Its major components are: Central Processing Unit Central Processing Unit (CPU): A device which fetches, interprets, and executes a specified set of operations called Instructions. L03 Instruction Set 3

4 A General-Purpose Computer The von Neumann Model Many architectural approaches to the general purpose computer have been explored. The one on which nearly all modern, practical computers is based was proposed by John von Neumann in the late 1940s. Its major components are: Central Processing Unit Main Memory Central Processing Unit (CPU): A device which fetches, interprets, and executes a specified set of operations called Instructions. Memory: storage of N words of W bits each, where W is a fixed architectural parameter, and N can be expanded to meet needs. L03 Instruction Set 4

5 A General-Purpose Computer The von Neumann Model Many architectural approaches to the general purpose computer have been explored. The one on which nearly all modern, practical computers is based was proposed by John von Neumann in the late 1940s. Its major components are: Input/ Output Central Processing Unit Main Memory Central Processing Unit (CPU): A device which fetches, interprets, and executes a specified set of operations called Instructions. Memory: storage of N words of W bits each, where W is a fixed architectural parameter, and N can be expanded to meet needs. I/O: Devices for communicating with the outside world. L03 Instruction Set 5

6 Anatomy of an Instruction L03 Instruction Set 6

7 Anatomy of an Instruction add $t0, $t1, $t2 L03 Instruction Set 7

8 Anatomy of an Instruction Computers execute a set of primitive operations called instructions Instructions specify an operation and its operands (the necessary variables to perform the operation) Types of operands: immediate, source, and destination add $t0, $t1, $t2 L03 Instruction Set 8

9 Anatomy of an Instruction Computers execute a set of primitive operations called instructions Instructions specify an operation and its operands (the necessary variables to perform the operation) Types of operands: immediate, source, and destination Operation add $t0, $t1, $t2 L03 Instruction Set 9

10 Anatomy of an Instruction Computers execute a set of primitive operations called instructions Instructions specify an operation and its operands (the necessary variables to perform the operation) Types of operands: immediate, source, and destination Operation add $t0, $t1, $t2 Operands (variables, arguments, etc.) L03 Instruction Set 10

11 Anatomy of an Instruction Computers execute a set of primitive operations called instructions Instructions specify an operation and its operands (the necessary variables to perform the operation) Types of operands: immediate, source, and destination Operation add $t0, $t1, $t2 Operands (variables, arguments, etc.) Source Operands L03 Instruction Set 11

12 Anatomy of an Instruction Computers execute a set of primitive operations called instructions Instructions specify an operation and its operands (the necessary variables to perform the operation) Types of operands: immediate, source, and destination Operation add $t0, $t1, $t2 Operands (variables, arguments, etc.) Source Operands Destination Operand L03 Instruction Set 12

13 Anatomy of an Instruction Computers execute a set of primitive operations called instructions Instructions specify an operation and its operands (the necessary variables to perform the operation) Types of operands: immediate, source, and destination Operation add $t0, $t1, $t2 Operands (variables, arguments, etc.) Source Operands Destination Operand addi $t0, $t1, 1 L03 Instruction Set 13

14 Anatomy of an Instruction Computers execute a set of primitive operations called instructions Instructions specify an operation and its operands (the necessary variables to perform the operation) Types of operands: immediate, source, and destination Operation add $t0, $t1, $t2 addi $t0, $t1, 1 Operands (variables, arguments, etc.) Source Operands Destination Operand Immediate Operand L03 Instruction Set 14

15 Anatomy of an Instruction Computers execute a set of primitive operations called instructions Instructions specify an operation and its operands (the necessary variables to perform the operation) Types of operands: immediate, source, and destination Why the $ on some operands? $X is a convention to denote the contents of a temporary variable named X, whereas immediate operands indicate the specified value Operation add $t0, $t1, $t2 addi $t0, $t1, 1 Operands (variables, arguments, etc.) Source Operands Destination Operand Immediate Operand L03 Instruction Set 15

16 Meaning of an Instruction Operations are abbreviated into opcodes (1-4 letters) Instructions are specified with a very regular syntax First an opcode followed by arguments Usually the destination is next, then source arguments (This is not strictly the case, but it is generally true) Why this order? Analogy to high-level language like Java or C L03 Instruction Set 16

17 Meaning of an Instruction Operations are abbreviated into opcodes (1-4 letters) Instructions are specified with a very regular syntax First an opcode followed by arguments Usually the destination is next, then source arguments (This is not strictly the case, but it is generally true) Why this order? Analogy to high-level language like Java or C add $t0, $t1, $t2 L03 Instruction Set 17

18 Meaning of an Instruction Operations are abbreviated into opcodes (1-4 letters) Instructions are specified with a very regular syntax First an opcode followed by arguments Usually the destination is next, then source arguments (This is not strictly the case, but it is generally true) Why this order? Analogy to high-level language like Java or C add $t0, $t1, $t2 implies int t0, t1, t2 t0 = t1 + t2 L03 Instruction Set 18

19 Meaning of an Instruction Operations are abbreviated into opcodes (1-4 letters) Instructions are specified with a very regular syntax First an opcode followed by arguments Usually the destination is next, then source arguments (This is not strictly the case, but it is generally true) Why this order? Analogy to high-level language like Java or C add $t0, $t1, $t2 implies int t0, t1, t2 t0 = t1 + t2 The instruction syntax provides operands in the same order as you would expect in a statement from a high level language. L03 Instruction Set 19

20 Generally Being the Machine! Instructions are executed sequentially from a list Instructions execute after all previous instructions have completed, therefore their results are available to the next instruction But, you may see exceptions to these rules Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 Variables $t0: 0 $t1: 6 $t2: 8 $t3: 10 L03 Instruction Set 20

21 Generally Being the Machine! Instructions are executed sequentially from a list Instructions execute after all previous instructions have completed, therefore their results are available to the next instruction But, you may see exceptions to these rules Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 Variables $t0: 0 $t1: 6 $t2: 8 $t3: 10 L03 Instruction Set 21

22 Generally Being the Machine! Instructions are executed sequentially from a list Instructions execute after all previous instructions have completed, therefore their results are available to the next instruction But, you may see exceptions to these rules Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 Variables $t0: 0 12 $t1: 6 $t2: 8 $t3: 10 L03 Instruction Set 22

23 Generally Being the Machine! Instructions are executed sequentially from a list Instructions execute after all previous instructions have completed, therefore their results are available to the next instruction But, you may see exceptions to these rules Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 Variables $t0: 0 12 $t1: 6 $t2: 8 $t3: 10 L03 Instruction Set 23

24 Generally Being the Machine! Instructions are executed sequentially from a list Instructions execute after all previous instructions have completed, therefore their results are available to the next instruction But, you may see exceptions to these rules Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 Variables $t0: $t1: 6 $t2: 8 $t3: 10 L03 Instruction Set 24

25 Generally Being the Machine! Instructions are executed sequentially from a list Instructions execute after all previous instructions have completed, therefore their results are available to the next instruction But, you may see exceptions to these rules Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 Variables $t0: $t1: 6 $t2: 8 $t3: 10 L03 Instruction Set 25

26 Generally Being the Machine! Instructions are executed sequentially from a list Instructions execute after all previous instructions have completed, therefore their results are available to the next instruction But, you may see exceptions to these rules Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 Variables $t0: $t1: 6 $t2: 8 $t3: 10 L03 Instruction Set 26

27 Generally Being the Machine! Instructions are executed sequentially from a list Instructions execute after all previous instructions have completed, therefore their results are available to the next instruction But, you may see exceptions to these rules Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 Variables $t0: $t1: 6 $t2: 8 $t3: 10 L03 Instruction Set 27

28 Generally Being the Machine! Instructions are executed sequentially from a list Instructions execute after all previous instructions have completed, therefore their results are available to the next instruction But, you may see exceptions to these rules Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 $t0: 0 $t1: 6 $t2: 8 $t3: 10 Variables L03 Instruction Set 28

29 Generally Being the Machine! Instructions are executed sequentially from a list Instructions execute after all previous instructions have completed, therefore their results are available to the next instruction But, you may see exceptions to these rules Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 What is this program doing? Variables $t0: $t1: 6 42 $t2: 8 $t3: 10 L03 Instruction Set 29

30 Analyzing the Machine! Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 $t0: $t1: $t2: $t3: Variables w x y z L03 Instruction Set 30

31 Analyzing the Machine! Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 $t0: $t1: $t2: $t3: Variables w x y z L03 Instruction Set 31

32 Analyzing the Machine! Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 $t0: $t1: $t2: $t3: Variables w 2x x y z L03 Instruction Set 32

33 Analyzing the Machine! Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 $t0: $t1: $t2: $t3: Variables w 2x x y z L03 Instruction Set 33

34 Analyzing the Machine! Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 $t0: $t1: $t2: $t3: Variables w 2x4x x y z L03 Instruction Set 34

35 Analyzing the Machine! Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 $t0: $t1: $t2: $t3: Variables w 2x4x x y z L03 Instruction Set 35

36 Analyzing the Machine! Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 $t0: $t1: $t2: $t3: Variables w 2x4x 8x x y z L03 Instruction Set 36

37 Analyzing the Machine! Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 $t0: $t1: $t2: $t3: Variables w 2x4x 8x x y z L03 Instruction Set 37

38 Analyzing the Machine! Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 $t0: $t1: $t2: $t3: Variables w 2x4x 8x x 7x y z L03 Instruction Set 38

39 Analyzing the Machine! Repeat the process treating the variables as unknowns Knowing what the program does allows us to write down its specification, and give it a meaningful name The instruction sequence is now a general purpose tool Instructions add $t0, $t1, $t1 add $t0, $t0, $t0 add $t0, $t0, $t0 sub $t1, $t0, $t1 $t0: $t1: $t2: $t3: Variables w 2x4x 8x x 7x y z L03 Instruction Set 39

40 Analyzing the Machine! Repeat the process treating the variables as unknowns Knowing what the program does allows us to write down its specification, and give it a meaningful name The instruction sequence is now a general purpose tool Instructions Variables times7: add $t0, $t1, $t1 $t0: w 2x4x 8x add $t0, $t0, $t0 $t1: x 7x add $t0, $t0, $t0 $t2: y sub $t1, $t0, $t1 $t3: z L03 Instruction Set 40

41 Looping the Flow Operations to change the flow of sequential execution A jump instruction with opcode j The operand refers to a label of some other instruction Instructions Variables times7: add $t0, $t1, $t1 $t0: w add $t0, $t0, $t0 $t1: x add $t0, $t0, $t0 $t2: y sub $t1, $t0, $t1 $t3: z L03 Instruction Set 41

42 Looping the Flow Operations to change the flow of sequential execution A jump instruction with opcode j The operand refers to a label of some other instruction Instructions Variables times7: add $t0, $t1, $t1 $t0: w add $t0, $t0, $t0 $t1: x add $t0, $t0, $t0 $t2: y sub $t1, $t0, $t1 $t3: z j times7 L03 Instruction Set 42

43 Looping the Flow Operations to change the flow of sequential execution A jump instruction with opcode j The operand refers to a label of some other instruction Instructions Variables times7: add $t0, $t1, $t1 $t0: w 8x add $t0, $t0, $t0 $t1: x 7x add $t0, $t0, $t0 $t2: y sub $t1, $t0, $t1 $t3: z j times7 L03 Instruction Set 43

44 Looping the Flow Operations to change the flow of sequential execution A jump instruction with opcode j The operand refers to a label of some other instruction Instructions Variables times7: add $t0, $t1, $t1 $t0: w 8x 56x add $t0, $t0, $t0 $t1: x 7x49x add $t0, $t0, $t0 $t2: y sub $t1, $t0, $t1 $t3: z j times7 L03 Instruction Set 44

45 Looping the Flow Operations to change the flow of sequential execution A jump instruction with opcode j The operand refers to a label of some other instruction Instructions Variables times7: add $t0, $t1, $t1 $t0: w 8x 56x 392x add $t0, $t0, $t0 $t1: x 7x49x 343x add $t0, $t0, $t0 $t2: y sub $t1, $t0, $t1 $t3: z j times7 L03 Instruction Set 45

46 Looping the Flow Operations to change the flow of sequential execution A jump instruction with opcode j The operand refers to a label of some other instruction Instructions Variables times7: add $t0, $t1, $t1 $t0: w 8x 56x 392x add $t0, $t0, $t0 An infinite loop $t1: x 7x49x 343x add $t0, $t0, $t0 $t2: y sub $t1, $t0, $t1 $t3: z j times7 L03 Instruction Set 46

47 Open Issues in our Simple Model WHERE are INSTRUCTIONS stored? HOW are instructions represented? WHERE are VARIABLES stored? How are labels associated with particular instructions? How do you access more complicated variable types like Arrays? Structures? Objects? Where does a program start executing? How does it stop? L03 Instruction Set 47

48 The Stored-Program Computer The von Neumann architecture addresses these issues of our simple programmable machine example: Instructions and Data are stored in a common memory Sequential semantics: To the programmer all instructions appear to be executed sequentially L03 Instruction Set 48

49 The Stored-Program Computer The von Neumann architecture addresses these issues of our simple programmable machine example: Instructions and Data are stored in a common memory Sequential semantics: To the programmer all instructions appear to be executed sequentially Key idea: Memory holds not only data, but coded instructions that make up a program. CPU fetches and executes instructions from memory... The CPU is a H/W interpreter Program IS simply data for this interpreter Central Processing Unit Main memory: Single expandable resource pool - constrains both data and program size - don t need to make separate decisions of how large of a program or data memory to buy Main Memory instruction instruction instruction data data data L03 Instruction Set 49

50 Internal storage Anatomy of a von Neumann Computer Data Paths control status Control Unit address data MEMORY address instructions L03 Instruction Set 50

51 Internal storage Anatomy of a von Neumann Computer Data Paths control status Control Unit address data MEMORY address instructions dest asel bsel fn ALU Cc s L03 Instruction Set 51

52 Internal storage Anatomy of a von Neumann Computer Data Paths control status Control Unit address data MEMORY address instructions dest registers asel bsel fn ALU Cc s L03 Instruction Set 52

53 Internal storage Anatomy of a von Neumann Computer Data Paths control status Control Unit address data MEMORY address instructions dest registers asel bsel operations fn ALU Cc s L03 Instruction Set 53

54 Internal storage Anatomy of a von Neumann Computer Data Paths control status Control Unit address data MEMORY address instructions dest registers asel bsel More about this stuff later! operations fn ALU Cc s L03 Instruction Set 54

55 Internal storage Anatomy of a von Neumann Computer Data Paths control status Control Unit address data MEMORY address instructions dest registers +1 PC R1 R2+R3 INSTRUCTIONS coded as binary data asel bsel More about this stuff later! PROGRAM COUNTER or PC: Address of next instruction to be executed operations fn ALU Cc s logic to translate instructions into control signals for data path L03 Instruction Set 55

56 Instruction Set Architecture (ISA) Encoding of instructions raises some interesting choices... Tradeoffs: performance, compactness, programmability Uniformity. Should different instructions Be the same size? Take the same amount of time to execute? Trend: Uniformity. Affords simplicity, speed, pipelining. Complexity. How many different instructions? What level operations? Level of support for particular software operations: array indexing, procedure calls, polynomial evaluate, etc Reduced Instruction Set Computer (RISC) philosophy: simple instructions, optimized for speed Mix of Engineering & Art... Trial (by simulation) is our best technique for making choices! Our representative example: the MIPS architecture! L03 Instruction Set 56

57 MIPS Programming Model a representative simple RISC machine PC r0 r1 r2... Processor State (inside the CPU) bit words 00 Addresses Main Memory bit words (4 bytes) next instruction 0 In we ll use a clean and sufficient subset of the MIPS-32 core Instruction set. Fetch/Execute loop: fetch Mem[PC] PC = PC + 4 execute fetched instruction (may change PC!) repeat! r31 General Registers: A small scratchpad of frequently used or temporary variables MIPS uses byte memory addresses. However, each instruction is 32-bits wide, and *must* be aligned on a multiple of 4 (word) address. Each word contains four 8-bit bytes. Addresses of consecutive instructions (words) differ by 4. L03 Instruction Set 57

58 Some MIPs Memory Nits Memory locations are 32 bits wide BUT, they are addressable in different-sized chunks 8-bit chunks (bytes) 16-bit chunks (shorts) 32-bit chunks (words) Addr 64-bit chunks (longs/double) 0: We also frequently need 4: access to individual bits! 8: (Instructions help to do this) Every BYTE has a unique address (MIPS is a byte-addressable machine) Every instruction is one word 12: L03 Instruction Set 58

59 Some MIPs Memory Nits Memory locations are 32 bits wide BUT, they are addressable in different-sized chunks 8-bit chunks (bytes) 16-bit chunks (shorts) 32-bit chunks (words) Addr 64-bit chunks (longs/double) 0: We also frequently need 4: access to individual bits! 8: (Instructions help to do this) Every BYTE has a unique address (MIPS is a byte-addressable machine) Every instruction is one word 12: byte3 byte2 byte1 byte L03 Instruction Set 59

60 Some MIPs Memory Nits Memory locations are 32 bits wide BUT, they are addressable in different-sized chunks 8-bit chunks (bytes) 16-bit chunks (shorts) 32-bit chunks (words) Addr 64-bit chunks (longs/double) 0: We also frequently need 4: access to individual bits! 8: (Instructions help to do this) Every BYTE has a unique address (MIPS is a byte-addressable machine) Every instruction is one word 12: short short0 byte3 byte2 byte1 byte L03 Instruction Set 60

61 Some MIPs Memory Nits Memory locations are 32 bits wide BUT, they are addressable in different-sized chunks 8-bit chunks (bytes) 16-bit chunks (shorts) 32-bit chunks (words) Addr 64-bit chunks (longs/double) 0: We also frequently need 4: access to individual bits! 8: (Instructions help to do this) Every BYTE has a unique address (MIPS is a byte-addressable machine) Every instruction is one word 12: short short0 byte3 byte2 byte1 byte long0 long8 L03 Instruction Set 61

62 Some MIPs Memory Nits Memory locations are 32 bits wide BUT, they are addressable in different-sized chunks 8-bit chunks (bytes) 16-bit chunks (shorts) 32-bit chunks (words) Addr 64-bit chunks (longs/double) 0: We also frequently need 4: access to individual bits! 8: (Instructions help to do this) Every BYTE has a unique address (MIPS is a byte-addressable machine) Every instruction is one word 12: short short0 byte3 byte2 byte1 byte long0 long8 L03 Instruction Set 62

63 MIPS Register Nits There are 32 named registers [$0, $1,. $31] The operands of *all* ALU instructions are registers This means to operate on a variables in memory you must: Load the value/values from memory into a register Perform the instruction Store the result back into memory Going to and from memory can be expensive (4x to 20x slower than operating on a register) Net effect: Keep variables in registers as much as possible! 2 registers have H/W specific side-effects (ex: $0 always contains the value 0 more later) 4 registers are dedicated to specific tasks by convention 26 are available for general use Further conventions delegate tasks to other registers L03 Instruction Set 63

64 MIPS Instruction Formats All MIPs instructions fit in a single 32-bit word. Every instruction includes various fields that encode combinations of a 6-bit operation or OPCODE specifying one of < 64 basic operations escape codes to enable extended functions several 5-bit OPERAND fields, for specifying the sources and destination of the operation, usually one of the 32 registers Embedded constants ( immediate values) of various sizes, 16-bits, 5-bits, and 26-bits. Sometimes treated as signed values, sometimes not. There are three basic instruction formats: L03 Instruction Set 64

65 MIPS Instruction Formats All MIPs instructions fit in a single 32-bit word. Every instruction includes various fields that encode combinations of a 6-bit operation or OPCODE specifying one of < 64 basic operations escape codes to enable extended functions several 5-bit OPERAND fields, for specifying the sources and destination of the operation, usually one of the 32 registers Embedded constants ( immediate values) of various sizes, 16-bits, 5-bits, and 26-bits. Sometimes treated as signed values, sometimes not. There are three basic instruction formats: R-type, 3 register operands (2 sources, destination) OP r s r t r d L03 Instruction Set 65

66 MIPS Instruction Formats All MIPs instructions fit in a single 32-bit word. Every instruction includes various fields that encode combinations of a 6-bit operation or OPCODE specifying one of < 64 basic operations escape codes to enable extended functions several 5-bit OPERAND fields, for specifying the sources and destination of the operation, usually one of the 32 registers Embedded constants ( immediate values) of various sizes, 16-bits, 5-bits, and 26-bits. Sometimes treated as signed values, sometimes not. There are three basic instruction formats: R-type, 3 register operands (2 sources, destination) OP r s r t r d func L03 Instruction Set 66

67 MIPS Instruction Formats All MIPs instructions fit in a single 32-bit word. Every instruction includes various fields that encode combinations of a 6-bit operation or OPCODE specifying one of < 64 basic operations escape codes to enable extended functions several 5-bit OPERAND fields, for specifying the sources and destination of the operation, usually one of the 32 registers Embedded constants ( immediate values) of various sizes, 16-bits, 5-bits, and 26-bits. Sometimes treated as signed values, sometimes not. There are three basic instruction formats: R-type, 3 register operands (2 sources, destination) OP r s r t r d shamt func L03 Instruction Set 67

68 MIPS Instruction Formats All MIPs instructions fit in a single 32-bit word. Every instruction includes various fields that encode combinations of a 6-bit operation or OPCODE specifying one of < 64 basic operations escape codes to enable extended functions several 5-bit OPERAND fields, for specifying the sources and destination of the operation, usually one of the 32 registers Embedded constants ( immediate values) of various sizes, 16-bits, 5-bits, and 26-bits. Sometimes treated as signed values, sometimes not. There are three basic instruction formats: R-type, 3 register operands (2 sources, destination) I-type, 2 register operands, 16-bit literal constant OP r s r t r d shamt func OP r s r t 16-bit constant L03 Instruction Set 68

69 MIPS Instruction Formats All MIPs instructions fit in a single 32-bit word. Every instruction includes various fields that encode combinations of a 6-bit operation or OPCODE specifying one of < 64 basic operations escape codes to enable extended functions several 5-bit OPERAND fields, for specifying the sources and destination of the operation, usually one of the 32 registers Embedded constants ( immediate values) of various sizes, 16-bits, 5-bits, and 26-bits. Sometimes treated as signed values, sometimes not. There are three basic instruction formats: R-type, 3 register operands (2 sources, destination) I-type, 2 register operands, 16-bit literal constant J-type, no register operands, 26-bit literal constant OP r s r t r d shamt func OP r s r t 16-bit constant OP 26-bit constant L03 Instruction Set 69

70 MIPS ALU Operations Sample coded operation: ADD instruction R-type: L03 Instruction Set 70

71 MIPS ALU Operations Sample coded operation: ADD instruction R-type: op = 0x00 dictating an ALU function L03 Instruction Set 71

72 MIPS ALU Operations Sample coded operation: ADD instruction R-type: op = 0x00 dictating an ALU function func = 0x20 dictating an add L03 Instruction Set 72

73 MIPS ALU Operations Sample coded operation: ADD instruction R-type: op = 0x00 dictating an ALU function rs = 11 Reg[11] source func = 0x20 dictating an add L03 Instruction Set 73

74 MIPS ALU Operations Sample coded operation: ADD instruction R-type: op = 0x00 dictating an ALU function rs = 11 Reg[11] source rt = 9 Reg[9] source func = 0x20 dictating an add L03 Instruction Set 74

75 MIPS ALU Operations Sample coded operation: ADD instruction R-type: op = 0x00 dictating an ALU function rs = 11 Reg[11] source rt = 9 Reg[9] source rd = 10 Reg[10] destination func = 0x20 dictating an add L03 Instruction Set 75

76 MIPS ALU Operations Sample coded operation: ADD instruction R-type: op = 0x00 dictating an ALU function rs = 11 Reg[11] source rt = 9 Reg[9] source rd = 10 Reg[10] destination func = 0x20 dictating an add unused fields are set to 0 L03 Instruction Set 76

77 MIPS ALU Operations Sample coded operation: ADD instruction R-type: op = 0x00 dictating an ALU function rs = 11 Reg[11] source rt = 9 Reg[9] source rd = 10 Reg[10] destination What we prefer to write: add $10, $11, $9 func = 0x20 dictating an add unused fields are set to 0 ( assembly language ) L03 Instruction Set 77

78 MIPS ALU Operations Sample coded operation: ADD instruction R-type: op = 0x00 dictating an ALU function rs = 11 Reg[11] source rt = 9 Reg[9] source rd = 10 Reg[10] destination What we prefer to write: add $10, $11, $9 func = 0x20 dictating an add unused fields are set to 0 References to register contents are prefixed by a $ to distinguish them from constants or memory addresses ( assembly language ) L03 Instruction Set 78

79 MIPS ALU Operations Sample coded operation: ADD instruction R-type: op = 0x00 dictating an ALU function rs = 11 Reg[11] source rt = 9 Reg[9] source rd = 10 Reg[10] destination What we prefer to write: add $10, $11, $9 The convention with MIPS assembly language is to specify the destination operand first, followed by source operands. func = 0x20 dictating an add unused fields are set to 0 References to register contents are prefixed by a $ to distinguish them from constants or memory addresses ( assembly language ) L03 Instruction Set 79

80 MIPS ALU Operations Sample coded operation: ADD instruction R-type: op = 0x00 dictating an ALU function What we prefer to write: add $10, $11, $9 add rd, rs, rt: rs = 11 Reg[11] source rt = 9 Reg[9] source The convention with MIPS assembly language is to specify the destination operand first, followed by source operands. Reg[rd] = Reg[rs] + Reg[rt] Add the contents of rs to the contents of rt; store the result in rd rd = 10 Reg[10] destination func = 0x20 dictating an add unused fields are set to 0 References to register contents are prefixed by a $ to distinguish them from constants or memory addresses ( assembly language ) L03 Instruction Set 80

81 MIPS ALU Operations Sample coded operation: ADD instruction R-type: op = 0x00 dictating an ALU function What we prefer to write: add $10, $11, $9 add rd, rs, rt: rs = 11 Reg[11] source rt = 9 Reg[9] source The convention with MIPS assembly language is to specify the destination operand first, followed by source operands. Reg[rd] = Reg[rs] + Reg[rt] Add the contents of rs to the contents of rt; store the result in rd rd = 10 Reg[10] destination func = 0x20 dictating an add unused fields are set to 0 References to register contents are prefixed by a $ to distinguish them from constants or memory addresses ( assembly language ) Similar instructions for other ALU operations: arithmetic: add, sub, addu, subu, mult, multu, div, divu compare: slt, sltu logical: and, or, xor, nor shift: sll, srl, sra, sllv, srav, srlv L03 Instruction Set 81

82 MIPS Shift Operations Sample coded operation: SHIFT LOGICAL LEFT instruction R-type: Assembly: sll $2, $2, 4 sll rd, rt, shamt: Reg[rd] = Reg[rt] << shamt Shift the contents of rt to the left by shamt; store the result in rd L03 Instruction Set 82

83 MIPS Shift Operations Sample coded operation: SHIFT LOGICAL LEFT instruction R-type: op = 0x00 dictating an ALU function Assembly: sll $2, $2, 4 sll rd, rt, shamt: Reg[rd] = Reg[rt] << shamt Shift the contents of rt to the left by shamt; store the result in rd L03 Instruction Set 83

84 MIPS Shift Operations Sample coded operation: SHIFT LOGICAL LEFT instruction R-type: op = 0x00 dictating an ALU function func = 0x00 dictating an sll Assembly: sll $2, $2, 4 sll rd, rt, shamt: Reg[rd] = Reg[rt] << shamt Shift the contents of rt to the left by shamt; store the result in rd L03 Instruction Set 84

85 MIPS Shift Operations Sample coded operation: SHIFT LOGICAL LEFT instruction R-type: op = 0x00 dictating an ALU function rt = 2 Reg[2] source func = 0x00 dictating an sll Assembly: sll $2, $2, 4 sll rd, rt, shamt: Reg[rd] = Reg[rt] << shamt Shift the contents of rt to the left by shamt; store the result in rd L03 Instruction Set 85

86 MIPS Shift Operations Sample coded operation: SHIFT LOGICAL LEFT instruction R-type: op = 0x00 dictating an ALU function Assembly: sll $2, $2, 4 rt = 2 Reg[2] source func = 0x00 dictating an sll shamt = 4 dictates a shift of 4- bits sll rd, rt, shamt: Reg[rd] = Reg[rt] << shamt Shift the contents of rt to the left by shamt; store the result in rd L03 Instruction Set 86

87 MIPS Shift Operations Sample coded operation: SHIFT LOGICAL LEFT instruction R-type: op = 0x00 dictating an ALU function Assembly: sll $2, $2, 4 rt = 2 Reg[2] source rd = 2 Reg[2] destination func = 0x00 dictating an sll shamt = 4 dictates a shift of 4- bits sll rd, rt, shamt: Reg[rd] = Reg[rt] << shamt Shift the contents of rt to the left by shamt; store the result in rd L03 Instruction Set 87

88 MIPS Shift Operations Sample coded operation: SHIFT LOGICAL LEFT instruction R-type: op = 0x00 dictating an ALU function unused set to 0 Assembly: sll $2, $2, 4 rt = 2 Reg[2] source rd = 2 Reg[2] destination func = 0x00 dictating an sll shamt = 4 dictates a shift of 4- bits sll rd, rt, shamt: Reg[rd] = Reg[rt] << shamt Shift the contents of rt to the left by shamt; store the result in rd L03 Instruction Set 88

89 MIPS Shift Operations Sample coded operation: SHIFT LOGICAL LEFT instruction R-type: op = 0x00 dictating an ALU function unused set to 0 Assembly: sll $2, $2, 4 rt = 2 Reg[2] source rd = 2 Reg[2] destination func = 0x00 dictating an sll shamt = 4 dictates a shift of 4- bits Assembly: sllv $2, $2, $8 sll rd, rt, shamt: Reg[rd] = Reg[rt] << shamt sllv rd, rt, rs: Reg[rd] = Reg[rt] << Reg[rs] Shift the contents of rt to the left by shamt; store the result in rd Shift the contents of rt left by the contents of rs; store the result in rd L03 Instruction Set 89

90 MIPS Shift Operations Sample coded operation: SHIFT LOGICAL LEFT instruction R-type: op = 0x00 dictating an ALU function unused set to 0 Assembly: sll $2, $2, 4 rt = 2 Reg[2] source rd = 2 Reg[2] destination func = 0x00 dictating an sll shamt = 4 dictates a shift of 4- bits Assembly: sllv $2, $2, $8 This is peculiar syntax for MIPS, in this ALU instruction the rt operand precedes the rs operand. Usually, it s the other way around sll rd, rt, shamt: Reg[rd] = Reg[rt] << shamt sllv rd, rt, rs: Reg[rd] = Reg[rt] << Reg[rs] Shift the contents of rt to the left by shamt; store the result in rd Shift the contents of rt left by the contents of rs; store the result in rd L03 Instruction Set 90

91 MIPS Shift Operations Sample coded operation: SHIFT LOGICAL LEFT instruction R-type: op = 0x00 dictating an ALU function unused set to 0 Assembly: sll $2, $2, 4 rt = 2 Reg[2] source How are shifts useful? rd = 2 Reg[2] destination func = 0x00 dictating an sll shamt = 4 dictates a shift of 4- bits Assembly: sllv $2, $2, $8 This is peculiar syntax for MIPS, in this ALU instruction the rt operand precedes the rs operand. Usually, it s the other way around sll rd, rt, shamt: Reg[rd] = Reg[rt] << shamt sllv rd, rt, rs: Reg[rd] = Reg[rt] << Reg[rs] Shift the contents of rt to the left by shamt; store the result in rd Shift the contents of rt left by the contents of rs; store the result in rd L03 Instruction Set 91

92 MIPS ALU Operations with Immediate addi instruction: adds register contents, signed-constant: I-type: OP = 0x08, dictating addi rs = 11, Reg[11] source rt = 9, Reg[9] destination Symbolic version: addi $9, $11, -3 constant field, indicating -3 as second operand (sign-extended!) addi rt, rs, imm: Reg[rt] = Reg[rs] + sxt(imm) Add the contents of rs to const; store result in rt Similar instructions for other ALU operations: arithmetic: addi, addiu compare: slti, sltiu logical: andi, ori, xori, lui Immediate values are sign-extended for arithmetic and compare operations, but not for logical operations. L03 Instruction Set 92

93 Why Built-in Constants? (Immediate) Why not put constants in memory (was common in older instruction sets)? create more hard-wired registers for constants (like $0)? SMALL constants are used frequently (50% of operands) In a C compiler (gcc) 52% of ALU operations involve a constant In a circuit simulator (spice) 69% involve constants e.g., B = B + 1; C = W & 0x00ff; A = B + 0; ISA Design Principle: Make the common cases fast MIPS Instructions: addi $29, $29, 4 slti $8, $18, 10 andi $29, $29, 6 ori $29, $29, 4 How large of constants should we allow for? If they are too big, we won t have enough bits leftover for the instructions. Why are there so many different sized constants in the MIPS ISA? Couldn t the shift amount have been encoded using the I-format? One way to answer architectural questions is to evaluate the consequences of different choices using carefully chosen representative benchmarks (programs and/or code sequences). Make choices that are best according to some metric (cost, performance, ). L03 Instruction Set 93

94 How About Larger Constants? L03 Instruction Set 94

95 How About Larger Constants? In order to load a 32-bit constant into a register a two instruction sequence is used, load upper immediate lui $8, Then must get the lower order bits right, i.e., ori $8, $8, L03 Instruction Set 95

96 How About Larger Constants? In order to load a 32-bit constant into a register a two instruction sequence is used, load upper immediate lui $8, Then must get the lower order bits right, i.e., ori $8, $8, ori L03 Instruction Set 96

97 How About Larger Constants? In order to load a 32-bit constant into a register a two instruction sequence is used, load upper immediate lui $8, Then must get the lower order bits right, i.e., ori ori $8, $8, Reminder: In MIPS, Logical Immediate instructions (ANDI, ORI, XORI) do not sign-extend their constant operand L03 Instruction Set 97

98 First MIPS Program (fragment) Suppose you want to compute the following expression: f = (g + h) (i + j) Where the variables f, g, h, i, and j are assigned to registers $16, $17, $18, $19, and $20 respectively. What is the MIPS assembly code? add $8,$17,$18 # (g + h) add $9,$19,$20 # (i + j) sub $16,$8,$9 # f = (g + h) (i + j) These three instructions are like our little ad-hoc machine from the beginning of lecture. Of course, limiting ourselves to registers for storage falls short of our ambitions... Needed: instruction-set support for reading and writing locations in main memory... L03 Instruction Set 98

99 MIPS Load & Store Instructions MIPS is a LOAD/STORE architecture. This means that *all* data memory accesses are limited to load and store instructions, which transfer register contents to-and-from memory. ALU operations work only on registers. I-type: OP rs rt 16-bit signed constant Reg[rt] = Mem[Reg[rs] + sxt(const)] lw rt, imm(rs) Fetch into rt the contents of the memory location whose address is const plus the contents of rs Abbreviation: lw rt,imm for lw rt, imm($0) sw rt, imm(rs) Mem[Reg[rs] + sxt(const)] = Reg[rt] Store the contents of rt into the memory location whose address is const plus the contents of rs Abbreviation: sw rt, imm for sw rt, imm($0) BYTE ADDRESSES, but lw and sw 32-bit word access word-aligned addresses. The resulting lowest two address bits must be 0! L03 Instruction Set 99

100 Storage Conventions Data and Variables are stored in memory Operations done on registers Registers hold Temporary results 1000: 1004: 1008: 100C: 1010: n r x y L03 Instruction Set 100

101 Storage Conventions Address assigned at compile time Data and Variables are stored in memory Operations done on registers Registers hold Temporary results 1000: 1004: 1008: 100C: 1010: n r x y L03 Instruction Set 101

102 Storage Conventions Address assigned at compile time int x, y; y = x + 37; Data and Variables are stored in memory Operations done on registers Registers hold Temporary results 1000: 1004: 1008: 100C: 1010: n r x y L03 Instruction Set 102

103 Storage Conventions Data and Variables are stored in memory Operations done on registers Registers hold Temporary results 1000: 1004: 1008: 100C: 1010: Address assigned at compile time int x, y; y = x + 37; n r x y translates to Compilation approach: LOAD, COMPUTE, STORE lw $t0, 0x1008($0) addi $t0, $t0, 37 sw $t0, 0x100C($0) L03 Instruction Set 103

104 Storage Conventions Data and Variables are stored in memory Operations done on registers Registers hold Temporary results 1000: 1004: 1008: 100C: 1010: Address assigned at compile time int x, y; y = x + 37; n r x y translates to or, more humanely, to Compilation approach: LOAD, COMPUTE, STORE lw $t0, 0x1008($0) addi $t0, $t0, 37 sw $t0, 0x100C($0) x=0x1008 y=0x100c lw $t0, x addi $t0, $t0, 37 sw $t0, y rs defaults to Reg[0] (0) L03 Instruction Set 104

105 MIPS Register Usage Conventions By convention, the MIPS registers are assigned to specific uses, and names. These are supported by the assembler, and higherlevel languages. We ll use these names increasingly. Name Register number Usage $zero 0 the constant value 0 $at 1 assembler temporary $v0-$v1 2-3 values for results and expression evaluation $a0-$a3 4-7 arguments $t0-$t temporaries $s0-$s saved $t8-$t more temporaries $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 return address L03 Instruction Set 105

106 Capabilities thus far: Expression Evaluation Translation of an Expression: int x, y; y = (x-3)*(y ) x:.word 0 y:.word 0 c:.word lw $t0, x addi $t0, $t0, -3 lw $t1, y lw $t2, c add $t1, $t1, $t2 mul $t0, $t0, $t1 sw $t0, y VARIABLES are allocated storage in main memory VARIABLE references translate to LD or ST OPERATORS translate to ALU instructions SMALL CONSTANTS translate to ALU instructions w/ built-in constant LARGE CONSTANTS translate to initialized variables NB: Here we assume that variable addresses fit into 16- bit constants! L03 Instruction Set 106

107 Model thus far: Can We Run Any Algorithm? Executes instructions sequentially Number of operations executed = number of instructions in our program! L03 Instruction Set 107

108 Model thus far: Can We Run Any Algorithm? Executes instructions sequentially Number of operations executed = number of instructions in our program! Good news: programs can t loop forever! So far the MIPS subset produces straight-line code only L03 Instruction Set 108

109 Model thus far: Can We Run Any Algorithm? Executes instructions sequentially Number of operations executed = number of instructions in our program! Good news: programs can t loop forever! So far the MIPS subset produces straight-line code only Bad news: Straight-line code Can t do a loop Can t reuse a block of code L03 Instruction Set 109

110 Model thus far: Can We Run Any Algorithm? Executes instructions sequentially Number of operations executed = number of instructions in our program! Good news: programs can t loop forever! So far the MIPS subset produces straight-line code only Bad news: Straight-line code Can t do a loop Can t reuse a block of code Needed: ability to change the PC. L03 Instruction Set 110

111 MIPS Branch Instructions MIPS branch instructions provide a way of conditionally changing the PC to some nearby location... I-type: OPCODE rs rt 16-bit signed constant beq rs, rt, label # Branch if equal if (REG[RS] == REG[RT]) { PC = PC *offset; } bne rs, rt, label # Branch if not equal if (REG[RS]!= REG[RT]) { PC = PC *offset; } NB: Branch targets are specified relative to the current instruction (actually relative to the next instruction, which would be fetched by default). The assembler hides the calculation of these offset values from the user, by allowing them to specify a target address (usually a label) and it does the job of computing the offset s value. The size of the constant field (16-bits) limits the range of branches. L03 Instruction Set 111

112 MIPS Branch Instructions MIPS branch instructions provide a way of conditionally changing the PC to some nearby location... I-type: OPCODE rs rt 16-bit signed constant beq rs, rt, label # Branch if equal bne rs, rt, label # Branch if not equal if (REG[RS] == REG[RT]) { PC = PC *offset; } if (REG[RS]!= REG[RT]) { PC = PC *offset; } Notice on memory references offsets are multiplied by 4, so that branch targets are restricted to word boundaries. NB: Branch targets are specified relative to the current instruction (actually relative to the next instruction, which would be fetched by default). The assembler hides the calculation of these offset values from the user, by allowing them to specify a target address (usually a label) and it does the job of computing the offset s value. The size of the constant field (16-bits) limits the range of branches. L03 Instruction Set 112

113 The range of MIPS branch instructions is limited to approximately 64K instructions from the branch instruction. In order to branch farther an unconditional jump instruction is used. Instructions: Formats: MIPS Jumps j label # jump to label (PC = PC[31-28] CONST[25:0]*4) jal label # jump to label and store PC+4 in $31 jr $t0 # jump to address specified by register s contents jalr $t0, $ra # jump to address specified by register s contents J-type: used for j OP = 2 26-bit constant J-type: used for jal OP = 3 26-bit constant R-type, used for jr OP = 0 r s func = 8 R-type, used for jalr OP = 0 r s 0 r d 0 func = 9 L03 Instruction Set 113

114 Now we can do a real program: Factorial... Synopsis (in C): Input in n, output in ans r1, r2 used for temporaries follows algorithm of our earlier data paths. MIPS code, in assembly language: int n, ans; register int r1, r2; r1 = 1; r2 = n; while (r2!= 0) { r1 = r1 * r2; r2 = r2 1; } ans = r1; n:.word 123 ans:.word 0... addi $t0, $0, 1 # t0 = 1 lw $t1, n # t1 = n loop: beq $t1, $0, done # while (t1!= 0) mul $t0, $t0, $t1 # t0 = t0 * t1 addi $t1, $t1, -1 # t1 = t1-1 beq $0, $0, loop # Always branch done: sw $t0, ans # ans = r1 L03 Instruction Set 114

115 To summarize: MIPS operands Name Example Comments $s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform 32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero always equals 0. Register $at is $fp, $sp, $ra, $at reserved for the assembler to handle large constants. Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so 2 30 memory Memory[4],..., sequential words differ by 4. Memory holds data structures, such as arrays, words Memory[ ] and spilled registers, such as those saved on procedure calls. MIPS assembly language Category Instruction Example Meaning Comments add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers add immediate addi $s1, $s2, 100 $s1 = $s Used to add constants load word lw $s1, 100($s2) $s1 = Memory[$s ] Word from memory to register store word sw $s1, 100($s2) Memory[$s ] = $s1 Word from register to memory Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s ] Byte from memory to register store byte sb $s1, 100($s2) Memory[$s ] = $s1 Byte from register to memory load upper immediate lui $s1, 100 $s1 = 100 * 2 16 Loads constant in upper 16 bits branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to PC branch on not equal bne $s1, $s2, 25 if ($s1!= $s2) go to Conditional PC branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; else $s1 = 0 Equal test; PC-relative branch Not equal test; PC-relative Compare less than; for beq, bne set less than immediate slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; else $s1 = 0 Compare less than constant jump j 2500 go to Jump to target address Uncondi- jump register jr $ra go to $ra For switch, procedure return tional jump jump and link jal 2500 $ra = PC + 4; go to For procedure call L03 Instruction Set 115

116 MIPS Instruction Decoding Ring OP ALU j jal beq bne 001 addi addiu slti sltiu andi ori xori lui lw 101 sw ALU sll srl sra sllv srlv srav 001 jr jalr mult multu div divu 100 add addu sub subu and or xor nor 101 slt sltu L03 Instruction Set 116

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