Recitation 5: Recitation 5: MIPS Interrupts and Floating Point

Size: px
Start display at page:

Download "Recitation 5: Recitation 5: MIPS Interrupts and Floating Point"

Transcription

1

2 Float Operations We will write a full program to read in two floats, perform an add, subtract, multiply, and divide, printing out each result Let s attempt in C (using blocking IO)

3 Float Operations We will write a full program to read in two floats, perform an add, subtract, multiply, and divide, printing out each result Let s attempt in C (using blocking IO) float a, b; scanf( %f, &a); scanf( %f, &b); printf( a + b = %f\n, a + b); printf( a b = %f\n, a b); printf( a b = %f\n, a b); printf( a / b = %f\n, a / b);

4 Float Operations float a, b; scanf( %f, &a); scanf( %f, &b); printf( a + b = %f\n, a + b); printf( a b = %f\n, a b); printf( a b = %f\n, a b); printf( a / b = %f\n, a / b);

5 Float Operations float a, b; scanf( %f, &a); scanf( %f, &b); li $v0, 6 # problem? li $v0, 6 # read into f0 # read into f0 printf( a + b = %f\n, a + b); printf( a b = %f\n, a b); printf( a b = %f\n, a b); printf( a / b = %f\n, a / b); add.s $f12, $f0, $f1 # and print sub.s $f12, $f0, $f1 # and print mult.s $f12, $f0, $f1 # and print div.s $f12, $f0, $f1 # and print

6 Convert To Float.data endl:.asciiz "\n" addmsg:.asciiz "a + b = " submsg:.asciiz "a - b = " mulmsg:.asciiz "a * b = " divmsg:.asciiz "a / b = ".text.globl main main: li $v0, 6 # enter a float mov.s $f1, $f0 li $v0, 6 # enter a float add.s $f12, $f0, $f1 la $a0, addmsg mfc1 $a1, $f12 jal printop sub.s $f12, $f0, $f1 la $a0, submsg mfc1 $a1, $f12 jal printop mul.s $f12, $f0, $f1 la $a0, mulmsg mfc1 $a1, $f12 jal printop div.s $f12, $f0, $f1 la $a0, divmsg mfc1 $a1, $f12 jal printop # add and print # sub and print # multiply and print # add and print exit: li $v0, 10 # exit # printop: print corresponding message, result, and newline # input: # a0 = &msg # a1 = result (float) # outputs: None printop: li $v0, 4 # print message (string) mfc1 $a1, $f12 li $v0, 2 # print result (float) la $a0, endl li $v0, 4 # print endl jr $ra

7 Convert to Float We will write a full program to read in nonblocking input and convert it to float Let s attempt in C (using blocking IO)

8 Convert to Float We will write a full program to read in nonblocking input and convert it to float Let s attempt in C (using blocking IO) while(tmp == getchar()) { if(tmp < 0 ) { printf( %d too low\n, tmp); else if(tmp > 9 ) { printf( %d too high\n, tmp); int intval = (int) tmp; float floatval = (float) intval; printf( %f, floatval); break;

9 Convert to Float while(tmp == getchar()) { if(tmp < 0 ) { printf( %d too low\n, tmp); else if(tmp > 9 ) { printf( %d too high\n, tmp); int intval = (int) tmp; float floatval = (float) intval; printf( %f, floatval); break;

10 Convert to Float while(tmp == getchar()) { if(tmp < 0 ) { printf( %d too low\n, tmp); else if(tmp > 9 ) { printf( %d too high\n, tmp); int intval = (int) tmp; float floatval = (float) intval; printf( %f, floatval); break; li $t0, 48 blt $s6, $t0, toolow li $t0, 57 bgt $s6, $t0, toohigh addi $s6, $s6, -48 mtc1 $s6, $f12 cvt.s.w $f12, $f12

11 .data endl:.asciiz "\n" lowmsg:.asciiz " is too low" highmsg:.asciiz " is too high".text.globl main main: mfc0 $a0, $12 # read from the status register ori $a0, 0xff11 # enable all interrupts mtc0 $a0, $12 # write back to the status register lui $t0, 0xFFFF ori $a0, $0, 2 sw $a0, 0($t0) li $s6, li $s7, ascii code loop: beq $s6, $s7, loop move $a0, $s6 # $t0 = 0xFFFF0000 # enable keyboard interrupt # write back to 0xFFFF0000 # $s6 used to pass the ascii code # a large number impossible to be an # if no input, loop li $t0, 48 # if (input < 48) goto loop blt $s6, $t0, toolow li $t0, 57 # if (input > 57) goto loop bgt $s6, $t0, toohigh addi $s6, $s6, -48 mtc1 $s6, $f12 cvt.s.w $f12, $f12 # convert char to int # convert int to float li $v0, 2 # print input la $a0, endl loopreset: mfc0 $t0, $12 # Set Status register andi $t0, 0xfffe # clear ENABLE mtc0 $t0, $12 # write back to status li $s6, mfc0 $t0, $12 ori $t0, 1 mtc0 $t0, $12 j loop toolow: li $v0, 11 li $v0, 4 la $a0, lowmsg la $a0, endl j loopreset toohigh: li $v0, 11 li $v0, 4 la $a0, highmsg la $a0, endl j loopreset exit: li $v0, 10.kdata s1:.word 10 s2:.word 11.ktext 0x # $s0 used to pass the ascii code # Set Status register # set ENABLE # write back to status # print low message # print high message # exit,if it ever comes here # kernel data # kernel code starts here sw $v0, s1 # To show how to save, we use these registers sw $a0, s2 # not using the stack because the interrupt might be # triggered by a memory reference # using a bad value of the stack pointer mfc0 $k0, $13 # Cause register srl $a0, $k0, 2 # Extract ExcCode Field (bits 2-6) andi $a0, $a0, 0x1f bne $a0, $zero, kdone processing I/O here lui $v0, 0xFFFF lw $s6, 4($v0) kdone: lw $v0, s1 lw $a0, s2 # Exception Code 0 is I/O. Only # $v0 = 0xFFFF0000 # get the input key # Restore other registers mtc0 $0, $13 # Clear Cause register mfc0 $k0, $12 # Set Status register andi $k0, 0xfffd # clear EXL bit ori $k0, 0x11 # Interrupts enabled mtc0 $k0, $12 # write back to status eret # return to EPC Convert To Float

Writing an Embedded Controller

Writing an Embedded Controller Writing an Embedded Controller Embedded Controller A computer with a dedicated function within a larger system Usually has real time computing constraints Is expected to process requests at a certain speed

More information

Lecture 7: MIPS Functions Part 2. Nested Function Calls. Lecture 7: Character and String Operations. SPIM Syscalls. Recursive Functions

Lecture 7: MIPS Functions Part 2. Nested Function Calls. Lecture 7: Character and String Operations. SPIM Syscalls. Recursive Functions Part Part Part What if we need to call a function inside of a function? Will this work? int twofun(int a, int b) { int res; res = addfun(a, b) a / ; return res; } twofun: addi $sp, $sp, -4 sw $s0, 0($sp)

More information

CDA3100 Midterm Exam, Summer 2013

CDA3100 Midterm Exam, Summer 2013 CDA3100 Midterm Exam, Summer 2013 Name : Instructions: 1. This is a close-book and close-notes exam. 2. You have 75 minutes to answer the questions. 3. Please write down your name on the top of this page

More information

MIPS function continued

MIPS function continued MIPS function continued Review Functions Series of related instructions one after another in memory Called through the jal instruction Pointed to by a label like any other Returns by calling Stack Top

More information

Implementing a Car Simulator in MIPS

Implementing a Car Simulator in MIPS 1. This homework must be finished individually. 2. This assignment has been designated by the Department of Computer Science for assessment of certain expected outcomes for its degree programs, as required

More information

Chapter loop: lw $v1, 0($a0) addi $v0, $v0, 1 sw $v1, 0($a1) addi $a0, $a0, 1 addi $a1, $a1, 1 bne $v1, $zero, loop

Chapter loop: lw $v1, 0($a0) addi $v0, $v0, 1 sw $v1, 0($a1) addi $a0, $a0, 1 addi $a1, $a1, 1 bne $v1, $zero, loop Chapter 3 3.7 loop: lw $v1, 0($a0) addi $v0, $v0, 1 sw $v1, 0($a1) addi $a0, $a0, 1 addi $a1, $a1, 1 bne $v1, $zero, loop Instructions Format OP rs rt Imm lw $v1, 0($a0) I 35 4 3 0 addi $v0, $v0, 1 I 8

More information

Patterson PII. Solutions

Patterson PII. Solutions Patterson-1610874 978-0-12-407726-3 PII 2 Solutions Chapter 2 Solutions S-3 2.1 addi f, h, -5 (note, no subi) add f, f, g 2.2 f = g + h + i 2.3 sub $t0, $s3, $s4 add $t0, $s6, $t0 lw $t1, 16($t0) sw $t1,

More information

MIPS ISA and MIPS Assembly. CS301 Prof. Szajda

MIPS ISA and MIPS Assembly. CS301 Prof. Szajda MIPS ISA and MIPS Assembly CS301 Prof. Szajda Administrative HW #2 due Wednesday (9/11) at 5pm Lab #2 due Friday (9/13) 1:30pm Read Appendix B5, B6, B.9 and Chapter 2.5-2.9 (if you have not already done

More information

Introduction to MIPS Processor

Introduction to MIPS Processor Introduction to MIPS Processor The processor we will be considering in this tutorial is the MIPS processor. The MIPS processor, designed in 1984 by researchers at Stanford University, is a RISC (Reduced

More information

Common Problems on Homework

Common Problems on Homework MIPS Functions Common Problems on Homework 1.3: Convert -3000 ten to binary in 8bit, 16bit, and 32bit Even though it overflows with 8bits, there is plenty of room with 16 and 32 bit. Common Problems on

More information

ECE 30 Introduction to Computer Engineering

ECE 30 Introduction to Computer Engineering ECE 30 Introduction to Computer Engineering Study Problems, Set #3 Spring 2015 Use the MIPS assembly instructions listed below to solve the following problems. arithmetic add add sub subtract addi add

More information

SPIM Instruction Set

SPIM Instruction Set SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large

More information

Exceptions and Interrupts

Exceptions and Interrupts Exceptions and Interrupts Unexpected events (asynchronous interrupt) requiring change in flow of control (different ISAs use the terms differently) exception Arises within the CPU e.g., undefined opcode,

More information

MIPS I/O and Interrupt

MIPS I/O and Interrupt MIPS I/O nd Interrupt Review Floting point instructions re crried out on seprte chip clled coprocessor 1 You hve to move dt to/from coprocessor 1 to do most common opertions such s printing, clling functions,

More information

EE 109 Unit 17 - Exceptions

EE 109 Unit 17 - Exceptions EE 109 Unit 17 - Exceptions 1 2 What are Exceptions? Any event that causes a break in normal execution Error Conditions Invalid address, Arithmetic/FP overflow/error Hardware Interrupts / Events Handling

More information

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Two 11 March Your Name (please print) total

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Two 11 March Your Name (please print) total Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

2) Using the same instruction set for the TinyProc2, convert the following hex values to assembly language: x0f

2) Using the same instruction set for the TinyProc2, convert the following hex values to assembly language: x0f CS2 Fall 28 Exam 2 Name: ) The Logisim TinyProc2 has four instructions, each using 8 bits. The instruction format is DR SR SR2 OpCode with OpCodes of for add, for subtract, and for multiply. Load Immediate

More information

CS152 Computer Architecture and Engineering

CS152 Computer Architecture and Engineering University of California, Berkeley College of Engineering Electrical Engineering and Computer Science, Computer Science Division Fall 2001 CS152 Computer Architecture and Engineering Homework #2 Solutions

More information

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam One 4 February Your Name (please print clearly)

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam One 4 February Your Name (please print clearly) Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

More information

Solutions for Chapter 2 Exercises

Solutions for Chapter 2 Exercises Solutions for Chapter 2 Exercises 1 Solutions for Chapter 2 Exercises 2.2 By lookup using the table in Figure 2.5 on page 62, 7fff fffa hex = 0111 1111 1111 1111 1111 1111 1111 1010 two = 2,147,483,642

More information

CSc 256 Midterm 1 Fall 2011

CSc 256 Midterm 1 Fall 2011 CSc 256 Midterm 1 Fall 2011 NAME: Problem 1a: Given the C++ function prototype and variable declarations: int func(int arg0, int *arg1, int *arg2); int *ptr, n, arr[10]; which of the following statements

More information

Points available Your marks Total 100

Points available Your marks Total 100 CSSE 232 Computer Architecture I Rose-Hulman Institute of Technology Computer Science and Software Engineering Department Exam 1 Solutions Name: Section: 1 2 This exam is closed book. You are allowed to

More information

MIPS Assembly Language Guide

MIPS Assembly Language Guide MIPS Assembly Language Guide MIPS is an example of a Reduced Instruction Set Computer (RISC) which was designed for easy instruction pipelining. MIPS has a Load/Store architecture since all instructions

More information

Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )

Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont ) Chapter 2 Computer Abstractions and Technology Lesson 4: MIPS (cont ) Logical Operations Instructions for bitwise manipulation Operation C Java MIPS Shift left >>> srl Bitwise

More information

Overview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)

Overview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2) Introduction to the MIPS ISA Overview Remember that the machine only understands very basic instructions (machine instructions) It is the compiler s job to translate your high-level (e.g. C program) into

More information

Branch Addressing. Jump Addressing. Target Addressing Example. The University of Adelaide, School of Computer Science 28 September 2015

Branch Addressing. Jump Addressing. Target Addressing Example. The University of Adelaide, School of Computer Science 28 September 2015 Branch Addressing Branch instructions specify Opcode, two registers, target address Most branch targets are near branch Forward or backward op rs rt constant or address 6 bits 5 bits 5 bits 16 bits PC-relative

More information

Format. 10 multiple choice 8 points each. 1 short answer 20 points. Same basic principals as the midterm

Format. 10 multiple choice 8 points each. 1 short answer 20 points. Same basic principals as the midterm Final Review Format 10 multiple choice 8 points each Make sure to show your work Can write a description to the side as to why you think your answer is correct for possible partial credit 1 short answer

More information

MIPS%Assembly% E155%

MIPS%Assembly% E155% MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary

More information

Quick Review. lw $t0, 4($a0) Registers x Memory. $a0 is simply another name for register 4 $t0 is another name for register (green sheet)

Quick Review. lw $t0, 4($a0) Registers x Memory. $a0 is simply another name for register 4 $t0 is another name for register (green sheet) CSE378 Lecture 3 Today: Finish up memory Control-flow (branches) in MIPS if/then loops case/switch (maybe) Start: Array Indexing vs. Pointers In particular pointer arithmetic String representation 1 Quick

More information

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Computer Science 2500 Computer Organization Rensselaer Polytechnic Institute Spring Topic Notes: MIPS Programming

Computer Science 2500 Computer Organization Rensselaer Polytechnic Institute Spring Topic Notes: MIPS Programming Computer Science 2500 Computer Organization Rensselaer Polytechnic Institute Spring 2009 Topic Notes: MIPS Programming We spent some time looking at the MIPS Instruction Set Architecture. We will now consider

More information

QtSPIM and MARS : MIPS Simulators

QtSPIM and MARS : MIPS Simulators QtSPIM and MARS : MIPS Simulators Learning MIPS & SPIM MIPS assembly is a low-level programming language The best way to learn any programming language is to write code We will get you started by going

More information

MIPS Instruction Reference

MIPS Instruction Reference Page 1 of 9 MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly

More information

CSc 256 Midterm 2 Spring 2012

CSc 256 Midterm 2 Spring 2012 CSc 256 Midterm 2 Spring 2012 NAME: 1a) You are given this MIPS assembly language instruction (i.e., pseudo- instruction): ble $12, 0x20004880, there Translate this MIPS instruction to an efficient sequence

More information

HW2 solutions You did this for Lab sbn temp, temp,.+1 # temp = 0; sbn temp, b,.+1 # temp = -b; sbn a, temp,.+1 # a = a (-b) = a + b;

HW2 solutions You did this for Lab sbn temp, temp,.+1 # temp = 0; sbn temp, b,.+1 # temp = -b; sbn a, temp,.+1 # a = a (-b) = a + b; HW2 solutions 3.10 Pseuodinstructions What is accomplished Minimum sequence of Mips Move $t5, $t3 $t5=$t3 Add $t5, $t3, $0 Clear $t5 $t5=0 Xor $t5, $t5, $t5 Li $t5, small $t5=small Addi $t5, $0, small

More information

MIPS Reference Guide

MIPS Reference Guide MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming

More information

We will study the MIPS assembly language as an exemplar of the concept.

We will study the MIPS assembly language as an exemplar of the concept. MIPS Assembly Language 1 We will study the MIPS assembly language as an exemplar of the concept. MIPS assembly instructions each consist of a single token specifying the command to be carried out, and

More information

Q1: /30 Q2: /25 Q3: /45. Total: /100

Q1: /30 Q2: /25 Q3: /45. Total: /100 ECE 2035(A) Programming for Hardware/Software Systems Fall 2013 Exam One September 19 th 2013 This is a closed book, closed note texam. Calculators are not permitted. Please work the exam in pencil and

More information

ECE232: Hardware Organization and Design. Computer Organization - Previously covered

ECE232: Hardware Organization and Design. Computer Organization - Previously covered ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization

More information

Examples of branch instructions

Examples of branch instructions Examples of branch instructions Beq rs,rt,target #go to target if rs = rt Beqz rs, target #go to target if rs = 0 Bne rs,rt,target #go to target if rs!= rt Bltz rs, target #go to target if rs < 0 etc.

More information

CSc 256 Midterm 2 Fall 2011

CSc 256 Midterm 2 Fall 2011 CSc 256 Midterm 2 Fall 2011 NAME: 1a) You are given a MIPS branch instruction: x: beq $12, $0, y The address of the label "y" is 0x400468. The memory location at "x" contains: address contents 0x40049c

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 23 October Your Name (please print clearly) Signed.

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 23 October Your Name (please print clearly) Signed. Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

More information

CSc 256 Midterm (green) Fall 2018

CSc 256 Midterm (green) Fall 2018 CSc 256 Midterm (green) Fall 2018 NAME: Problem 1 (5 points): Suppose we are tracing a C/C++ program using a debugger such as gdb. The code showing all function calls looks like this: main() { bat(5);

More information

CS 61C, Midterm #2, Spring 1997 CS 61C. Spring 1997 Midterm #2. Professor Brian Harvey

CS 61C, Midterm #2, Spring 1997 CS 61C. Spring 1997 Midterm #2. Professor Brian Harvey This exam was worth 24 points, and was open book. Problem #1 (4 points) CS 61C Spring 1997 Midterm #2 Professor Brian Harvey Translate the following procedure to MAL. (Assume that the argument and return

More information

Flow of Control -- Conditional branch instructions

Flow of Control -- Conditional branch instructions Flow of Control -- Conditional branch instructions You can compare directly Equality or inequality of two registers One register with 0 (>,

More information

Compiling Techniques

Compiling Techniques Lecture 10: An Introduction to MIPS assembly 18 October 2016 Table of contents 1 Overview 2 3 Assembly program template.data Data segment: constant and variable definitions go here (including statically

More information

Mark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA

Mark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA EE 357 Unit 11 MIPS ISA Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible

More information

ICS DEPARTMENT ICS 233 COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE. Midterm Exam. First Semester (141) Time: 1:00-3:30 PM. Student Name : _KEY

ICS DEPARTMENT ICS 233 COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE. Midterm Exam. First Semester (141) Time: 1:00-3:30 PM. Student Name : _KEY Page 1 of 14 Nov. 22, 2014 ICS DEPARTMENT ICS 233 COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE Midterm Exam First Semester (141) Time: 1:00-3:30 PM Student Name : _KEY Student ID. : Question Max Points Score

More information

Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei

Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei Computer Architecture Instruction Set Architecture part 2 Mehran Rezaei Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 19 September 2012

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 19 September 2012 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 21 October 2016

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 21 October 2016 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ECE 473 Computer Architecture and Organization Lab 4: MIPS Assembly Programming Due: Wednesday, Oct. 19, 2011 (30 points)

ECE 473 Computer Architecture and Organization Lab 4: MIPS Assembly Programming Due: Wednesday, Oct. 19, 2011 (30 points) ECE 473 Computer Architecture and Organization Lab 4: MIPS Assembly Programming Due: Wednesday, Oct. 19, 2011 (30 points) Objectives: Get familiar with MIPS instructions Assemble, execute and debug MIPS

More information

MIPS Coding Snippets. Prof. James L. Frankel Harvard University. Version of 9:32 PM 14-Feb-2016 Copyright 2016 James L. Frankel. All rights reserved.

MIPS Coding Snippets. Prof. James L. Frankel Harvard University. Version of 9:32 PM 14-Feb-2016 Copyright 2016 James L. Frankel. All rights reserved. MIPS Coding Snippets Prof. James L. Frankel Harvard University Version of 9:32 PM 14-Feb-2016 Copyright 2016 James L. Frankel. All rights reserved. Loading a 32-bit constant into a register # Example loading

More information

Course Administration

Course Administration Fall 2017 EE 3613: Computer Organization Chapter 2: Instruction Set Architecture 2/4 Avinash Kodi Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio 45701 E-mail: kodi@ohio.edu

More information

Lecture 6 Decision + Shift + I/O

Lecture 6 Decision + Shift + I/O Lecture 6 Decision + Shift + I/O Instructions so far MIPS C Program add, sub, addi, multi, div lw $t0,12($s0) sw $t0, 12($s0) beq $s0, $s1, L1 bne $s0, $s1, L1 j L1 (unconditional branch) slt reg1,reg2,reg3

More information

COMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture

COMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture COMP 303 Computer Architecture Lecture 3 Comp 303 Computer Architecture 1 Supporting procedures in computer hardware The execution of a procedure Place parameters in a place where the procedure can access

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 22 September Your Name (please print clearly) Signed.

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 22 September Your Name (please print clearly) Signed. Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

More information

MIPS Assembly Language Programming

MIPS Assembly Language Programming MIPS Assembly Language Programming ICS 233 Computer Architecture and Assembly Language Dr. Aiman El-Maleh College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals [Adapted

More information

comp 180 Lecture 10 Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions

comp 180 Lecture 10 Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions Procedure Calls A procedure of a subroutine is like an agent which needs certain information to perform a

More information

Lecture 5: Procedure Calls

Lecture 5: Procedure Calls Lecture 5: Procedure Calls Today s topics: Procedure calls and register saving conventions 1 Example Convert to assembly: while (save[i] == k) i += 1; i and k are in $s3 and $s5 and base of array save[]

More information

TSK3000A - Generic Instructions

TSK3000A - Generic Instructions TSK3000A - Generic Instructions Frozen Content Modified by Admin on Sep 13, 2017 Using the core set of assembly language instructions for the TSK3000A as building blocks, a number of generic instructions

More information

Computer Architecture. MIPS Instruction Set Architecture

Computer Architecture. MIPS Instruction Set Architecture Computer Architecture MIPS Instruction Set Architecture Instruction Set Architecture An Abstract Data Type Objects Registers & Memory Operations Instructions Goal of Instruction Set Architecture Design

More information

MIPS Assembly Language. Today s Lecture

MIPS Assembly Language. Today s Lecture MIPS Assembly Language Computer Science 104 Lecture 6 Homework #2 Midterm I Feb 22 (in class closed book) Outline Assembly Programming Reading Chapter 2, Appendix B Today s Lecture 2 Review: A Program

More information

USING A SIMULATOR. QUICK INTRODUCTION From various sources For cs470

USING A SIMULATOR. QUICK INTRODUCTION From various sources For cs470 USING A SIMULATOR QUICK INTRODUCTION From various sources For cs470 INTRODUCTION MARS INTERFACE SIMULATOR USAGE MIPS ASSEMBLER LANGUAGE PROGRAM EXAMPLE Introduction MARS IDE A simulator for the MIPS processor

More information

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:

More information

Lec 10: Assembler. Announcements

Lec 10: Assembler. Announcements Lec 10: Assembler Kavita Bala CS 3410, Fall 2008 Computer Science Cornell University Announcements HW 2 is out Due Wed after Fall Break Robot-wide paths PA 1 is due next Wed Don t use incrementor 4 times

More information

F. Appendix 6 MIPS Instruction Reference

F. Appendix 6 MIPS Instruction Reference F. Appendix 6 MIPS Instruction Reference Note: ALL immediate values should be sign extended. Exception: For logical operations immediate values should be zero extended. After extensions, you treat them

More information

EE 361 University of Hawaii Fall

EE 361 University of Hawaii Fall C functions Road Map Computation flow Implementation using MIPS instructions Useful new instructions Addressing modes Stack data structure 1 EE 361 University of Hawaii Implementation of C functions and

More information

MIPS Assembly Language

MIPS Assembly Language MIPS Assembly Language Chapter 15 S. Dandamudi Outline MIPS architecture Registers Addressing modes MIPS instruction set Instruction format Data transfer instructions Arithmetic instructions Logical/shift/rotate/compare

More information

Topic Notes: MIPS Instruction Set Architecture

Topic Notes: MIPS Instruction Set Architecture Computer Science 220 Assembly Language & Comp. Architecture Siena College Fall 2011 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture.

More information

MIPS Assembly Language Programming

MIPS Assembly Language Programming MIPS Assembly Language Programming COE 308 Computer Architecture Prof. Muhamed Mudawar College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals Presentation Outline Assembly

More information

Chapter 2. Instructions:

Chapter 2. Instructions: Chapter 2 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive e.g., MIPS Arithmetic Instructions We ll be working with

More information

Computer Architecture. The Language of the Machine

Computer Architecture. The Language of the Machine Computer Architecture The Language of the Machine Instruction Sets Basic ISA Classes, Addressing, Format Administrative Matters Operations, Branching, Calling conventions Break Organization All computers

More information

MIPS (SPIM) Assembler Syntax

MIPS (SPIM) Assembler Syntax MIPS (SPIM) Assembler Syntax Comments begin with # Everything from # to the end of the line is ignored Identifiers are a sequence of alphanumeric characters, underbars (_), and dots () that do not begin

More information

Procedure Calling. Procedure Calling. Register Usage. 25 September CSE2021 Computer Organization

Procedure Calling. Procedure Calling. Register Usage. 25 September CSE2021 Computer Organization CSE2021 Computer Organization Chapter 2: Part 2 Procedure Calling Procedure (function) performs a specific task and return results to caller. Supporting Procedures Procedure Calling Calling program place

More information

CSc 256 Final Fall 2016

CSc 256 Final Fall 2016 CSc 256 Final Fall 2016 NAME: Problem 1 (25 points) Translate the C/C++ function func() into MIPS assembly language. The prototype is: void func(int arg0, int *arg1); arg0-arg1 are in $a0- $a1 respectively.

More information

Stored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands

Stored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands Stored Program Concept nstructions: nstructions are bits Programs are stored in memory to be read or written just like data Processor Memory memory for data, programs, compilers, editors, etc. Fetch &

More information

1/26/2014. Previously. CSE 2021: Computer Organization. The Load/Store Family (1) Memory Organization. The Load/Store Family (2)

1/26/2014. Previously. CSE 2021: Computer Organization. The Load/Store Family (1) Memory Organization. The Load/Store Family (2) CSE 202: Computer Organization Lecture-4 Code Translation-2 Memory, Data transfer instructions, Data segment,, Procedures, Stack Shakil M. Khan (adapted from Prof. Roumani) Previously Registers $s0 - $s7,

More information

COMP2611: Computer Organization MIPS function and recursion

COMP2611: Computer Organization MIPS function and recursion COMP2611 Fall2015 COMP2611: Computer Organization MIPS function and recursion Overview 2 You will learn the following in this lab: how to use MIPS functions in a program; the concept of recursion; how

More information

Instruction Set Architecture part 1 (Introduction) Mehran Rezaei

Instruction Set Architecture part 1 (Introduction) Mehran Rezaei Instruction Set Architecture part 1 (Introduction) Mehran Rezaei Overview Last Lecture s Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a

More information

Reduced Instruction Set Computer (RISC)

Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the machine. Reduced number of cycles needed per instruction.

More information

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 $zero all bits are zero 16 $s0 local variable 1 $at assembler temporary 17 $s1 local

More information

ECE260: Fundamentals of Computer Engineering

ECE260: Fundamentals of Computer Engineering Accessing and Addressing Memory James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy American

More information

MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support

MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support Components of an ISA EE 357 Unit 11 MIPS ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible

More information

ECE260: Fundamentals of Computer Engineering

ECE260: Fundamentals of Computer Engineering Accessing and Addressing Memory James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy American

More information

Computer Organization MIPS Architecture. Department of Computer Science Missouri University of Science & Technology

Computer Organization MIPS Architecture. Department of Computer Science Missouri University of Science & Technology Computer Organization MIPS Architecture Department of Computer Science Missouri University of Science & Technology hurson@mst.edu Computer Organization Note, this unit will be covered in three lectures.

More information

ECE 331 Hardware Organization and Design. Professor Jay Taneja UMass ECE - Discussion 3 2/8/2018

ECE 331 Hardware Organization and Design. Professor Jay Taneja UMass ECE - Discussion 3 2/8/2018 ECE 331 Hardware Organization and Design Professor Jay Taneja UMass ECE - jtaneja@umass.edu Discussion 3 2/8/2018 Study Jams Leader: Chris Bartoli Tuesday 5:30-6:45pm Elab 325 Wednesday 8:30-9:45pm Elab

More information

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ECE/CS 314 Fall 2003 Homework 2 Solutions. Question 1

ECE/CS 314 Fall 2003 Homework 2 Solutions. Question 1 ECE/CS 314 Fall 2003 Homework 2 Solutions Question 1 /* Equivalent C code with no loops (goto instead) char* strchr(char* pcstring, char csearchchr) strchr_loop: if (!*pcstring) return 0; if (*pcstring

More information

MIPS Functions and the Runtime Stack

MIPS Functions and the Runtime Stack MIPS Functions and the Runtime Stack COE 301 Computer Organization Prof. Muhamed Mudawar College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals Presentation Outline

More information

Problem 3: Theoretical Questions: Complete the midterm exam taken from a previous year attached at the end of the assignment.

Problem 3: Theoretical Questions: Complete the midterm exam taken from a previous year attached at the end of the assignment. CSE 2021: Computer Organization Assignment # 1: MIPS Programming Due Date: October 25, 2010 Please note that a short quiz based on Assignment 1 will be held in class on October 27, 2010 to assess your

More information

Winter 2012 MID-SESSION TEST Tuesday, March 6 6:30pm to 8:15pm. Please do not write your U of C ID number on this cover page.

Winter 2012 MID-SESSION TEST Tuesday, March 6 6:30pm to 8:15pm. Please do not write your U of C ID number on this cover page. University of Calgary Department of Electrical and Computer Engineering ENCM 369: Computer Organization Lecture Instructors: S. A. Norman and N. R. Bartley Winter 2012 MID-SESSION TEST Tuesday, March 6

More information

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

More information

Chapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes

Chapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes Chapter 2 Instructions: Language of the Computer Adapted by Paulo Lopes Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects

More information

ECE468 Computer Organization & Architecture. MIPS Instruction Set Architecture

ECE468 Computer Organization & Architecture. MIPS Instruction Set Architecture ECE468 Computer Organization & Architecture MIPS Instruction Set Architecture ECE468 Lec4.1 MIPS R2000 / R3000 Registers 32-bit machine --> Programmable storage 2^32 x bytes 31 x 32-bit GPRs (R0 = 0) 32

More information

MIPS Coding Continued

MIPS Coding Continued MIPS Coding Continued Exercise 1 Suppose we have three arrays, A, B, C, all of size 10. Now we want to set C[i] = min(a[i], B[i]) for all 0

More information

MIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions

MIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions Representing Instructions Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register

More information

Lecture 5: Procedure Calls

Lecture 5: Procedure Calls Lecture 5: Procedure Calls Today s topics: Memory layout, numbers, control instructions Procedure calls 1 Memory Organization The space allocated on stack by a procedure is termed the activation record

More information

ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 8 December 2014

ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 8 December 2014 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Three 10 April 2013

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Three 10 April 2013 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information