Instruction Set Architecture part 1 (Introduction) Mehran Rezaei
|
|
- Aleesha Robinson
- 5 years ago
- Views:
Transcription
1 Instruction Set Architecture part 1 (Introduction) Mehran Rezaei
2 Overview Last Lecture s Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter MIPS Arithmetic Instructions Register File and Register Naming Convention 2
3 Review Intro to Computer Architecture Course Style, Philosophy and Structure High Level, Assembly, Machine Language Anatomy of computer system 3
4 Execution Cycle Instruction Fetch Instruction Decode Operand Fetch Execute Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Result Store Deposit results in storage for later use Next Instruction Determine successor instruction 4
5 assembler Different levels of computer language Need to communicate with each other The same thing with computers High level language Assembly language Machine code Natural Different purposes More understandable Better Debugged Portable Better Optimized 5
6 Different levels of computer language (Cont d) High Level Language Program strange(... ){... } Assembly Language strange: sll $2,$4,2 addu $6,$6,$2... Machine code compiler assembler 6
7 Stored Program Computer 7
8 Stored Program Computer (object code in memory) 8
9 The process of executing instructions Instruction Fetch PC has the address of the next instruction to be fetched so the control unit fetches the instruction whose address is in PC, and puts it into IR. 9
10 Next Cycle:? Control unit decodes the instruction and fetches the operands 10
11 Execute Data path executes the instruction as directed by the Control unit 11
12 Instruction formats in R3000 Instruction Categories Load/Store Computational Jump and Branch Floating Point coprocessor Memory Management Special 3 Instruction Formats: all 32 bits wide Registers R0 - R31 PC HI LO R-format I-format J-format OP OP OP rs rt rd sa funct rs rt immediate jump target 12
13 Executes (Reg Reg) Data path executes the instruction as directed by the Control unit 13
14 Mem (Reg Reg) No operation takes place in this cycle 14
15 WB (Reg Reg) Result will be put into Reg #2 15
16 Question What if the CPU executes a load instruction lw $2,504($1) what happens in Exe, Mem, and WB 16
17 RISC: Reduced Instruction Set Computer RISC philosophy Fixed instruction length Load/store instruction set Limited addressing modes Limited operations Examples Alpha processor, Sun SPARC, SGI MIPS, Design a good instruction set How well compilers use it; compiler optimization 17
18 Homework Assignment SPIM a MIPS Interpreter 18
19 MIPS Arithmetic Instructions Assembly arithmetic statement add $3, $1, $2 sub $3, $1, $2 Each arithmetic instruction performs only one operation Each arithmetic instruction specifies exactly three operands Destination source1 op source2 The operands should be the contents of the datapath s register files The operand s order is fix: Destination first 19
20 An example If b is in register $1, c in $2, d in $3, and the result supposed to be in $4 h = (b c) + d sub $5, $1, $2 add $4, $5, $3 20
21 MIPS Register file Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath s register file Holds thirty-two 32-bit registers 2 read ports 1 write port Registers are Faster than main memory Easier for compiler to use (a * b) (c * d) (e * f) any order of these multiplication Can hold variables so that Code density is improved (fewer bits used to address registers than memory locations) 21
22 interface Register file (Cont d) 32 bits R#0 src1 addr src2 addr dest addr interface R#1 R# src1 data src2 data R# Write Back data
23 Register file (Cont d) 23
24 Register spilling More about Registers Limited number of registers Compilers place not commonly used registers back into memory Why registers are faster? Small register file Difference in technology Higher throughput in register operations, therefore higher throughput in register file 24
25 Naming Convention for registers 0 zero constant 0 1 at reserved for assembler 2 v0 expression evaluation & 3 v1 function results 4 a0 arguments 5 a1 6 a2 7 a3 8 t0 temporary: caller saves... (callee can clobber) 15 t7 16 s0 callee saves... (caller can clobber) 23 s7 24 t8 temporary (cont d) 25 t9 26 k0 reserved for OS kernel 27 k1 28 gp Pointer to global area 29 sp Stack pointer 30 fp frame pointer 31 ra Return Address (HW) 25
26 Compile example f = g + h + i if f is in $s0, g in $s1, h in $s2, i in $s3 add $s0,$s1,$s2 add $s0,$s0,$s3 f = (g + h) (i + j) if f is in $s0, g in $s1, h in $s2, i in $s3, and j in $s4 26
27 Compile Data transfer instructions G = h - A[7]; address of A[0] is in $s1, G in $s2, and h in $s3 27
28 Compile Example A[20] += A[8]; address of A[0] is in $s1 29
29 Anatomy of data transfer inst. lw $t0, 5($s1) offset Base register Index register (why?) 30
30 Instructions, so far Translate to machine code A[20] +=A[8]; 31
31 Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter MIPS and Register File Register Naming convention 32
32 Today s class Register Naming Convention, a review MIPS Arithmetic, Load/store and logical instructions slt and jr instructions Branches and jumps pc relative addressing 33
33 Naming Convention for registers 0 zero constant 0 1 at reserved for assembler 2 v0 expression evaluation & 3 v1 function results 4 a0 arguments 5 a1 6 a2 7 a3 8 t0 temporary: caller saves... (callee can clobber) 15 t7 16 s0 callee saves... (caller can clobber) 23 s7 24 t8 temporary (cont d) 25 t9 26 k0 reserved for OS kernel 27 k1 28 gp Pointer to global area 29 sp Stack pointer 30 fp frame pointer 31 ra Return Address (HW) 34
34 Compile Example A[20] += A[8]; address of A[0] is in $s1 35
35 Anatomy of data transfer inst. lw $t0, 5($s1) offset Base register Index register (why?) 36
36 Instructions, so far Translate to machine code A[20] +=A[8]; 37
37 Shifters Two kinds: logical-- value shifted in is always "0" "0" msb lsb "0" arithmetic-- on right shifts, sign extend msb lsb "0" Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted! 38
38 MIPS logical instructions and $1,$2,$3 $1 = $2 & $3 or $1,$2,$3 $1 = $2 $3 nor $1,$2,$3 $1 = ~($2 $3) andi $1,$2,10 $1 = $2 & 10 ori $1,$2,10 $1 = $2 10 sll $1,$2,10 $1 = $2 << 10 srl $1,$2,10 $1 = $2 >> 10 sra $1,$2,10 $1 = $2 >> 10 39
39 A different style Make access to small constant fast Application for(j=0;j<10;j++) A[j]++; Profile analysis shows: In gcc 52% In spice 69% Of arithmetic instructions involve constants op rs rt immediate addi $s4,$s4,4 40
40 A tiny problem What if the immediate value is beyond the range that 16 bits can provide By the way, what is this range? lui $s1,5 $s What if I want to load 5* to $s1? Who is responsible for doing this? MIPS provides $at for such cases 41
41 American Std Code for Info. Interchange (ASCII) 42
42 Load and store bytes lb $t0,0($sp) sb $t1,4($sp) $sp 43
43 Alignment MIPS requires that all words start at addresses that are multiples of 4 bytes Aligned Not Aligned Called Alignment: objects must fall on address that is multiple of their size. Why do we care? 44
44 Endian-ness or Edianess Big Endian: Leftmost byte is word address Little Endian: Rightmost byte is word address little endian msb lsb Big endian
45 MIPS arithmetic instruction format R-type: I-Type: op Rs Rt Rd funct op Rs Rt Immed 16 Type op funct ADDI 10 xx ADDIU 11 xx SLTI 12 xx SLTIU 13 xx ANDI 14 xx ORI 15 xx XORI 16 xx LUI 17 xx Type op funct ADD ADDU SUB SUBU AND OR XOR NOR Type op funct SLT SLTU
46 lbu $t0,0($s0) lb $t0,0($s0) New instructions Extension $t0 94H $s0 94H 47
47 Examples 0X4E + 0X1F 0X4E 0X1F Overflow Addition/Subtraction operation condition result A + B A > 0 B > 0 < 0 A + B A < 0 B < 0 > 0 A - B A > 0 B < 0 < 0 A - B A < 0 B > 0 > 0 48
48 What to do on overflow? Ignore Programmer is responsible for Leave it to OS Either completely takes care of it Or signals the application What does MIPS do? For signed operation (if overflow occurs) it throws an exception It ignores the overflow of unsigned operations 49
49 PC -> EPC If an overflow is detected mfc0 places EPC to a register ($k0 and $k1 are used for such a purpose) Jump to a code which services the interrupt based on the type of the interrupt Resolve the problem Return with an error code Abort program 50
50 More in overflow No means to check if overflow occurs in MIPS Question: How would I indicate that an overflow occur? For signed operations Unsigned operations 51
51 Instructions for making decisions Conditional/Unconditional branches beq bne j Example Compile $s1,$s2, L1 $s3,$s4, L2 L3 if(i == j) f = g + h k; else f = g + h + k; Given i: $s1, j: $s2, f: $s3, g: $s4, h: $s5, and k: $s6 52
52 More examples compile Loop: g += A[i]; i += j; if(i!= h) goto Loop; 53
53 Compile a while loop while (save[j] == k) j += n; Loop: if(save[j]!= k) goto Exit; j += n; goto Loop; Exit: 54
54 Hierarchical Interpretation of an Application (Executable file) Executable File Object Object procedure procedure Basic block Basic block instruction 55
55 slt $s1,$s2,$s3 if $s2 < $s3 set $s1 to 1 else set $s1 to 0 New Instructions jr $s0 jump to the address given by the $s0 56
56 I-Type Branches (Conditional) bne $s0, $s1, Exit Exit What seems to be the problem? 57
57 PC Relative addressing MIPS adds the content of PC to the immediate field to provide a wider range. Why? 50% of conditional branch targets in gcc are smaller than 16 instructions apart from their origin bne $s0, $s1, address PC = (PC + 4) + 4*address What is the range of the branching? What if you need branch farther than that? We will come back to this shortly. 58
58 J-Type Unconditional Branches opcode Target address What range could it provide? Keep in your mind that J-Type is also word address In J-Type 4 upper bits of the PC will be unchanged Do not place the program across the boundary of 256 MB : 64 million instructions 59
59 bne $s1,$s2, L1 Final Question and L1 is beyond [-2 17, 2 17 ] apart from PC 60
60 Function calls and Procedures What is the difference between a function call and a procedure? Leaf versus Recursive What is needed for supporting the procedure calls by hardware? 61
61 Registers 0 zero constant 0 1 at reserved for assembler 2 v0 expression evaluation & 3 v1 function results 4 a0 arguments 5 a1 6 a2 7 a3 8 t0 temporary: caller saves... (callee can clobber) 15 t7 16 s0 callee saves... (caller can clobber) 23 s7 24 t8 temporary (cont d) 25 t9 26 k0 reserved for OS kernel 27 k1 28 gp Pointer to global area 29 sp Stack pointer 30 fp frame pointer 31 ra Return Address (HW) 62
62 Instructions jal x (again jal is also word address) $ra= PC + 4 Jump to the address 4*x Instruction type is J with opcode 3 jr $ra Which we have seen already and jump to the instruction whose address is in the register; in this case we have return address register Instruction type is R with opcode 0 and func 8 63
63 Steps for Making a Procedure Call 1. Save necessary values onto stack 2. Assign argument(s), if any $a0 - $a3 for arguments 3. jal call 4. Restore values from stack 64
64 Steps taken by the Callee 1. Acquire the storage resources needed If need any of $s registers, should save them onto the stack, and after use restore them back to the registers 2. Perform the desired task 3. Place the result values in $v0 and $v1 4. jr $ra 65
65 Rules for Procedures Called with a jal instruction, returns with a jr $ra Accepts up to 4 arguments in $a0, $a1, $a2 and $a3 Return value is always in $v0 (and if necessary in $v1) Must follow register conventions (even in functions that only you will call)! 66
66 Hand - Compile Example int leaf(int g,int h,int i,int j){ int f; f = (g + h) (i + j); return f; } 67
67 MIPS memory layout 68
68 Example Hand - compile int leaf(int arg){ int l=10; return l*arg; } main(){ int j; j = leaf(5); } 69
69 Recursive Calls int fact(int n){ if(n <= 1) return 1; return n * fact(n-1); } int fact(int n){ int a; int b; if(n <= 1) return 1; a = fact(n 1); b = n * a; return b; } 70
70 Recursive Calls (Cont d) main(){ int j=fact(3); } fact(3){ a=fact(2); b=3*a; return b; } fact(2){ a=fact(1); b=2*a; return b; } 71
71 How to represent strings Use the beginning of the string for the length (4 bytes) Accompany string with a variable length Use a special character at the end of the string as an indication of string s end (C uses null for that purpose) 72
72 Example Hand compile strcat(char s[], char t[]){ int i,j; i=j=0; while(s[i]!= 0) i++; while((s[i++] = t[j++])!= 0); } 73
73 Some Words about SPIM Comments, Identifiers, Labels, Number representation, Strings, and Special Characters Some assembly directives.text <addr>.data <addr> Mydata:.word 1,2,3.ascii str1.asciiz str2 74
74 System Calls What is a system call? SPIM provides a small set of system calls How does it work? Load syscall code into $v0 Load arguments (if any) into $a0,, $a3 Issue syscall 75
Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei
Computer Architecture Instruction Set Architecture part 2 Mehran Rezaei Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA
CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization
CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationChapter 2A Instructions: Language of the Computer
Chapter 2A Instructions: Language of the Computer Copyright 2009 Elsevier, Inc. All rights reserved. Instruction Set The repertoire of instructions of a computer Different computers have different instruction
More informationCENG3420 Lecture 03 Review
CENG3420 Lecture 03 Review Bei Yu byu@cse.cuhk.edu.hk 2017 Spring 1 / 38 CISC vs. RISC Complex Instruction Set Computer (CISC) Lots of instructions of variable size, very memory optimal, typically less
More informationAnnouncements HW1 is due on this Friday (Sept 12th) Appendix A is very helpful to HW1. Check out system calls
Announcements HW1 is due on this Friday (Sept 12 th ) Appendix A is very helpful to HW1. Check out system calls on Page A-48. Ask TA (Liquan chen: liquan@ece.rutgers.edu) about homework related questions.
More informationReduced Instruction Set Computer (RISC)
Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the machine. Reduced number of cycles needed per instruction.
More informationInstructions: Language of the Computer
CS359: Computer Architecture Instructions: Language of the Computer Yanyan Shen Department of Computer Science and Engineering 1 The Language a Computer Understands Word a computer understands: instruction
More informationComputer Architecture. The Language of the Machine
Computer Architecture The Language of the Machine Instruction Sets Basic ISA Classes, Addressing, Format Administrative Matters Operations, Branching, Calling conventions Break Organization All computers
More information101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009
101 Assembly ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 What is assembly? 79 Why are we learning assembly now? 80 Assembly Language Readings: Chapter 2 (2.1-2.6, 2.8, 2.9, 2.13, 2.15), Appendix
More informationComputer Organization MIPS ISA
CPE 335 Computer Organization MIPS ISA Dr. Iyad Jafar Adapted from Dr. Gheith Abandah Slides http://www.abandah.com/gheith/courses/cpe335_s08/index.html CPE 232 MIPS ISA 1 (vonneumann) Processor Organization
More informationReduced Instruction Set Computer (RISC)
Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the ISA. RISC Goals RISC: Simplify ISA Simplify CPU Design Better CPU Performance Motivated by simplifying
More informationChapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )
Chapter 2 Computer Abstractions and Technology Lesson 4: MIPS (cont ) Logical Operations Instructions for bitwise manipulation Operation C Java MIPS Shift left >>> srl Bitwise
More informationECE232: Hardware Organization and Design. Computer Organization - Previously covered
ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization
More informationMIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions
Representing Instructions Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register
More informationLecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)
Lecture 2 Instructions: Language of the Computer (Chapter 2 of the textbook) Instructions: tell computers what to do Chapter 2 Instructions: Language of the Computer 2 Introduction Chapter 2.1 Chapter
More informationChapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes
Chapter 2 Instructions: Language of the Computer Adapted by Paulo Lopes Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects
More informationComputer Architecture
Computer Architecture Chapter 2 Instructions: Language of the Computer Fall 2005 Department of Computer Science Kent State University Assembly Language Encodes machine instructions using symbols and numbers
More informationCENG3420 L03: Instruction Set Architecture
CENG3420 L03: Instruction Set Architecture Bei Yu byu@cse.cuhk.edu.hk (Latest update: January 31, 2018) Spring 2018 1 / 49 Overview Introduction Arithmetic & Logical Instructions Data Transfer Instructions
More informationMath 230 Assembly Programming (AKA Computer Organization) Spring 2008
Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro II Lect 10 Feb 15, 2008 Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L10.1
More informationControl Instructions. Computer Organization Architectures for Embedded Computing. Thursday, 26 September Summary
Control Instructions Computer Organization Architectures for Embedded Computing Thursday, 26 September 2013 Many slides adapted from: Computer Organization and Design, Patterson & Hennessy 4th Edition,
More informationControl Instructions
Control Instructions Tuesday 22 September 15 Many slides adapted from: and Design, Patterson & Hennessy 5th Edition, 2014, MK and from Prof. Mary Jane Irwin, PSU Summary Previous Class Instruction Set
More informationMIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support
Components of an ISA EE 357 Unit 11 MIPS ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible
More informationChapter 2. Instructions: Language of the Computer. HW#1: 1.3 all, 1.4 all, 1.6.1, , , , , and Due date: one week.
Chapter 2 Instructions: Language of the Computer HW#1: 1.3 all, 1.4 all, 1.6.1, 1.14.4, 1.14.5, 1.14.6, 1.15.1, and 1.15.4 Due date: one week. Practice: 1.5 all, 1.6 all, 1.10 all, 1.11 all, 1.14 all,
More informationToday s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.
Today s topics CS/COE1541: Introduction to Computer Architecture MIPS operations and operands MIPS registers Memory view Instruction encoding A Review of MIPS ISA Sangyeun Cho Arithmetic operations Logic
More informationInstructions: Language of the Computer
Instructions: Language of the Computer Tuesday 22 September 15 Many slides adapted from: and Design, Patterson & Hennessy 5th Edition, 2014, MK and from Prof. Mary Jane Irwin, PSU Summary Previous Class
More informationMIPS%Assembly% E155%
MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary
More informationBranch Addressing. Jump Addressing. Target Addressing Example. The University of Adelaide, School of Computer Science 28 September 2015
Branch Addressing Branch instructions specify Opcode, two registers, target address Most branch targets are near branch Forward or backward op rs rt constant or address 6 bits 5 bits 5 bits 16 bits PC-relative
More informationComputer Architecture
CS3350B Computer Architecture Winter 2015 Lecture 4.2: MIPS ISA -- Instruction Representation Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and Design,
More informationStored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands
Stored Program Concept Instructions: Instructions are bits Programs are stored in memory to be read or written just like data Processor Memory memory for data, programs, compilers, editors, etc. Fetch
More informationCS3350B Computer Architecture MIPS Instruction Representation
CS3350B Computer Architecture MIPS Instruction Representation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada
More informationCS 61c: Great Ideas in Computer Architecture
MIPS Functions July 1, 2014 Review I RISC Design Principles Smaller is faster: 32 registers, fewer instructions Keep it simple: rigid syntax, fixed instruction length MIPS Registers: $s0-$s7,$t0-$t9, $0
More informationCourse Administration
Fall 2017 EE 3613: Computer Organization Chapter 2: Instruction Set Architecture 2/4 Avinash Kodi Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio 45701 E-mail: kodi@ohio.edu
More informationCOMPUTER ORGANIZATION AND DESIGN
COMPUTER ORGANIZATION AND DESIGN 5 th The Hardware/Software Interface Edition Chapter 2 Instructions: Language of the Computer 2.1 Introduction Instruction Set The repertoire of instructions of a computer
More informationRecap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011
CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-3 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language
More informationELEC / Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2)
ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2) Victor P. Nelson, Professor & Asst. Chair Vishwani D. Agrawal, James J. Danaher Professor Department
More information5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers
CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-2 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language
More informationMath 230 Assembly Programming (AKA Computer Organization) Spring MIPS Intro
Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L09.1 Smith Spring 2008 MIPS
More informationMIPS Instruction Set Architecture (2)
MIPS Instruction Set Architecture (2) Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu
More informationComputer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#:
Computer Science and Engineering 331 Midterm Examination #1 Fall 2000 Name: Solutions S.S.#: 1 41 2 13 3 18 4 28 Total 100 Instructions: This exam contains 4 questions. It is closed book and notes. Calculators
More informationMark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA
EE 357 Unit 11 MIPS ISA Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible
More informationComputer Architecture. MIPS Instruction Set Architecture
Computer Architecture MIPS Instruction Set Architecture Instruction Set Architecture An Abstract Data Type Objects Registers & Memory Operations Instructions Goal of Instruction Set Architecture Design
More informationECE 331 Hardware Organization and Design. Professor Jay Taneja UMass ECE - Discussion 3 2/8/2018
ECE 331 Hardware Organization and Design Professor Jay Taneja UMass ECE - jtaneja@umass.edu Discussion 3 2/8/2018 Study Jams Leader: Chris Bartoli Tuesday 5:30-6:45pm Elab 325 Wednesday 8:30-9:45pm Elab
More informationcomp 180 Lecture 10 Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions
Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions Procedure Calls A procedure of a subroutine is like an agent which needs certain information to perform a
More informationMIPS Instruction Set
MIPS Instruction Set Prof. James L. Frankel Harvard University Version of 7:12 PM 3-Apr-2018 Copyright 2018, 2017, 2016, 201 James L. Frankel. All rights reserved. CPU Overview CPU is an acronym for Central
More informationIntroduction to the MIPS. Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University
Introduction to the MIPS Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University Introduction to the MIPS The Microprocessor without Interlocked Pipeline Stages
More informationInstructions: MIPS ISA. Chapter 2 Instructions: Language of the Computer 1
Instructions: MIPS ISA Chapter 2 Instructions: Language of the Computer 1 PH Chapter 2 Pt A Instructions: MIPS ISA Based on Text: Patterson Henessey Publisher: Morgan Kaufmann Edited by Y.K. Malaiya for
More informationComputer Organization and Structure. Bing-Yu Chen National Taiwan University
Computer Organization and Structure Bing-Yu Chen National Taiwan University Instructions: Language of the Computer Operations and Operands of the Computer Hardware Signed and Unsigned Numbers Representing
More informationWe will study the MIPS assembly language as an exemplar of the concept.
MIPS Assembly Language 1 We will study the MIPS assembly language as an exemplar of the concept. MIPS assembly instructions each consist of a single token specifying the command to be carried out, and
More informationThe MIPS Instruction Set Architecture
The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use
More informationCS31001 COMPUTER ORGANIZATION AND ARCHITECTURE. Debdeep Mukhopadhyay, CSE, IIT Kharagpur. Instructions and Addressing
CS31001 COMPUTER ORGANIZATION AND ARCHITECTURE Debdeep Mukhopadhyay, CSE, IIT Kharagpur Instructions and Addressing 1 ISA vs. Microarchitecture An ISA or Instruction Set Architecture describes the aspects
More informationConcocting an Instruction Set
Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.7 L03 Instruction Set 1 A General-Purpose Computer The von
More informationEEC 581 Computer Architecture Lecture 1 Review MIPS
EEC 581 Computer Architecture Lecture 1 Review MIPS 1 Supercomputing: Suddenly Fancy 2 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control
More informationChapter 2. Instructions: Language of the Computer
Chapter 2 Instructions: Language of the Computer Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects in common Early computers
More informationCOMPSCI 313 S Computer Organization. 7 MIPS Instruction Set
COMPSCI 313 S2 2018 Computer Organization 7 MIPS Instruction Set Agenda & Reading MIPS instruction set MIPS I-format instructions MIPS R-format instructions 2 7.1 MIPS Instruction Set MIPS Instruction
More informationMachine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine
Machine Language Instructions Introduction Instructions Words of a language understood by machine Instruction set Vocabulary of the machine Current goal: to relate a high level language to instruction
More informationLecture 5: Procedure Calls
Lecture 5: Procedure Calls Today s topics: Memory layout, numbers, control instructions Procedure calls 1 Memory Organization The space allocated on stack by a procedure is termed the activation record
More informationProcessor. Han Wang CS3410, Spring 2012 Computer Science Cornell University. See P&H Chapter , 4.1 4
Processor Han Wang CS3410, Spring 2012 Computer Science Cornell University See P&H Chapter 2.16 20, 4.1 4 Announcements Project 1 Available Design Document due in one week. Final Design due in three weeks.
More informationENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5
ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 $zero all bits are zero 16 $s0 local variable 1 $at assembler temporary 17 $s1 local
More informationDo-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero
Do-While Example In C++ do { z--; while (a == b); z = b; In assembly language loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero 25 Comparisons Set on less than (slt) compares its source registers
More informationECE232: Hardware Organization and Design
ECE232: Hardware Organization and Design Lecture 4: Logic Operations and Introduction to Conditionals Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Overview Previously examined
More informationMIPS Assembly Language. Today s Lecture
MIPS Assembly Language Computer Science 104 Lecture 6 Homework #2 Midterm I Feb 22 (in class closed book) Outline Assembly Programming Reading Chapter 2, Appendix B Today s Lecture 2 Review: A Program
More informationProcedure Calling. Procedure Calling. Register Usage. 25 September CSE2021 Computer Organization
CSE2021 Computer Organization Chapter 2: Part 2 Procedure Calling Procedure (function) performs a specific task and return results to caller. Supporting Procedures Procedure Calling Calling program place
More informationComputer Organization and Structure. Bing-Yu Chen National Taiwan University
Computer Organization and Structure Bing-Yu Chen National Taiwan University Instructions: Language of the Computer Operations and Operands of the Computer Hardware Signed and Unsigned Numbers Representing
More informationToday s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats
Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:
More informationA General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction
page 1 Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... A General-Purpose Computer The von Neumann Model Many architectural approaches
More informationThomas Polzer Institut für Technische Informatik
Thomas Polzer tpolzer@ecs.tuwien.ac.at Institut für Technische Informatik Branch to a labeled instruction if a condition is true Otherwise, continue sequentially beq rs, rt, L1 if (rs == rt) branch to
More informationCSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI.
CSCI 402: Computer Architectures Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI Recall Big endian, little endian Memory alignment Unsigned
More informationCharacter Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21
2.9 Communication with People: Byte Data & Constants Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21 32: space 33:! 34: 35: #...
More informationCS3350B Computer Architecture
CS3350B Computer Architecture Winter 2015 Lecture 4.1: MIPS ISA: Introduction Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted d from lectures on Computer Organization and Design, Patterson & Hennessy,
More informationArchitecture II. Computer Systems Laboratory Sungkyunkwan University
MIPS Instruction ti Set Architecture II Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Making Decisions (1) Conditional operations Branch to a
More informationMIPS Memory Access Instructions
MIPS Memory Access Instructions MIPS has two basic data transfer instructions for accessing memory lw $t0, 4($s3) #load word from memory sw $t0, 8($s3) #store word to memory The data is loaded into (lw)
More informationInstruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers
CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers $0 $31 Multiply divide Coprocessor 1 (FPU) Registers
More informationRechnerstrukturen. Chapter 2. Instructions: Language of the Computer
182.690 Rechnerstrukturen Chapter 2 Instructions: Language of the Computer Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many
More informationMIPS Reference Guide
MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming
More informationCS3350B Computer Architecture MIPS Introduction
CS3350B Computer Architecture MIPS Introduction Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada Thursday January
More informationConcocting an Instruction Set
Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.6 L04 Instruction Set 1 A General-Purpose Computer The von
More informationRui Wang, Assistant professor Dept. of Information and Communication Tongji University.
Instructions: ti Language of the Computer Rui Wang, Assistant professor Dept. of Information and Communication Tongji University it Email: ruiwang@tongji.edu.cn Computer Hierarchy Levels Language understood
More informationChapter 3 MIPS Assembly Language. Ó1998 Morgan Kaufmann Publishers 1
Chapter 3 MIPS Assembly Language Ó1998 Morgan Kaufmann Publishers 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive
More informationCSE 141 Computer Architecture Spring Lecture 3 Instruction Set Architecute. Course Schedule. Announcements
CSE141: Introduction to Computer Architecture CSE 141 Computer Architecture Spring 2005 Lecture 3 Instruction Set Architecute Pramod V. Argade April 4, 2005 Instructor: TAs: Pramod V. Argade (p2argade@cs.ucsd.edu)
More informationEE108B Lecture 3. MIPS Assembly Language II
EE108B Lecture 3 MIPS Assembly Language II Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Urgent: sign up at EEclass and say if you are taking 3 or 4 units Homework
More informationA Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3
A Processor Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Let s build a MIPS CPU but using Harvard architecture Basic Computer System Registers ALU
More informationCS61C Machine Structures. Lecture 12 - MIPS Procedures II & Logical Ops. 2/13/2006 John Wawrzynek. www-inst.eecs.berkeley.
CS61C Machine Structures Lecture 12 - MIPS Procedures II & Logical Ops 2/13/2006 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS 61C L12 MIPS Procedures II / Logical (1)
More informationAnne Bracy CS 3410 Computer Science Cornell University. See P&H Chapter: , , Appendix B
Anne Bracy CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer. See P&H Chapter: 2.16-2.20, 4.1-4.4,
More informationMachine Instructions - II. Hwansoo Han
Machine Instructions - II Hwansoo Han Conditional Operations Instructions for making decisions Alter the control flow - change the next instruction to be executed Branch to a labeled instruction if a condition
More informationCPS311 - COMPUTER ORGANIZATION. A bit of history
CPS311 - COMPUTER ORGANIZATION A Brief Introduction to the MIPS Architecture A bit of history The MIPS architecture grows out of an early 1980's research project at Stanford University. In 1984, MIPS computer
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:
More informationInstructions: MIPS arithmetic. MIPS arithmetic. Chapter 3 : MIPS Downloaded from:
Instructions: Chapter 3 : MIPS Downloaded from: http://www.cs.umr.edu/~bsiever/cs234/ Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive
More informationSPIM Instruction Set
SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large
More informationEEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture
EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 Overview Instruction Representation Big idea: stored program consequences of stored program Instructions as numbers Instruction
More informationOverview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)
Introduction to the MIPS ISA Overview Remember that the machine only understands very basic instructions (machine instructions) It is the compiler s job to translate your high-level (e.g. C program) into
More informationLecture 4: MIPS Instruction Set
Lecture 4: MIPS Instruction Set No class on Tuesday Today s topic: MIPS instructions Code examples 1 Instruction Set Understanding the language of the hardware is key to understanding the hardware/software
More informationMIPS Datapath. MIPS Registers (and the conventions associated with them) MIPS Instruction Types
1 Lecture 08 Introduction to the MIPS ISA + Procedure Calls in MIPS Longer instructions = more bits to address registers MIPS Datapath 6 bit opcodes... 2 MIPS Instructions are 32 bits More ways to address
More informationChapter 1. Computer Abstractions and Technology. Lesson 3: Understanding Performance
Chapter 1 Computer Abstractions and Technology Lesson 3: Understanding Performance Manufacturing ICs 1.7 Real Stuff: The AMD Opteron X4 Yield: proportion of working dies per wafer Chapter 1 Computer Abstractions
More informationMIPS (SPIM) Assembler Syntax
MIPS (SPIM) Assembler Syntax Comments begin with # Everything from # to the end of the line is ignored Identifiers are a sequence of alphanumeric characters, underbars (_), and dots () that do not begin
More informationChapter 2: Instructions:
Chapter 2: Instructions: Language of the Computer Computer Architecture CS-3511-2 1 Instructions: To command a computer s hardware you must speak it s language The computer s language is called instruction
More informationMIPS ISA and MIPS Assembly. CS301 Prof. Szajda
MIPS ISA and MIPS Assembly CS301 Prof. Szajda Administrative HW #2 due Wednesday (9/11) at 5pm Lab #2 due Friday (9/13) 1:30pm Read Appendix B5, B6, B.9 and Chapter 2.5-2.9 (if you have not already done
More informationCS 4200/5200 Computer Architecture I
CS 4200/5200 Computer Architecture I MIPS Instruction Set Architecture Dr. Xiaobo Zhou Department of Computer Science CS420/520 Lec3.1 UC. Colorado Springs Adapted from UCB97 & UCB03 Review: Organizational
More informationStored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands
Stored Program Concept nstructions: nstructions are bits Programs are stored in memory to be read or written just like data Processor Memory memory for data, programs, compilers, editors, etc. Fetch &
More informationChapter 2. Instructions:
Chapter 2 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive e.g., MIPS Arithmetic Instructions We ll be working with
More information