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1 G_tech Multiplier Fast Multiplier using Vedic Mathematics Datasheet and Manual

2 1. G_tech Multiplier Application Procedure 1.1. Features This is 37 pin IC used for multiplication based on Vedic Mathematics. It can multiply 2-8 bit (A [7:0] & B [7:0]) input binary digits and the resultant is 16 bits (Y[15:0]) output binary digits. Can operate at different clock frequency with minimum clock time period of 4 ns with 50% duty cycle. The result is ready to read once output pin Done is high. The time required to output the result is 4 time cycles considering timing issue and retiming issue. Time required for each computation is directly dependent on input clock. It works on Vdd voltage as 5Vdc and Gnd pin to 0Vdc/Reference ground. For all stable input output is stable, even if the input value changes during the computation the value is not affected. Design is based on serial, parallel and additional computation logic that 1.2. Description As the name suggest it is a fast multiplier based on Vedic Mathematics. Vedic mathematics is a system of mathematics consisting of a list of 16 basic sūtras, oraphorisms. They were presented by a Hindu scholar and mathematician, Jagadguru Swami Sri Bharati Krishna Tirthaji Maharaja, during the early part of the 20th century[1]. Tirthaji claims that he found the sūtras after years of studying the Vedas, a set of sacred ancient Hindu texts[2]. However, labeling the mathematics he presented as Vedic has provoked great controversy amongst Indian mathematicians who question both the Vedic origin of the mathematics, and whether the sūtras can fulfill the claim of encompassing all mathematics. Nonetheless, the calculation strategies provided by Vedic mathematics are creative and useful, and can be applied in a number of ways to calculation methods in arithmetic and algebra, most notably within the education system. As most of the digital input are in the form of 0 s and 1 s we can use few basic principles (Sutra s) for performing multiplication.

3 Vedic Sutra/Principle used in G_tech Multiplier: Multiplying by = 00 (1) The product of any number multiplied by 0 is always 0. Multiplying by = 35 (1) The product of any number multiplied by 1 is the number itself. (2) The eight in the answer is the sum of 35 (3+5=8). (3) The three in the hundreds place of the answer is taken from the three in 35. Multiplying by = 350 (1) For any number is in form of 1 followed by 0 s then the result is nothing but the number followed by the number of 0 s in the multiplying number. Multiplying by = 385 (1) The five in the ones place of the answer is taken from the five in 35. (2) The eight in the answer is the sum of 35 (3+5=8). (3) The three in the hundreds place of the answer is taken from the three in 35. This technique can be applied for multiplication of any given digits of a numbers.

4 1.3. Algorithm Fig:1 : Algorithm used for implementation of the design. The design was implemented keeping in mind that less number of registers to be used and also most of the design uses half adders except the final stage which gives a plus to the algorithm to execute the result faster. Thought the algorithm is the not claimed to be the best in the market but it is one of the most competitive method keeping in mind number of registers used and the speed. As in conventional method uses more register thought the computation can be done serial which is slow and parallel computation require more register. In modern day method thought the computation is done parallel and through help of pipelining which require additional processing and computation logic. This algorithm uses both parallel and serial computation with and additional processing logic for fast computation.

5 1.4. Block Diagram Fig:2 : Block Diagram for the algorithm for implementations of the design.

6 Idea for this project was designed aiming for fast computation with less hardware. The design us based on Vedic mathematics i.e. efficient and faster way of computation for human brain. So the whole idea was to mimic the human thinking and help the computation Arithmetic block faster and realize then with less hardware. There are some guidelines to be followed for implementation of G_tech multiplier. The primary step is to divide the multiplicand into 2 bit pair and then apply the rules give below for each pair with respect to multiplier. And then apply any one rule based on the its value and compute the primary result for the algorithm. Rule for Algorithm implementation: 00 Do nothing 01 Add only the multiplier by the previous result 10 Add 0 to LSB of Multiplier and add to previous result 11 Use simple Vedic logic of adding the neighbor digit to obtain the number and add to the previous result Calculating value for Step 1 of algorithm: Above rules are used for calculation of the values for step 1 based on different input combination. All the Step 1 value are calculated in parallel. With the edge of clock input these values are then passed to Step2. Simple example for multiplying 4 bit number based on above table is as shown below. Example: Multiplicant A Multiply B For Bit (B0-B1) (1_1)bits For Bit (B2-B3) (0_1)bits Add Result Weighted Value Example 1: If the number 1010 is to be multiplied by 0111 then the result will be ( ) ie : 10.d * 7.d = 70.d (.d- decimal numbers). Thus it is proved that the method that that can be used in to multiply 11 decimal number can be used for the binary 11. This can be realized by the formulating it in a coded form in verilog and the implement. As the design seems to be simple in implementation the design complexity increases with the increase in the data input bits and hence in Step 2 and Step 3 different approach was followed for fast computation of the design. The design will then have set of 4 unique value based on each pair of bits. The registers were grouped alternately to generate the Step 2 results. As we know that for any normal multiplication the maximum addition takes place in the center bits and these bit calculate the critical path or the maximum speed of the design. Keeping this basic in mind and using the concept of retiming the lower and the higher bits in the design used to generate and add the carry in the same cycle. This simply means that if the resultant bit is

7 directly propagated at the output then can wait for previous stage carry. But if the addition is between two bit then don t wait for previous carry either add to get secondary resultant and carry bits separately. The bits in the center where the addition required full adder to add with carry were replaced by half adder to add without carry. Carry for these stages were stored in separate register and then used in Step 3 for calculating the carry and secondary result separately. Thus combination of serial and parallel combination was used to have after calculation. The result so obtained are pair of secondary resultant and partial carry information. In Step 3 this resultant and carry are added sepearately and then merged all together in Step 4. Thus at every edge of clock input the data propagates to next step thus having better timing for the design.

8 1.5. State diagram Fig:4 :State Diagram for the implementation

9 The state diagram above is for the practical implementation of the algorithm design. The default state of the design in clear state i.e. S0 state when ever the clock edge appears, conditional logic checks for the clear bit. If the clear bit is high it will output 0000h at the output else it will enter the state S1 of the state diagram. This state is nothing but the Step 1 of the algorithm, where we calculate 4 different values primary resultant value. Then on next clock edge the computed data acts as input to S2 state. This state will be mapped to the Step 2 of the algorithm. In this state we generate sum of alternate values of register and the partial carry. Based in the clock edge the data is then passed over to the next state for addition of sum and carry separately. Then in the final stage all the separate sum and carry value are added together to calculate the final result. Only when the done pin is high in the final state S4 which indicated that the result is ready to read. The only rigidity of the design is if the input changes, there will be no effect on the computation. The computation will be based on the value of input when the clock edge appeared for the state S1.

10 1.6. Terminal Implementation Pin Diagram Fig:5 : General block description of the design Detailed pin diagram Fig:6 : Detailed Pin Description of the design

11 Pin Description Pin Name Vdd Gnd Clock Clear A[7:0] B[7:0] Y[15:0] Done Description Supply input pin of the IC Supply ground or reference pin of the IC Clock input to the design. Design works in the same input frequency Input pin used to start the multiplication or to reset the output. If Clear = 1 then output is 0000h Clear = 0 for normal operation 8 - Input multiplier bits 8 - Input multiplicand bits 16- Output result bits Result statue indicator. If Done = 1 then output result is ready to read Done = 0 then output result not ready to read Different test were carried out to find the minimum operating frequency of the clock and it was observed that the minimum operation frequency for the clock is 4ns (total time period) with 50% duty cycle.

1.6.4. Design Specification and Characteristics 1.6.4.1. Pad Frame Fig:7 :Tiny frame Layout used in Design

12 Design Specification and Characteristics Pad Frame Fig:7 :Tiny frame Layout used in Design

13 G_tech Multiplier Design Implementation on Cadence Virtuoso Fig:8 :Detail layout of the chip without poly fill

14 Testing information and Pattern As the chip is basic implementation of multiplication no test logic is included but it is important to check for the functionality of the IC before using it in some module. Below is the table1.6.4.a is used for testing the chip and table b is used for fault finding for the design based on output obtained which is one method for fault finding Input A Input B Expected Output S.no Hex Binary Hex Binary Hex Binary FF F FF EF F FF EF F FB F FB F AA F F AA F E D D AAAA C B E B C AAC C B AAC B C E EA FF FF FE Table a Note: Before we input any value to the chip make sure the to check for Clock input at the given frequency range as the complete design is synchronous. Set clear pin to high for the first time and check for zero output. On initial testing if you find the output are spike in nature then increase that clock total time period.

15 Test Pattern and Fault Finding The design was fully tested on using Model Sim and Cadence for functionality but in case we need to test the chip use the following pattern. This will lead to possible defect in the chip during fabrication. Each pattern is followed with the type of block the error in the block diagram. As it is not economic to have all register for observablity and also do to pad constraints there is no test logic included. But this pattern will almost lead you to the error. Initially check for Case 1, 2, 13, 14, 15, 16 and 17. If the result matches the one given in the table the design is fully functional for use. If the chip fails then check for all cases and look for comment to check for debugging or locating the fault. Input A Input B Expected Output S.no Hex Binary Hex Binary Hex Binary This pattern will check for one of the corner case of the design and will let to initial problem with the input or output. If result is non-zero then check for the input A, B, Clear pin. If the result is non zero there is defect in the design. 2 FF This pattern will check for re checking if any possible defect in the design of case 1 fails. 3 F FF EF This pattern will check for the functionality of the design for the Step1 of the algorithm. If the result don t conclude that the Step1 processing is incorrect. If Y[1:0] bits are fault then there is problem with accw of Step1. If Y[3:2] bits are faulty then there is problem with accx in the Step1 If Y[15:14] bits are faulty then accz may be faulty but if other bit are faulty then there can be problem with any of the register in step1. Go to next case to find the exact error. 4 0F FF EF This pattern will check for the functionality of the design for the Step1 of the algorithm. If the result don t conclude that the Step1 processing is incorrect. If Y[1:0] bits are fault then there is problem with accw of Step1. If Y[13:12] bits are faulty then there is problem with accy in the Step1 If Y[15:14] bits are faulty then accz may be faulty but if other bit are faulty then there can be problem with any of the register in step1. Go to next case to find the exact error. 5 F FB This pattern will check for the functionality of the design for the Step1 of the algorithm. If the result don t conclude that the Step1 processing is incorrect. If Y[1:0] bits are fault then there is problem with accw of Step1. If Y[3:2] bits are faulty then there is problem with accx in the Step1 If Y[5:4] bits are faulty then there is problem with accx in the Step1 or computation stage 2,3 If case 3,4,5 fails for Y[13:12] then there is possible defect in step 2,3 of the design else If Y[15:14] bits are faulty then accz may be faulty but if other bit are faulty then there

16 can be problem with any of the register in step1. Go to next case to find the exact error. 6 0F FB This pattern will check for the functionality of the design for the Step1 of the algorithm. If the result don t conclude that the Step1 processing is incorrect. If Y[3:9] bits are fault then there is problem with accw of Step2,3 or step4. If this bits error are not encountered before then there is a problem in stage 4 for carry genertation. If Y[10:15] bits are faulty then there is problem with Step2, 3 if these bits are no error before. 7 F AA F This pattern will check for the functionality of the design for the Step1 of the algorithm. If the result don t conclude that the Step1 processing is incorrect. If Y[1:0] bits are fault then there is problem with accw of Step1. If Y[3:2] bits are faulty then there is problem with accx in the Step1 If Y[5:4] bits are faulty then there is problem with accx in the Step1 or computation stage 2,3 If case 3,4,5 fails for Y[13:12] then there is possible defect in step 2,3 of the design else If Y[15:14] bits are faulty then accz may be faulty but if other bit are faulty then there can be problem with any of the register in step1. Go to next case to find the exact error. 8 0F AA F This pattern will check for the functionality of the design for the Step1 of the algorithm. If the result don t conclude that the Step1 processing is incorrect. If Y[3:9] bits are fault then there is problem with accw of Step2,3 or step4. If this bits error are not encountered before then there is a problem in stage 4 for carry genertation. If Y[10:15] bits are faulty then there is problem with Step2, 3 if these bits are no error before. N1:If case 5-8 is satisfied the you the toggle coverage for stage 1-3 is 100 % E This test pattern are additional test pattern to ensure that the stage 1 and its corresponding stages can compute the result based on the combination of input thus testing the input multiplexer of stage 1 and also reflects the stage 2,3,4 register and computation of these stages for its complete functionality This test pattern are additional test pattern to ensure that the stage 1 and its corresponding stages can compute the result based on the combination of input thus testing the input multiplexer of stage 1 and also reflects the stage 2,3,4 register and computation of these stages for its complete functionality. N2: If N2 is satisfied and case 9-10 pass then we can conclude that the toggle coverage is 100% This test pattern are additional test pattern to ensure that the stage 1 and its corresponding stages can compute the result based on the combination of input thus testing the input multiplexer of stage 1 and also reflects the stage 2,3,4 register and computation of these stages for its complete functionality.

17 12 D D AAAA This test pattern are additional test pattern to ensure that the stage 1 and its corresponding stages can compute the result based on the combination of input thus testing the input multiplexer of stage 1 and also reflects the stage 2,3,4 register and computation of these stages for its complete functionality. 13 C B E This test pattern are additional test pattern to ensure that the stage 1 and its corresponding stages can compute the result based on the combination of input thus testing the input multiplexer of stage 1 and also reflects the stage 2,3,4 register and computation of these stages for its complete functionality. Check for completeness all corner case of Step 1 in the design. 14 B C AAC This test pattern are additional test pattern to ensure that the stage 1 and its corresponding stages can compute the result based on the combination of input thus testing the input multiplexer of stage 1 and also reflects the stage 2,3,4 register and computation of these stages for its complete functionality. Check for completeness all corner case of Step 1 in the design. 15 6C B AAC This test pattern are additional test pattern to ensure that the stage 1 and its corresponding stages can compute the result based on the combination of input thus testing the input multiplexer of stage 1 and also reflects the stage 2,3,4 register and computation of these stages for its complete functionality. Check for completeness all corner case of Step 1 in the design. 16 1B C E This test pattern are additional test pattern to ensure that the stage 1 and its corresponding stages can compute the result based on the combination of input thus testing the input multiplexer of stage 1 and also reflects the stage 2,3,4 register and computation of these stages for its complete functionality. Check for completeness all corner case of Step 1 in the design. N3: If case is satisfied the the code coverage for this design is 100% and can be used for any input value EA This test pattern are additional test pattern to ensure that the stage 1 and its corresponding stages can compute the result based on the combination of input thus testing the input multiplexer of stage 1 and also reflects the stage 2,3,4 register and computation of these stages for its complete functionality. Check for completeness all corner case of Step 1 in the design. 18 FF FF FE This test pattern are additional test pattern to ensure that the stage 1 and its corresponding stages can compute the result based on the combination of input thus testing the input multiplexer of stage 1 and also reflects the stage 2,3,4 register and computation of these stages for its complete functionality.check for completeness all corner case of Step 1 in the design. Check for the worst case computation for user. N4: There is no worst case for the design except B in put for case considered to be the worst case tests for the design. Table a

1.6.7. Simulation Results 1.6.7.1. Using

18 Simulation Results Using Model-Sim Multiplication for 0F * 0F = 00E1

19 Multiplication for F0 * 0F = 0E10 Multiplication for FF * 00 = 0000

20 Multiplication for FF * FF = FE Using Cadence- Virtuoso

22 The spikes that are visible for zero logic output is nothing but the due to the varying transition time and clock skew.

23 1.7. Design Specification and Fabrication details AMI Semiconductor Layer Map C5 This is the layer map for the AMI C5F/N 0.50 micron 3 metal, 2 poly (non-silicided) la rules (AMI_C5F/N), and only for those AMI vendor design rules. For designs that are out using other design rules (or technology-codes), use the standard layer mapping conventions of that design rule set. For submissions in GDS format, the datatype is " (zero) unless specified in the map below. Layer GDS CIF Notes N_WELL 1 A01 ACTIVE 2 A02 N_CHANNEL_FLD 3 A03 Derived from N_WELL when N_CHANNEL_FLD is completely absent from layout. See Note #1 POLY 4 A04 N_PLUS_BLOCK 5 A05 A copy of the drawn P_PLUS_SELECT is used when N_PLUS_BLOCK is completely absent from layout. See Note #1 AMI calls this layer N_PLUS_SELECT and further requires that it be a copy of P_PLUS_SELECT. It is functionally an N_PLUS_BLOCK layer; the drawn regions will not receive the n+ implant. P_PLUS_SELECT 6 A06 CONTACT 8 A08 METAL1 9 A09 VIA1 10 A10 METAL2 11 A11 VIA2 12 A12 METAL3 13 A13 CAP_POLY (POLY2) 26 A26 Optional HRP (HIGH RESISTANCE) 27 A27 THICK_GATE 28 A28 C5F layer N_MINUS_IMPLANT (Npblk) P_MINUS_IMPLANT (Ppblk) 36 A36 C5F layer 37 A37 C5F layer GLASS 14 A14 Note #1: If this layer is present anywhere in the submitted design or anywhere in the

24 design after instantiation, then MOSIS will not derive it. If this layer is not in the submitted design or anywhere in the design after instantiation, then MOSIS will derive that layer from the listed layers. MOSIS does not create a layer partially from a layer drawn by the customer and partially derived from other layers Reading Status Report format from MOSIS Basic Information Design Number This is unique number given for each design by MOSIS on submission of the design. In other words it is you chip identification number. Date Submitted Shows the date when the design was submitted to MOSIS with time stamping Project Status Shows the current status of you chip in fabrication at MOSIS Account Name It is unique college/ individual/ Commercial vendors identification number under whom you send you chip to fabrication i.e its replicates the details of account owner who is registered with MOSIS to send chip for fabrication. Run Date Requested Date when the chip will be sent for fabrication. Usually the date is on the website for each technology Area Reflects the total area of the chip fabricated Checksum On submission o design to MOSIS, MOSIS quickly runs few checksum code to check for any problem in design or layout Design Details Size in X Dimension of the X-co-ordinate of chip Size in Y Dimension of the Y-co-ordinate of chip Wafer Technology Specifies the wafer technology and process detail Fabrication Restricted to Specified on based on what technology the chip will be fabricated Layout Format Format in which design was submitted to MOSIS Top Cell Name Specifies top cell name of you Design Fill MOSIS

25 Bonding Pad Count (Customer) Number of pins in chip user designed Bonding Pad Count (MOSIS) Number of pins MOSIS will package and provide to you Maximum Die Size Specifies maximum die area of the design Layers (Density) Shows details of all the layers used on your design Project Errors Error Shows error on running initial checksum Project Warnings Warning Shows error on running initial checksum Warning Description of error or Warning

26 1.8. Future planning and advancement The design can be easily extended for signed multiplication also this design can be extended to produce much faster result by using pipelining technique which could be extension of this project. Also by mapping the current design to ff.db (Fast fast library cell) the design performance can be further enhanced. Also test logic could be added to the design to have better controllability and observblity.

High speed DCT design using Vedic mathematics N.J.R. Muniraj 1 and N.Senathipathi 2

High speed DCT design using Vedic mathematics N.J.R. Muniraj 1 and N.Senathipathi 2 464 N.J.R.Muniraj/ Elixir Adv. Engg. Info. 9 (0) 464-468 Available online at www.elixirpublishers.com (Elixir International Journal) Advanced Engineering Informatics Elixir Adv. Engg. Info. 9 (0) 464-468