COMPUTER ORGANIZATION AND DESIGN. ARM Edition. The Hardware/Software Interface. Chapter 2. Instructions: Language of the Computer

Transcription

1 COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface ARM Editio Chapter 2 Istructios: Laguage of the Computer

2 Istructio Set The repertoire of istructios of a computer Differet computers have differet istructio sets But with may aspects i commo Early computers had very simple istructio sets Simplified implemetatio May moder computers also have simple istructio sets 2.1 Itroductio Chapter 2 Istructios: Laguage of the Computer 2

3 The ARMv8 Istructio Set A subset, called LEGv8, used as the example throughout the book Commercialized by ARM Holdigs ( Large share of embedded core market Applicatios i cosumer electroics, etwork/storage equipmet, cameras, priters, Typical of may moder ISAs See ARM Referece Data tear-out card Chapter 2 Istructios: Laguage of the Computer 3

4 Arithmetic Operatios Add ad subtract, three operads Two sources ad oe destiatio ADD a, b, c // a gets b + c All arithmetic operatios have this form Desig Priciple 1: Simplicity favours regularity Regularity makes implemetatio simpler 2.2 Operatios of the Computer Hardware Simplicity eables higher performace at lower cost Chapter 2 Istructios: Laguage of the Computer 4

5 Arithmetic Example C code: f = (g + h) - (i + j); Compiled LEGv8 code: ADD t0, g, h // temp t0 = g + h ADD t1, i, j // temp t1 = i + j SUB f, t0, t1 // f = t0 - t1 Chapter 2 Istructios: Laguage of the Computer 5

6 Register Operads Arithmetic istructios use register operads LEGv8 has a bit register file Use for frequetly accessed data 64-bit data is called a doubleword 31 x 64-bit geeral purpose registers X0 to X30 32-bit data called a word 31 x 32-bit geeral purpose sub-registers W0 to W Operads of the Computer Hardware Desig Priciple 2: Smaller is faster c.f. mai memory: millios of locatios Chapter 2 Istructios: Laguage of the Computer 6

7 LEGv8 Registers X0 X7: procedure argumets/results X8: idirect result locatio register X9 X15: temporaries X16 X17 (IP0 IP1): may be used by liker as a scratch register, other times as temporary register X18: platform register for platform idepedet code; otherwise a temporary register X19 X27: saved X28 (SP): stack poiter X29 (FP): frame poiter X30 (LR): lik register (retur address) XZR (register 31): the costat value 0 Chapter 2 Istructios: Laguage of the Computer 7

8 Register Operad Example C code: f = (g + h) - (i + j); f,, j i X19, X20,, X23 Compiled LEGv8 code: ADD X9, X20, X21 ADD X10, X22, X23 SUB X19, X9, X10 Chapter 2 Istructios: Laguage of the Computer 8

9 Memory Operads Mai memory used for composite data Arrays, structures, dyamic data To apply arithmetic operatios Load values from memory ito registers Store result from register to memory Memory is byte addressed Each address idetifies a 8-bit byte LEGv8 does ot require words to be aliged i memory, except for istructios ad the stack Chapter 2 Istructios: Laguage of the Computer 9

10 Memory Operad Example C code: A[12] = h + A[8]; h i X21, base address of A i X22 Compiled LEGv8 code: Idex 8 requires offset of 64 LDUR ADD STUR X9,[X22,#64] // U for uscaled X9,X21,X9 X9,[X22,#96] Chapter 2 Istructios: Laguage of the Computer 10

11 Registers vs. Memory Registers are faster to access tha memory Operatig o memory data requires loads ad stores More istructios to be executed Compiler must use registers for variables as much as possible Oly spill to memory for less frequetly used variables Register optimizatio is importat! Chapter 2 Istructios: Laguage of the Computer 11

12 Immediate Operads Costat data specified i a istructio ADDI X22, X22, #4 Desig Priciple 3: Make the commo case fast Small costats are commo Immediate operad avoids a load istructio Chapter 2 Istructios: Laguage of the Computer 12

13 Usiged Biary Itegers Give a -bit umber x = x x-22 +! + x12 x02 Rage: 0 to +2 1 Example 2.4 Siged ad Usiged Numbers = = = Usig 32 bits 0 to +4,294,967,295 Chapter 2 Istructios: Laguage of the Computer 13

14 2s-Complemet Siged Itegers Give a -bit umber x = -x x-22 +! + x12 x02 Rage: 2 1 to Example = = 2,147,483, ,147,483,644 = 4 10 Usig 32 bits 2,147,483,648 to +2,147,483,647 Chapter 2 Istructios: Laguage of the Computer 14

15 2s-Complemet Siged Itegers Bit 31 is sig bit 1 for egative umbers 0 for o-egative umbers ( 2 1 ) ca t be represeted No-egative umbers have the same usiged ad 2s-complemet represetatio Some specific umbers 0: : Most-egative: Most-positive: Chapter 2 Istructios: Laguage of the Computer 15

16 Siged Negatio Complemet ad add 1 Complemet meas 1 0, 0 1 x + x = = -1 x + 1= -x Example: egate = two 2 = two + 1 = two Chapter 2 Istructios: Laguage of the Computer 16

17 Sig Extesio Represetig a umber usig more bits Preserve the umeric value Replicate the sig bit to the left c.f. usiged values: exted with 0s Examples: 8-bit to 16-bit +2: => : => I LEGv8 istructio set LDURSB: sig-exted loaded byte LDURB: zero-exted loaded byte Chapter 2 Istructios: Laguage of the Computer 17

18 Represetig Istructios Istructios are ecoded i biary Called machie code LEGv8 istructios Ecoded as 32-bit istructio words Small umber of formats ecodig operatio code (opcode), register umbers, Regularity! 2.5 Represetig Istructios i the Computer Chapter 2 Istructios: Laguage of the Computer 18

19 Hexadecimal Base 16 Compact represetatio of bit strigs 4 bits per hex digit c d a 1010 e b 1011 f 1111 Example: eca Chapter 2 Istructios: Laguage of the Computer 19

20 LEGv8 R-format Istructios opcode Rm shamt R Rd 11 bits 5 bits 6 bits 5 bits 5 bits Istructio fields opcode: operatio code Rm: the secod register source operad shamt: shift amout (00000 for ow) R: the first register source operad Rd: the register destiatio Chapter 2 Istructios: Laguage of the Computer 20

21 R-format Example opcode Rm shamt R Rd 11 bits 5 bits 6 bits 5 bits 5 bits ADD X9,X20,X te 21 te 0 te 20 te 9 te two two two two two two = 8B Chapter 2 Istructios: Laguage of the Computer 21

22 LEGv8 D-format Istructios opcode address op2 R Rt 11 bits 9 bits 2 bits 5 bits 5 bits Load/store istructios R: base register address: costat offset from cotets of base register (+/- 32 doublewords) Rt: destiatio (load) or source (store) register umber Desig Priciple 3: Good desig demads good compromises Differet formats complicate decodig, but allow 32-bit istructios uiformly Keep formats as similar as possible Chapter 2 Istructios: Laguage of the Computer 22

23 LEGv8 I-format Istructios opcode immediate R Rd 10 bits 12 bits 5 bits 5 bits Immediate istructios R: source register Rd: destiatio register Immediate field is zero-exteded Chapter 2 Istructios: Laguage of the Computer 23

24 Stored Program Computers The BIG Picture Istructios represeted i biary, just like data Istructios ad data stored i memory Programs ca operate o programs e.g., compilers, likers, Biary compatibility allows compiled programs to work o differet computers Stadardized ISAs Chapter 2 Istructios: Laguage of the Computer 24

25 Logical Operatios Istructios for bitwise maipulatio Operatio C/Java Java (usiged) LEGv8 Shift left << <<< LSL Shift right >> >>> LSR Bit-by-bit AND & & AND, ANDI Bit-by-bit OR OR, ORI Bit-by-bit NOT ~ ~ EOR, EORI Useful for extractig ad isertig groups of bits i a word 2.6 Logical Operatios Chapter 2 Istructios: Laguage of the Computer 25

26 Shift Operatios opcode Rm shamt R Rd 11 bits 5 bits 6 bits 5 bits 5 bits shamt: how may positios to shift Shift left logical Shift left ad fill with 0 bits LSL by i bits multiplies by 2 i Shift right logical Shift right ad fill with 0 bits LSR by i bits divides by 2 i (usiged oly) Chapter 2 Istructios: Laguage of the Computer 26

27 AND Operatios Useful to mask bits i a word Select some bits, clear others to 0 AND X9,X10,X11 X10 X11 X Chapter 2 Istructios: Laguage of the Computer 27

28 OR Operatios Useful to iclude bits i a word Set some bits to 1, leave others uchaged OR X9,X10,X11 X10 X11 X Chapter 2 Istructios: Laguage of the Computer 28

29 EOR Operatios Differecig operatio Set some bits to 1, leave others uchaged EOR X9,X10,X12 // NOT operatio X10 X12 X Chapter 2 Istructios: Laguage of the Computer 29

30 Coditioal Operatios Brach to a labeled istructio if a coditio is true Otherwise, cotiue sequetially CBZ register, L1 if (register == 0) brach to istructio labeled L1; CBNZ register, L1 if (register!= 0) brach to istructio labeled L1; 2.7 Istructios for Makig Decisios B L1 brach ucoditioally to istructio labeled L1; Chapter 2 Istructios: Laguage of the Computer 30

31 Compilig If Statemets C code: if (i==j) f = g+h; else f = g-h; f, g, i X19, X20, Compiled LEGv8 code: SUB X9,X22,X23 CBNZ X9,Else ADD X19,X20,X21 B Exit Else: SUB X19,X20,x21 Exit: Assembler calculates addresses Chapter 2 Istructios: Laguage of the Computer 31

32 Compilig Loop Statemets C code: while (save[i] == k) i += 1; i i X22, k i X24, address of save i x25 Compiled LEGv8 code: Loop: LSL ADD LDUR SUB CBNZ ADDI B Exit: X10, X22,#3 X10, X10, X25 X9,[X10,#0] X11, X9, X24 X11,Exit X22, X22,#1 Loop Chapter 2 Istructios: Laguage of the Computer 32

33 Basic Blocks A basic block is a sequece of istructios with No embedded braches (except at ed) No brach targets (except at begiig) A compiler idetifies basic blocks for optimizatio A advaced processor ca accelerate executio of basic blocks Chapter 2 Istructios: Laguage of the Computer 33

34 More Coditioal Operatios Coditio codes, set from arithmetic istructio with S- suffix (ADDS, ADDIS, ANDS, ANDIS, SUBS, SUBIS) egative (N): result had 1 i MSB zero (Z): result was 0 overlow (V): result overflowed carry (C): result had carryout from MSB Use subtract to set flags, the coditioally brach: B.EQ B.NE B.LT (less tha, siged), B.LO (less tha, usiged) B.LE (less tha or equal, siged), B.LS (less tha or equal, usiged) B.GT (greater tha, siged), B.HI (greater tha, usiged) B.GE (greater tha or equal, siged), B.HS (greater tha or equal, usiged) Chapter 2 Istructios: Laguage of the Computer 34

35 Coditioal Example if (a > b) a += 1; a i X22, b i X23 Exit: SUBS X9,X22,X23 // use subtract to make compariso B.LTE Exit // coditioal brach ADDI X22,X22,#1 Chapter 2 Istructios: Laguage of the Computer 35

36 Siged vs. Usiged Siged compariso Usiged compariso Example X22 = X23 = X22 < X23 # siged 1 < +1 X22 > X23 # usiged +4,294,967,295 > +1 Chapter 2 Istructios: Laguage of the Computer 36

37 Procedure Callig Steps required 1. Place parameters i registers X0 to X7 2. Trasfer cotrol to procedure 3. Acquire storage for procedure 4. Perform procedure s operatios 5. Place result i register for caller 6. Retur to place of call (address i X30) 2.8 Supportig Procedures i Computer Hardware Chapter 2 Istructios: Laguage of the Computer 37

38 Procedure Call Istructios Procedure call: jump ad lik BL ProcedureLabel Address of followig istructio put i X30 Jumps to target address Procedure retur: jump register BR LR Copies LR to program couter Ca also be used for computed jumps e.g., for case/switch statemets Chapter 2 Istructios: Laguage of the Computer 38

39 Leaf Procedure Example C code: log log it leaf_example (log log it g, log log it h, log log it i, log log it j) { log log it f; f = (g + h) - (i + j); retur f; } Argumets g,, j i X0,, X3 f i X19 (hece, eed to save X19 o stack) Chapter 2 Istructios: Laguage of the Computer 39

40 Leaf Procedure Example LEGv8 code: leaf_example: SUBI SP,SP,#24 STUR X10,[SP,#16] STUR X9,[SP,#8] STUR X19,[SP,#0] ADD X9,X0,X1 ADD X10,X2,X3 SUB X19,X9,X10 ADD X0,X19,XZR LDUR X10,[SP,#16] LDUR X9,[SP,#8] LDUR X19,[SP,#0] ADDI SP,SP,#24 BR LR Save X10, X9, X19 o stack X9 = g + h X10 = i + j f = X9 X10 copy f to retur register Restore X10, X9, X19 from stack Retur to caller Chapter 2 Istructios: Laguage of the Computer 40

41 Notes X9 X17 temporary registers that are ot preserved by the callee (called procedure) o a procedure call X19 X28: saved registers that must be preserved o a procedure call if used, the callee saves ad restores them Chapter 2 Istructios: Laguage of the Computer 41

42 Local Data o the Stack Chapter 2 Istructios: Laguage of the Computer 42

43 Register Usage i Subrouties X9 to X17: temporary registers Not preserved by the callee X19 to X28: saved registers If used, the callee saves ad restores them Chapter 2 Istructios: Laguage of the Computer 43

44 No-Leaf Procedures Procedures that call other procedures For ested call, caller eeds to save o the stack: Its retur address Ay argumets ad temporaries eeded after the call Restore from the stack after the call Chapter 2 Istructios: Laguage of the Computer 44

45 No-Leaf Procedure Example C code: it fact (it ) { if ( < 1) retur 1; else retur * fact( - 1); } Argumet i X0 Result i X1 Chapter 2 Istructios: Laguage of the Computer 45

46 No-Leaf Procedure Example LEGv8 code: fact: SUBI SP,SP,#16 STUR LR,[SP,#8] STUR X0,[SP,#0] SUBIS XZR,X0,#1 B.GE L1 ADDI X1,XZR,#1 ADDI SP,SP,#16 BR LR L1: SUBI X0,X0,#1 BL fact LDUR X0,[SP,#0] LDUR LR,[SP,#8] ADDI SP,SP,#16 MUL X1,X0,X1 BR LR Save retur address ad o stack compare ad 1 if >= 1, go to L1 Else, set retur value to 1 Pop stack, do t bother restorig values Retur = - 1 call fact(-1) Restore caller s Restore caller s retur address Pop stack retur * fact(-1) retur Chapter 2 Istructios: Laguage of the Computer 46

47 Memory Layout Text: program code Static data: global variables e.g., static variables i C, costat arrays ad strigs Dyamic data: heap E.g., malloc i C, ew i Java Stack: automatic storage Chapter 2 Istructios: Laguage of the Computer 47

48 Character Data Byte-ecoded character sets ASCII: 128 characters 95 graphic, 33 cotrol Lati-1: 256 characters ASCII, +96 more graphic characters Uicode: 32-bit character set 2.9 Commuicatig with People Used i Java, C++ wide characters, Most of the world s alphabets, plus symbols UTF-8, UTF-16: variable-legth ecodigs Chapter 2 Istructios: Laguage of the Computer 48

49 Byte/Halfword Operatios LEGv8 byte/halfword load/store Load byte: LDURB Rt, [R, offset] Sig exted to 32 bits i rt Store byte: STURB Rt, [R, offset] Store just rightmost byte Load halfword: LDURH Rt, [R, offset] Sig exted to 32 bits i rt Store halfword: STURH Rt, [R, offset] Store just rightmost halfword Chapter 2 Istructios: Laguage of the Computer 49

50 Strig Copy Example C code: Null-termiated strig void strcpy (char x[], char y[]) { size_t i; i = 0; while ((x[i]=y[i])!='\0') i += 1; } Chapter 2 Istructios: Laguage of the Computer 50

51 Strig Copy Example LEGv8 code: strcpy: SUBI SP,SP,8 // push X19 STUR X19,[SP,#0] ADD X19,XZR,XZR // i=0 L1: ADD X10,X19,X1 // X10 = addr of y[i] LDURB X11,[X10,#0] // X11 = y[i] ADD X12,X19,X0 // X12 = addr of x[i] STURB X11,[X12,#0] // x[i] = y[i] CBZ X11,L2 // if y[i] == 0 the exit ADDI X19,X19,#1 // i = i + 1 B L1 // ext iteratio of loop L2: LDUR X19,[SP,#0] // restore saved $s0 ADDI SP,SP,8 // pop 1 item from stack BR LR // ad retur Chapter 2 Istructios: Laguage of the Computer 51

52 32-bit Costats Most costats are small 12-bit immediate is sufficiet For the occasioal 32-bit costat MOVZ: move wide with zeros MOVK: move with with keep Use with flexible secod operad (shift) MOVZ X9,255,LSL MOVK X9,255,LSL LEGv8 Addressig for 32-Bit Immediates ad Addresses Chapter 2 Istructios: Laguage of the Computer 52

53 Brach Addressig B-type B 1000 // go to locatio te CB-type te 6 bits 26 bits CBNZ X19, Exit // go to Exit if X19!= Exit 8 bits 19 bits 19 5 bits Both addresses are PC-relative Address = PC + offset (from istructio) Chapter 2 Istructios: Laguage of the Computer 53

54 LEGv8 Addressig Summary Chapter 2 Istructios: Laguage of the Computer 54

55 LEGv8 Ecodig Summary Chapter 2 Istructios: Laguage of the Computer 55

56 Sychroizatio Two processors sharig a area of memory P1 writes, the P2 reads Data race if P1 ad P2 do t sychroize Result depeds of order of accesses Hardware support required Atomic read/write memory operatio No other access to the locatio allowed betwee the read ad write Could be a sigle istructio E.g., atomic swap of register memory Or a atomic pair of istructios 2.11 Parallelism ad Istructios: Sychroizatio Chapter 2 Istructios: Laguage of the Computer 56

57 Sychroizatio i LEGv8 Load exclusive register: LDXR Store exclusive register: STXR To use: Execute LDXR the STXR with same address If there is a iterveig chage to the address, store fails (commuicated with additioal output register) Oly use register istructio i betwee Chapter 2 Istructios: Laguage of the Computer 57

58 Sychroizatio i LEGv8 Example 1: atomic swap (to test/set lock variable) agai: LDXR X10,[X20,#0] STXR X23,X9,[X20] // X9 = status CBNZ X9, agai ADD X23,XZR,X10 // X23 = loaded value Example 2: lock ADDI X11,XZR,#1 // copy locked value agai: LDXR X10,[X20,#0] // read lock CBNZ X10, agai // check if it is 0 yet STXR X11, X9, [X20] // attempt to store BNEZ X9,agai // brach if fails Ulock: STUR XZR, [X20,#0] // free lock Chapter 2 Istructios: Laguage of the Computer 58

59 Traslatio ad Startup May compilers produce object modules directly Static likig 2.12 Traslatig ad Startig a Program Chapter 2 Istructios: Laguage of the Computer 59

60 Producig a Object Module Assembler (or compiler) traslates program ito machie istructios Provides iformatio for buildig a complete program from the pieces Header: described cotets of object module Text segmet: traslated istructios Static data segmet: data allocated for the life of the program Relocatio ifo: for cotets that deped o absolute locatio of loaded program Symbol table: global defiitios ad exteral refs Debug ifo: for associatig with source code Chapter 2 Istructios: Laguage of the Computer 60

61 Likig Object Modules Produces a executable image 1. Merges segmets 2. Resolve labels (determie their addresses) 3. Patch locatio-depedet ad exteral refs Could leave locatio depedecies for fixig by a relocatig loader But with virtual memory, o eed to do this Program ca be loaded ito absolute locatio i virtual memory space Chapter 2 Istructios: Laguage of the Computer 61

62 Loadig a Program Load from image file o disk ito memory 1. Read header to determie segmet sizes 2. Create virtual address space 3. Copy text ad iitialized data ito memory Or set page table etries so they ca be faulted i 4. Set up argumets o stack 5. Iitialize registers (icludig SP, FP) 6. Jump to startup routie Copies argumets to X0, ad calls mai Whe mai returs, do exit syscall Chapter 2 Istructios: Laguage of the Computer 62

63 Dyamic Likig Oly lik/load library procedure whe it is called Requires procedure code to be relocatable Avoids image bloat caused by static likig of all (trasitively) refereced libraries Automatically picks up ew library versios Chapter 2 Istructios: Laguage of the Computer 63

64 Lazy Likage Idirectio table Stub: Loads routie ID, Jump to liker/loader Liker/loader code Dyamically mapped code Chapter 2 Istructios: Laguage of the Computer 64

65 Startig Java Applicatios Simple portable istructio set for the JVM Compiles bytecodes of hot methods ito ative code for host machie Iterprets bytecodes Chapter 2 Istructios: Laguage of the Computer 65

66 C Sort Example Illustrates use of assembly istructios for a C bubble sort fuctio Swap procedure (leaf) void swap(log log it v[], log log it k) { log log it temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } v i X0, k i X1, temp i X A C Sort Example to Put It All Together Chapter 2 Istructios: Laguage of the Computer 66

67 The Procedure Swap swap: LSL X10,X1,#3 // X10 = k * 8 ADD X10,X0,X10 // X10 = address of v[k] LDUR X9,[X10,#0] // X9 = v[k] LDUR X11,[X10,#8] // X11 = v[k+1] STUR X11,[X10,#0] // v[k] = X11 (v[k+1]) STUR X9,[X10,#8] // v[k+1] = X9 (v[k]) BR LR // retur to callig routie Chapter 2 Istructios: Laguage of the Computer 67

68 The Sort Procedure i C No-leaf (calls swap) void sort (log log it v[], size_t ) { size_t i, j; for (i = 0; i < ; i += 1) { for (j = i 1; j >= 0 && v[j] > v[j + 1]; j -= 1) { swap(v,j); } } } v i X0, i X1, i i X19, j i X20 Chapter 2 Istructios: Laguage of the Computer 68

69 The Outer Loop Skeleto of outer loop: for (i = 0; i <; i += 1) { MOV X19,XZR // i = 0 for1tst: CMP X19, X1 // compare X19 to X1 (i to ) B.GE exit1 // go to exit1 if X19 X1 (i ) (body of outer for-loop) ADDI X19,X19,#1 // i += 1 B for1tst // brach to test of outer loop exit1: Chapter 2 Istructios: Laguage of the Computer 69

70 The Ier Loop Skeleto of ier loop: for (j = i 1; j >= 0 && v[j] > v[j + 1]; j = 1) { SUBI X20, X19, #1 // j = i - 1 for2tst: CMP X20,XZR // compare X20 to 0 (j to 0) B.LT exit2 // go to exit2 if X20 < 0 (j < 0) LSL X10, X20, #3 // reg X10 = j * 8 ADD X11, X0, X10 // reg X11 = v + (j * 8) LDUR X12, [X11,#0] // reg X12 = v[j] LDUR X13, [X11,#8] // reg X13 = v[j + 1] CMP X12, X13 // compare X12 to X13 B.LE exit2 // go to exit2 if X12 X13 MOV X0, X21 // first swap parameter is v MOV X1, X20 // secod swap parameter is j BL swap // call swap SUBI X20, X20, #1 // j = 1 B for2tst // brach to test of ier loop exit2: Chapter 2 Istructios: Laguage of the Computer 70

71 Preservig Registers Preserve saved registers: SUBI SP,SP,#40 STUR LR,[SP,#32] STUR X22,[SP,#24] STUR X21,[SP,#16] STUR X20,[SP,#8] STUR X19,[SP,#0] MOV X21, X0 MOV X22, X1 Restore saved registers: // make room o stack for 5 regs // save LR o stack // save X22 o stack // save X21 o stack // save X20 o stack // save X19 o stack // copy parameter X0 ito X21 // copy parameter X1 ito X22 exit1: LDUR X19, [SP,#0] // restore X19 from stack LDUR X20, [SP,#8] // restore X20 from stack LDUR X21,[SP,#16] // restore X21 from stack LDUR X22,[SP,#24] // restore X22 from stack LDUR X30,[SP,#32] // restore LR from stack SUBI SP,SP,#40 // restore stack poiter Chapter 2 Istructios: Laguage of the Computer 71

72 Effect of Compiler Optimizatio Compiled with gcc for Petium 4 uder Liux 3 Relative Performace Istructio cout oe O1 O2 O3 0 oe O1 O2 O Clock Cycles oe O1 O2 O CPI oe O1 O2 O3 Chapter 2 Istructios: Laguage of the Computer 72

73 Effect of Laguage ad Algorithm 3 Bubblesort Relative Performace C/oe C/O1 C/O2 C/O3 Java/it Java/JIT 2.5 Quicksort Relative Performace C/oe C/O1 C/O2 C/O3 Java/it Java/JIT 3000 Quicksort vs. Bubblesort Speedup C/oe C/O1 C/O2 C/O3 Java/it Java/JIT Chapter 2 Istructios: Laguage of the Computer 73

74 Lessos Leart Istructio cout ad CPI are ot good performace idicators i isolatio Compiler optimizatios are sesitive to the algorithm Java/JIT compiled code is sigificatly faster tha JVM iterpreted Comparable to optimized C i some cases Nothig ca fix a dumb algorithm! Chapter 2 Istructios: Laguage of the Computer 74

75 Arrays vs. Poiters Array idexig ivolves Multiplyig idex by elemet size Addig to array base address Poiters correspod directly to memory addresses Ca avoid idexig complexity 2.14 Arrays versus Poiters Chapter 2 Istructios: Laguage of the Computer 75

76 Example: Clearig a Array clear1(it array[], it size) { it i; for (i = 0; i < size; i += 1) array[i] = 0; } MOV X9,XZR // i = 0 loop1: LSL X10,X9,#3 // X10 = i * 8 ADD X11,X0,X10 // X11 = address // of array[i] STUR XZR,[X11,#0] // array[i] = 0 ADDI X9,X9,#1 // i = i + 1 CMP X9,X1 // compare i to // size B.LT loop1 // if (i < size) // go to loop1 clear2(it *array, it size) { it *p; for (p = &array[0]; p < &array[size]; p = p + 1) *p = 0; } MOV X9,X0 // p = address of // array[0] LSL X10,X1,#3 // X10 = size * 8 ADD X11,X0,X10 // X11 = address // of array[size] loop2: STUR XZR,0[X9,#0] // Memory[p] = 0 ADDI X9,X9,#8 // p = p + 8 CMP X9,X11 // compare p to < // &array[size] B.LT loop2 // if (p < // &array[size]) // go to loop2 Chapter 2 Istructios: Laguage of the Computer 76

77 Compariso of Array vs. Ptr Multiply stregth reduced to shift Array versio requires shift to be iside loop Part of idex calculatio for icremeted i c.f. icremetig poiter Compiler ca achieve same effect as maual use of poiters Iductio variable elimiatio Better to make program clearer ad safer Chapter 2 Istructios: Laguage of the Computer 77

78 ARM & MIPS Similarities ARM: the most popular embedded core Similar basic set of istructios to MIPS ARM MIPS Date aouced Istructio size 32 bits 32 bits Address space 32-bit flat 32-bit flat Data aligmet Aliged Aliged Data addressig modes 9 3 Registers bit bit Iput/output Memory mapped Memory mapped 2.16 Real Stuff: ARM Istructios Chapter 2 Istructios: Laguage of the Computer 78

79 Istructio Ecodig Chapter 2 Istructios: Laguage of the Computer 79

80 The Itel x86 ISA Evolutio with backward compatibility 8080 (1974): 8-bit microprocessor Accumulator, plus 3 idex-register pairs 8086 (1978): 16-bit extesio to 8080 Complex istructio set (CISC) 8087 (1980): floatig-poit coprocessor Adds FP istructios ad register stack (1982): 24-bit addresses, MMU Segmeted memory mappig ad protectio (1985): 32-bit extesio (ow IA-32) Additioal addressig modes ad operatios Paged memory mappig as well as segmets 2.17 Real Stuff: x86 Istructios Chapter 2 Istructios: Laguage of the Computer 80

81 The Itel x86 ISA Further evolutio i486 (1989): pipelied, o-chip caches ad FPU Compatible competitors: AMD, Cyrix, Petium (1993): superscalar, 64-bit datapath Later versios added MMX (Multi-Media extesio) istructios The ifamous FDIV bug Petium Pro (1995), Petium II (1997) New microarchitecture (see Colwell, The Petium Chroicles) Petium III (1999) Added SSE (Streamig SIMD Extesios) ad associated registers Petium 4 (2001) New microarchitecture Added SSE2 istructios Chapter 2 Istructios: Laguage of the Computer 81

82 The Itel x86 ISA Ad further AMD64 (2003): exteded architecture to 64 bits EM64T Exteded Memory 64 Techology (2004) AMD64 adopted by Itel (with refiemets) Added SSE3 istructios Itel Core (2006) Added SSE4 istructios, virtual machie support AMD64 (aouced 2007): SSE5 istructios Itel declied to follow, istead Advaced Vector Extesio (aouced 2008) Loger SSE registers, more istructios If Itel did t exted with compatibility, its competitors would! Techical elegace market success Chapter 2 Istructios: Laguage of the Computer 82

83 Basic x86 Registers Chapter 2 Istructios: Laguage of the Computer 83

84 Basic x86 Addressig Modes Two operads per istructio Source/dest operad Register Register Register Memory Memory Secod source operad Register Immediate Memory Register Immediate Memory addressig modes Address i register Address = R base + displacemet Address = R base + 2 scale R idex (scale = 0, 1, 2, or 3) Address = R base + 2 scale R idex + displacemet Chapter 2 Istructios: Laguage of the Computer 84

85 x86 Istructio Ecodig Variable legth ecodig Postfix bytes specify addressig mode Prefix bytes modify operatio Operad legth, repetitio, lockig, Chapter 2 Istructios: Laguage of the Computer 85

86 Implemetig IA-32 Complex istructio set makes implemetatio difficult Hardware traslates istructios to simpler microoperatios Simple istructios: 1 1 Complex istructios: 1 may Microegie similar to RISC Market share makes this ecoomically viable Comparable performace to RISC Compilers avoid complex istructios Chapter 2 Istructios: Laguage of the Computer 86

87 Fallacies Powerful istructio Þ higher performace Fewer istructios required But complex istructios are hard to implemet May slow dow all istructios, icludig simple oes Compilers are good at makig fast code from simple istructios Use assembly code for high performace But moder compilers are better at dealig with moder processors More lies of code Þ more errors ad less productivity 2.19 Fallacies ad Pitfalls Chapter 2 Istructios: Laguage of the Computer 87

88 Fallacies Backward compatibility Þ istructio set does t chage But they do accrete more istructios x86 istructio set Chapter 2 Istructios: Laguage of the Computer 88

89 Pitfalls Sequetial words are ot at sequetial addresses Icremet by 4, ot by 1! Keepig a poiter to a automatic variable after procedure returs e.g., passig poiter back via a argumet Poiter becomes ivalid whe stack popped Chapter 2 Istructios: Laguage of the Computer 89

90 Cocludig Remarks Desig priciples 1. Simplicity favors regularity 2. Smaller is faster 3. Make the commo case fast 4. Good desig demads good compromises Layers of software/hardware Compiler, assembler, hardware LEGv8: typical of RISC ISAs c.f. x Cocludig Remarks Chapter 2 Istructios: Laguage of the Computer 90

91 Cocludig Remarks Additioal ARMv8 features: Flexible secod operad Additioal addressig modes Coditioal istructios (e.g. CSET, CINC) Chapter 2 Istructios: Laguage of the Computer 91