# All instructions have 3 operands Operand order is fixed (destination first)

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1 Instruction Set Architecture for MIPS Processors Overview Dr. Arjan Durresi Louisiana State University Baton Rouge, LA These slides are available at: Operations and Operands of the Computer Hardware Representing Instructions in Computer MIPS addressing An Introduction to Compilers IA-32 Instructions Louisiana State University 2- Instructions - 1 Louisiana State University 2- Instructions - 2 Instructions: Language of the Machine We ll be working with the MIPS instruction set architecture similar to other architectures developed since the 1980's Almost 100 million MIPS processors manufactured in 2002 used by NEC, Nintendo, Cisco, Silicon Graphics, Sony, MIPS Processor Other SPARC Hitachi SH PowerPC Motorola 68K MIPS IA-32 ARM Louisiana State University 2- Instructions - 3 Louisiana State University 2- Instructions - 4 MIPS arithmetic All instructions have 3 operands Operand order is fixed (destination first) Example: C code: a = b + c MIPS code : add a, b, c Louisiana State University 2- Instructions - 5 (we ll talk about registers in a bit) The natural number of operands for an operation like addition is three requiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple MIPS arithmetic Design Principle: Simplicity favors regularity. Of course this complicates some things... C code: a = b + c + d; MIPS code: add a, b, c add a, a, d Operands must be registers, only 32 registers provided Each register contains 32 bits Design Principle: smaller is faster. Louisiana State University 2- Instructions - 6 Why?

2 Compiling C Assignments into MIPS C code: f = (g+h) (i+j); MIPS code: add t0, g, h add t1, i, j sub f, t0, t1 Registers vs. Memory Arithmetic instructions operands must be registers, only 32 registers provided Registers are primitives used in hardware design that are visible to the programmer Compiler associates variables with registers What about programs with lots of variables Control Datapath Memory Input Output Processor I/O Louisiana State University 2- Instructions - 7 Louisiana State University 2- Instructions - 8 CPU: MIPS Registers bit general purpose registers GPRs (r0 r31); r0 has fixed value of zero. Attempt to writing into r0 is not illegal, but its value will not change; two 32-bit registers Hi & Lo, hold results of integer multiply and divide 32-bit program counter PC; MIPS Data Types MIPS operates on: 32-bit (unsigned or 2 s complement) integers, 32-bit (single precision floating point) real numbers, 64-bit (double precision floating point) real numbers; bytes and half words loaded into GPRs are either zero or sign bit expanded to fill the 32 bits; only 32-bit units can be loaded d into FPRs; 32-bit real numbers are stored in even numbered FPRs. 64-bit real numbers are stored in two consecutive FPRs, starting with even-numbered register. Floating Point Processor FPU (Coprocessor 1 CP1): bit floating point registers FPRs (f0 f31) Five control registers Louisiana State University 2- Instructions - 9 Louisiana State University 2- Instructions - 10 Memory Organization Viewed as a large, single-dimension array, with an address. A memory address is an index into the array "Byte addressing" means that the index points to a byte of memory. 0 8 bits of data 1 8 bits of data 2 8 bits of data 3 8 bits of data 4 8 bits of data 5 8 bits of data 6 8 bits of data... Memory Organization Bytes are nice, but most data items use larger "words" For MIPS, a word is 32 bits or 4 bytes bits of data 4 32 bits of data 8 32 bits of data bits of data... Registers hold 32 bits of data 2 32 bytes with byte addresses from 0 to words with byte addresses 0, 4, 8, Words are aligned Louisiana State University 2- Instructions - 11 Louisiana State University 2- Instructions - 12

4 MIPS Instructions Instructions that move data: load to register from memory, store from register to memory, move between registers in same and different coprocessors ALU integer instructions, Floating point instructions, Control-related instructions, Special control-related instructions. Instructions, like registers and words of data, are also 32 bits long Example: add \$t0, \$s1, \$s2 registers have numbers, \$t0=8, \$s1=17, \$s2=18 Instruction Format: Machine Language op rs rt rd shamt funct Can you guess what the field names stand for? All MIPS instructions are 32 bits long Louisiana State University 2- Instructions - 19 Louisiana State University 2- Instructions - 20 Machine Language Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions other format was R-type for register Example: lw \$t0, 32(\$s2) op rs rt 16 bit number MIPS Fields op rs rt rd shamt funct 6 bits op: - Basic operation of the instruction, traditionally called opcode rs: - The first register source operand rt: - The second register source operand rd: - The Register destination operand shamt: Shift amount funct: Function Design Principle: Good design demands good compromises. Louisiana State University 2- Instructions - 21 Louisiana State University 2- Instructions - 22 Stored Program Concept Stored Program Concept Instructions are bits Programs are stored in memory to be read or written just like data Processor Memory memory for data, programs, compilers, editors, etc. Fetch & Execute Cycle Instructions are fetched and put into a special register Bits in the register "control" the subsequent actions Fetch the next instruction and continue Louisiana State University 2- Instructions - 23 Louisiana State University 2- Instructions - 24

5 A[300] = h + A[300]: Example Hexadecimal lw \$t0, 1200(\$t1) #Temporary reg \$t0 gets A[300] add \$t0,\$s2,\$t0 # Temporary reg \$t0 gets h + A[300] sw \$t0,1200(\$t1) #Stores h + A[300] \$t1 has the base array for A and \$s2 corresponds to h op rs rt rd Address/ funct shamt Hexadecimal Binary Hexadecimal Binary Hexadecimal Binary Hexadecimal Binary 0 hex 0000 two 4 hex 0100 two 8 hex 1000 two c hex 1100 two 1 hex 0001 two 5 hex 0101 two 9 hex 1001 two d hex 1101 two 2 hex 0010 two 6 hex 0110 two a hex 1010 two e hex 1110 two 3 hex 0011 two 7 hex 0111 two b hex 1011 two f hex 1111 two Louisiana State University 2- Instructions - 25 Louisiana State University 2- Instructions - 26 Logical Operations Logical operation MIPS Shift = 9 ten Shift left Shift right Bit-by-bit AND Bit-by-bit OR sll srl and, andi or, ori = 144 ten Sll \$t2,\$s0,4 # reg \$t2 = reg \$s0 << 4 bits op rs rt rd shamt funct Bit-by-bit NOT nor Shifting left by i bits gives the same result as multiplying by 2i It is useful to be able to operate on bits Louisiana State University 2- Instructions - 27 Louisiana State University 2- Instructions - 28 AND, OR, NOR Control add \$t0,\$t1,\$t2 # reg \$t0 = reg \$t1 & reg \$t or \$t0,\$t1,\$t2 # reg \$t0 = reg \$t1 reg \$t nor \$t0,\$t1,\$t2 # reg \$t0 = ~(reg \$t1 reg \$t2) Decision making instructions alter the control flow, i.e., change the "next" instruction to be executed MIPS conditional branch instructions: bne \$t0, \$t1, Label beq \$t0, \$t1, Label Example: if (i==j) h = i + j; AND is called a mask NOR - NOT OR bne \$s0, \$s1, Label add \$s3, \$s0, \$s1 Label:... Louisiana State University 2- Instructions - 29 Louisiana State University 2- Instructions - 30

10 IA-32 Overview Complexity: Instructions from 1 to 17 bytes long one operand must act as both a source and destination one operand can come from memory complex addressing modes e.g., base or scaled index with 8 or 32 bit displacement Saving grace: the most frequently used instructions are not too difficult to build compilers avoid the portions of the architecture that are slow IA-32 Registers and Data Addressing Registers in the 32-bit subset that originated with Name EAX ECX EDX EBX ESP EBP ESI EDI 31 CS SS Use 0 GPR 0 GPR 1 GPR 2 GPR 3 GPR 4 GPR 5 GPR 6 GPR 7 Code segment pointer Stack segment pointer (top of stack) what the 80x86 lacks in style is made up in quantity, making it beautiful from the right perspective DS ES FS GS Data segment pointer 0 Data segment pointer 1 Data segment pointer 2 Data segment pointer 3 EIP EFLAGS Instruction pointer (PC) Condition codes Louisiana State University 2- Instructions - 55 Louisiana State University 2- Instructions - 56 IA-32 Register Restrictions Registers are not general purpose note the restrictions below IA-32 Typical Instructions Four major types of integer instructions: Data movement including move, push, pop Arithmetic and logical (destination register or memory) Control flow (use of condition codes / flags ) String instructions, including string move and string compare Louisiana State University 2- Instructions - 57 Louisiana State University 2- Instructions - 58 IA-32 instruction Formats Typical formats: (notice the different a. JE EIP + displacement lengths) JE b. CALL CALL Condition Displacement 8 32 c. MOV EBX, [EDI + 45] MOV d. PUSH ESI PUSH e. ADD EAX, #6765 ADD Offset f. TEST EDX, # TEST d 5 3 Reg w Reg w w r/m Postbyte Postbyte Displacement Immediate Immediate Summary Instruction complexity is only one variable lower instruction count vs. higher CPI / lower clock rate Design Principles: simplicity it favors regularity smaller is faster good design demands compromise make the common case fast Instruction set architecture a very important abstraction indeed! Louisiana State University 2- Instructions - 59 Louisiana State University 2- Instructions - 60

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