Description of Single Cycle Computer (SCC)

Transcription

1 Descriptio of Sigle Cycle Computer (SCC) Refereces: Chapter 9 of M. Morris Mao ad Charles Kime, Logic ad Computer Desig Fudametals, Pearso Pretice Hall, 4 th Editio, 28. Overview Part Datapaths Itroductio Datapath Example Arithmetic Logic Uit (ALU) Shifter Datapath Represetatio ad Cotrol Word Part 2 A Simple Computer Istructio Set Architecture (ISA) Sigle-Cycle Hardwired Cotrol Part 3 Multiple Cycle Hardwired Cotrol Sigle Cycle Computer Issues Sequetial Cotrol Desig

2 Itroductio Computer Specificatio Istructio Set Architecture (ISA) - the specificatio of a computer's appearace to a programmer at its lowest level Computer Architecture - a high-level descriptio of the hardware implemetig the computer derived from the ISA The architecture usually icludes additioal specificatios such as speed/performace, cost, ad reliability Itroductio Simple computer architecture decomposed ito: Datapath: performig operatios (i.e., data maipulatio) A set of registers Microoperatios performed o the data stored i the registers A cotrol iterface Cotrol uit: cotrollig datapath operatios Programmable & No-programmable Cotrol iputs Data iputs Cotrol uit Status sigals Cotrol sigals Datapath Cotrol outputs Data outputs 2

3 Datapath Example Load eable Write D data A address A select address select Register file: Four parallel-load regs Two mux-based register selectors Register destiatio decoder Microoperatio implemetatio Mux for exteral costat iput uses A ad with exteral address ad data outputs Fuctio Uit: ALU ad Shifter with Mux F for output select Mux D for exteral data iput Logic for geeratig status bits: V, C, N, 2 3 Decoder D address 2 Costat i Destiatio select V C N Load Load Load Load M select us A MD select us D MUX MUX D us 2 2 A data A G select H select 4 A 2 S 2: C S i Arithmetic/logic IR Shifter IL uit (ALU) G H ero Detect MF select R R R2 R3 MUX F F 2 3 MUX Fuctio uit 2 3 MUX data Register file Address Out Data Out Data I Datapath Example: Performig a Microoperatio Microoperatio: R R + R2 Apply to A select to place cotets of R oto us A Apply to select to place cotets of R2 oto data ad apply to M select to place data o us Apply to G select to perform additio G = us A + us Apply to MF select ad to MD select to place the value of G oto US D Apply to Destiatio select to eable the Load iput to R Apply to Load Eable to force the Load iput to R to so that R is loaded o the clock pulse (ot show) The overall microoperatio requires clock cycle Load eable Write D data 2 3 Decoder D address 2 Costat i Destiatio select V C N Load Load Load Load M select us A MD select MUX D us D MUX us 2 2 A data A G select H select 4 A 2 S 2: C S i Arithmetic/logic IR Shifter IL uit (ALU) G H ero Detect MF select R R R2 R3 MUX F F A address A select 2 3 MUX address 2 3 Fuctio uit select MUX Register file data Address Out Data Out Data I 3

4 Datapath Example: Key Cotrol Actios for Microoperatio Alteratives Various microoperatios: Perform a shift microoperatio: apply to MF select Use a costat i a micro-operatio usig us : apply to M select Provide a address ad data for a memory or output write microoperatio apply to Load eable to prevet register loadig Provide a address ad obtai data for a memory or output read microoperatio apply to MD select For some of the above, other cotrol sigals become do't cares Load eable Write D data 2 3 Decoder D address 2 Costat i Destiatio select V C N Load Load Load Load M select R R R2 R3 us A MD select MUX D us D MUX A address us A select 2 2 MUX A data A G select H select 4 A 2 S 2: C S i Arithmetic/logic IR Shifter IL uit (ALU) G H ero Detect MF select MUX F Fuctio uit F 2 3 address select 2 3 MUX Register file data Address Out Data Out Data I Overview Part Datapaths Itroductio Datapath Example Arithmetic Logic Uit (ALU) Shifter Datapath Represetatio ad Cotrol Word Part 2 A Simple Computer Istructio Set Architecture (ISA) Sigle-Cycle Hardwired Cotrol Part 3 Multiple Cycle Hardwired Cotrol Sigle Cycle Computer Issues Sequetial Cotrol Desig 4

5 Arithmetic Logic Uit (ALU) Decompose the ALU ito: A arithmetic circuit & A logic circuit A selector to pick betwee the two circuits Ci Ci Ci Ci + Ai i S S Ai i S S Oe stage of arithmetic circuit 2-to- MUX Gi Ai i S Oe stage of logic circuit S S S2 Arithmetic Circuit Arithmetic circuit desig Decompose the arithmetic circuit ito: A -bit parallel adder A logic block that selects four choices for iput to the adder There are oly four fuctios of to select as Y i G = A + Y +C i : Y C i = C i = G = A G = A + G = A + G = A G = A + G = A + + G = A + + G = A Ci A iput logic S X Y -bit parallel adder G= X+ Y + Ci Arithmetic operatios S Cout 5

6 4-it asic Left/Right Shifter 3 2 IR IL 2 M S UX 2 M S UX 2M S UX S 2 M UX S 2 H3 H2 H H Serial Iputs: I R for right shift I L for left shift Shift Fuctios: (S, S ) = Pass uchaged Right shift Left shift Uused arrel Shifter D3 D2 D D S S 3 S S S S 3 2 S S 3 2 S S M M M M UX UX UX UX Y3 Y2 Y Y A rotate is a shift i which the bits shifted out are iserted ito the positios vacated The circuit rotates its cotets left from to 3 positios depedig o S: S = positio uchaged S = rotate left by 2 positios S = rotate left by positios S = rotate left by 3 positios 6

7 Example 8-bit: Layer shifts by, 4 Layer 2 shifts by, 2 Layer 3 shifts by, Large barrel shifters ca be costructed usig: Layers of multiplexers 2-dimesioal array circuits desiged at the electroic level Overview Part Datapaths Itroductio Datapath Example Arithmetic Logic Uit (ALU) Shifter Datapath Represetatio ad Cotrol Word Part 2 A Simple Computer Istructio Set Architecture (ISA) Sigle-Cycle Hardwired Cotrol Part 3 Multiple Cycle Hardwired Cotrol Sigle Cycle Computer Issues Sequetial Cotrol Desig 7

8 Datapath Represetatio I the register file: Select iputs for multiplexers => A address & address Decoder iput => D address Load eable => write Iput data to the registers => D data Multiplexer outputs => A data & data The register file ow appears like a memory based o clocked flipflops FS? Costat i M select FS V C N m m 4 MD select D data Write D address 2 m x Register file A address A data A us A address data Fuctio uit F MUX D MUX m us Address out Data out Data i Defiitio of Fuctio Select (FS) Codes FS(3:) MF Select G H Select(3:) Select(:) FS Microoperatio V C N G select 4 A ero Detect MF select F A S 2: C i Arithmetic/logic uit (ALU) G MUX F H select 2 S IR Shifter IL H Fuctio uit XX XX XX XX XX XX XX XX X XX X XX X XX X XX XXXX XXXX XXXX F A F A + F A + F A + + F A + F A + + F A - F A F A F A F A F A F F sr F sl oolea Equatios: MF i = F 3 F 2 G i = F i H i = F i 8

9 The Cotrol Word The datapath has may cotrol iput sigals, ca be orgaized ito a cotrol word To execute a microistructio, we apply cotrol word values for a clock cycle DA AA A M Cotrol word FS DA D Address, AA A Address A Address, M Mux FS Fuctio Select, MD Mux D RW Register Write M R D W RW 5 DA AA V C N Write Costat i M6 D data D address 8x Register file A address A data MD A us A Fuctio uit us D address data MUX MUX D us 5 4 FS A 7 Address out Data out Data i Cotrol Word Ecodig DA, AA, A M FS MD RW Fuctio Code Fuctio Code Fuctio Code Fuctio Code Fuctio Code R Register F A Fuctio No write R Costat F A + Data I Write R2 F A + R3 F A + + R4 F A + R5 F A + + R6 F A - R7 F A F A F A F A F A F F sr F sl 9

10 Microoperatios for the Datapath Symbolic & iary Represetatio Microoperatio DA AA A M FS MD RW R R2 R3 R R2 R3 Register F = A + + Fuctio Write R4 sl R6 R4 R6 Register F = sl Fuctio Write R7 R7 + R7 R7 Register F = A + Fuctio Write R R + 2 R R Costat F = A + Fuctio Write Data out R3 R3 Register No Write R4 Data i R4 Data i Write R5 R5 R R Register F = A Fuctio Write Microoperatio DA AA A M FS MD RW R R2 R3 R4 s l R6 R7 R7 + R R + 2 Data out R3 R4 Data i R5 XXX XXX XXX XXX XXX XXXX X XXX XXX X XXXX Datapath Simulatio clock DA AA A FS Costat_i X 2 M Address_out Data_out Data_i MD RW reg reg reg2 reg3 reg4 reg5 reg6 reg7 Status_bits X X 7 8

11 Overview Part Datapaths Itroductio Datapath Example Arithmetic Logic Uit (ALU) Shifter Datapath Represetatio ad Cotrol Word Part 2 A Simple Computer Istructio Set Architecture (ISA) Sigle-Cycle Hardwired Cotrol Part 3 Multiple Cycle Hardwired Cotrol Sigle Cycle Computer Issues Sequetial Cotrol Desig Istructio Set Architecture (ISA) for Simple Computer (SC) Istructios are stored i RAM or ROM as a program, the addresses for istructios are provided by a program couter (PC) Cout up or load a ew address The PC ad associated cotrol logic are part of the Cotrol Uit A typical istructio specifies: Operads to use Operatio to be performed Where to place the result, or which istructio to execute ext Executig a istructio Activate the ecessary sequece of operatios specified by the istructio e cotrolled by the cotrol uit ad performed i: Datapath Cotrol uit Exteral hardware such as memory or iput/output

12 ISA Examples RISC (Reduced Istructio Set Computer) Digital Alpha Su Sparc MIPS RX IM PowerPC HP PA/RISC CISC (Complex Istructio Set Computer) Itel x86 Motorola 68 DEC VAX VLIW (Very Large Istructio Word) Itel Itaium ISA: Storage Resources "Harvard architecture : separate istructio ad data memories Permit use of sigle clock cycle per istructio implemetatio Istructio memory 2 5 x 6 Program couter (PC) Register file 8 x 6 Due to use of "cache" i moder computer architectures, it is a fairly realistic model Data memory 2 5 x6 2

13 ISA: Istructio Formats The three formats are: Register, Immediate, ad Jump/rach Opcode Destiatio register (DR) (a) Register (c) Jump ad rach Source register A (SA) Source register (S) Opcode Destiatio register (DR) (b) Immediate Source register A (SA) Operad (OP) Opcode Address (AD) (Left) Source register A (SA) Address (AD) (Right) All formats cotai a Opcode field i bits 9 through 5. The Opcode specifies the operatio to be performed ISA: Istructio Format - Register Opcode Destiatio register (DR) Source register A (SA) Source register (S) (a) Register This format supports: R R2 + R3 R sl R2 Three 3-bit register fields: DR - destiatio register (R i the examples) SA - the A source register (R2 i the first example) S - the source register (R3 i the first example ad R2 i the secod example) Why is R2 i the secod example S istead of SA? 3

14 ISA: Istructio Format - Immediate Opcode Destiatio register (DR) (b) Immediate Source register A (SA) Operad (OP) This format supports: R R2 + 3 The Source Register field is replaced by a Operad field OP specifyig a costat. (3-bit costat, values from to 7) The costat: ero-fill (o the left of) the operad to form 6-bit costat 6-bit represetatio for values through 7 ISA: Istructio Format - Jump & rach Opcode Address (AD) (Left) Source register A (SA) Address (AD) (Right) (c) Jump ad rach This istructio supports chages i the sequece of istructio executio by addig a exteded, 6-bit, siged 2 s-complemet address offset to the PC value The SA field: permits jumps ad braches o N or based o the cotets of Source register A The Address (AD) field (6-bit) replaces the DR ad S fields Example: Suppose that a jump for the Opcode ad the PC cotais 45 ( ) ad AD cotais -2 (). The the ew PC value will be: + ( ) = (i.e., 45 + (-2) = 33) 4

15 ISA: Istructio Specificatios Istr uctio Opcode Memoic Format Descriptio St atus its Move A MOVA RD,RA R[DR] R[SA] N, Icremet INC RD,RA R[DR] R[SA] + N, Add ADD RD,RA,R R[DR] R[SA] + R[ S] N, Subtract SU RD,RA,R R[DR] R[SA] - R[S] N, Decremet DEC RD,RA R[DR] R[SA] - N, AND AND RD,RA,R R[DR] R[SA] R[S ] N, OR OR RD,RA,R R[DR] R[SA] R[S] N, Exclusive OR XOR RD,RA,R R[DR] R[SA] R[S] N, NO T NO T RD,RA R[DR] R[SA ] N, Move MOV RD,R R[DR] R[S] Shift Right SHR RD,R R[DR] sr R[S] Shift Left SHL RD,R R[DR] sl R[S] Load Immediate LDI RD, OP R[DR] zf OP Add Immediate ADI RD,RA,OP R[DR] R[SA] + zf OP Load LD RD,RA R[DR] M[R[SA]] Store ST RA,R M[R[SA]] R[S] rach o ero R RA,AD if (R[SA] = ) PC PC + se A D rach o Negative RN RA,AD if (R[SA] < ) PC PC + se A D Jump JMP RA PC R[SA] ISA: Example Istructios ad Data i Memory Memory Represetatio of Istructio ad Data Decimal Ad dress Memory Cotets Decimal Opcode Other Field Operatio 25 5 (Subtract) DR:, SA:2, S:3 R R2 - R (Store ) SA:4, S:5 M[ R4] R (Add Im mediate) DR: 2, SA :7, OP :3 R 2 R (rach o ero ) AD: 44, SA:6 If R6 =, PC PC Data = 92. After executio of istructio i 35, Data = 8. 5

16 Overview Part Datapaths Itroductio Datapath Example Arithmetic Logic Uit (ALU) Shifter Datapath Represetatio ad Cotrol Word Part 2 A Simple Computer Istructio Set Architecture (ISA) Sigle-Cycle Hardwired Cotrol Part 3 Multiple Cycle Hardwired Cotrol Sigle Cycle Computer Issues Sequetial Cotrol Desig V CN rach Cotrol PC IR(8:6) IR(2:) Exted Sigle-Cycle Hardwired Cotrol: J L P C D A A A A Address Istructio memory Istructio Istructio decoder ased o the ISA defied, desig a computer architecture to support the ISA The architecture is to fetch ad execute each istructio i a sigle clock cycle ero fill IR(2:) M F M R M J S D W W L P C CONTROL RW DA AA Costat i FS V C N us A A MD us D D Register file A MUX us Fuctio uit F MUX D A M DATAPATH Address out Data out MW Data_i Address Data i Data memory Data out 6

17 The Cotrol Uit Datapath: the Data Memory has bee attached to the Address Out, Data Out, ad Data I lies of the Datapath. Cotrol Uit: The MW iput to the Data Memory is the Memory Write sigal from the Cotrol Uit. The Istructio Memory address iput is provided by the PC ad its istructio output feeds the Istructio Decoder. ero-filled IR(2:) becomes Costat I Exteded IR(8:6) IR(2:) ad us A are address iputs to the PC. The PC is cotrolled by rach Cotrol logic Program Couter (PC) Fuctio PC fuctio is based o istructio specificatios ivolvig jumps ad braches: rach o ero R if (R[SA] = ) PC PC + se A D rach o Negative RN if (R[SA] < ) PC PC + sea D Jump JMP PC R[SA ] The first two trasfers require additio to the PC of: Address Offset = Exteded IR(8:6) IR(2:) The third trasfer requires that the PC be loaded with: Jump Address = us A = R[SA] I additio to the above register trasfers, the PC must implemet the coutig fuctio: PC PC + 7

18 PC Fuctio (Cotd.) rach Cotrol determies the PC trasfers based o five iputs: N, egative ad zero status bits PL load eable for the PC J Jump/rach select: If J =, Jump, else rach C rach Coditio select: If C =, brach for N =, else brach for =. PL J C PC Operatio X X Cout Up X Jump rach o Negative (else Cout Up) rach o ero (else Cout Up) Istructio Decoder Coverts the istructio ito the sigals ecessary to cotrol the computer durig the sigle cycle executio, combiatioal Iputs: the 6-bit Istructio Outputs: cotrol sigals DA, AA, ad A: Register file addresses (IR (8:)) simply pass-through sigals: DA = DR, AA = SA, ad A = S FS: Fuctio Uit Select M ad MD: Multiplexer Select Cotrols RW ad MW: Register file ad Data Memory Write Cotrols PL, J, ad C: PC Cotrols Observe that for other tha braches ad jumps, FS = IR(2:9) The other cotrol sigals should deped as much as possible o IR(5:3) 8

19 Istructio Decoder (Cotd.) Truth Table for Istructio Decoder Logic Istructio Fuctio Type Istructio its Cotrol Word its M MD RW MW PL J C. Fuctio uit operatios usig registers X 2. Memory read X 3. Memory write X 4. Fuctio uit operatios usig register ad costat X 5. Coditioal brach o zero () X X X X X X X X X X X 6. Coditioal brach o egative X X (N) 7. Ucoditioal Jump X X X X Istructio Decoder (Cotd.) Istructio types are based o the cotrol blocks ad the seve cotrol sigals to be geerated (M, MD, RW, MW, PL, J, C): Datapath ad Memory Cotrol (types -4) Mux Memory ad Mux D PC Cotrol (types 5-7) it 5 = it 4 = => PL it 3 => J. it 9 was use as C which cotradicts FS = eeded for braches. To force FS() to for braches, it 9 ito FS() is disabled by PL. 9

20 Istructio Decoder (Cotd.) The ed result by use of the types, careful assigmet of codes, ad use of do't cares, yields very simple logic: This completes the desig of most of the essetial parts of the sigle-cycle simple computer Istructio Opcode DR SA S DA AA A M FS MD RW MW PL J C Cotrol word Example Istructio Executio Decodig, cotrol iputs ad paths show for ADI, LD ad R o ext 6 slides 2

21 Decodig for ADI Istructio Opcode DR SA S DA 6 4 AA 3 A M 9 6 FS MD RW MW PL J C 2 Cotrol word V CN rach Cotrol J L P C Icremet PC D A A A A PC Address Istructio memory Istructio IR(8:6) IR(2:) Exted Istructio decoder ero fill IR(2:) M F M R M J S D W W L P C CONTROL RW DA AA Costat i FS V C N us A D Register file A A MUX us + Fuctio uit F A M Cotrol Iputs ad Paths for ADI Address out Data out MW Data i Address Data memory Data out No Write Data i MD us D MUX D DATAPATH 2

22 Decodig for LD Istructio Opcode DR SA S DA 6 4 AA 3 A M 9 6 FS MD RW MW PL J C 2 Cotrol word V CN rach Cotrol PC IR(8:6) IR(2:) Exted Cotrol Iputs ad Paths for LD J L P C Icremet PC D A A A A Address Istructio memory Istructio Istructio decoder ero fill IR(2:) M F M R M J S D W W L P C CONTROL RW DA AA Costat i FS V C N us A D Register file A A MUX us Fuctio uit F A M Address out Data out MW Data i Address Data i Data memory Data out No Write MD us D MUX D DATAPATH 22

23 Decodig for R Istructio Opcode DR SA S DA 6 4 AA 3 A M 9 6 FS MD RW MW PL J C 2 Cotrol word V CN rach Cotrol J L P C rach o D A A A A PC Address Istructio memory Istructio IR(8:6) IR(2:) Exted Istructio decoder ero fill IR(2:) M F M R M J S D W W L P C CONTROL RW DA AA Costat i FS V C N us A No Write D Register file A A MUX us Fuctio uit F A M Cotrol Iputs ad Paths for R Address out Data out MW Data i Address Data memory Data out No Write Data i MD us D MUX D DATAPATH 23

24 Abstract View of Critical Path Overview Part Datapaths Itroductio Datapath Example Arithmetic Logic Uit (ALU) Shifter Datapath Represetatio ad Cotrol Word Part 2 A Simple Computer Istructio Set Architecture (ISA) Sigle-Cycle Hardwired Cotrol Part 3 Multiple Cycle Hardwired Cotrol Sigle Cycle Computer Issues Sequetial Cotrol Desig 24

25 Sigle-Cycle Computer Issues Shortcomig of Sigle Cycle Desig Complexity of istructios executable i a sigle cycle is limited Accessig both a istructio ad data from a simple sigle memory impossible A log worst case delay path limits clock frequecy ad the rate of performig istructios Hadlig of Shortcomigs The first two shortcomigs ca be hadled by the multiple-cycle computer The third shortcomig is dealt with by usig a techique called pipeliig described i later lectures Multiple-Cycle Computer Covertig the sigle-cycle computer ito a multiple-cycle computer ivolves: Modificatios to the datapath/memory Modificatio to the cotrol uit Desig of a multiple-cycle hardwired cotrol 25

26 V CN rach Cotrol PC IR(8:6) IR(2:) Exted J L P C D A A A A Address Istructio memory Istructio Istructio decoder ero fill IR(2:) M F M R M J S D W W L P C CONTROL Sigle-Cycle Simple Computer (SC) RW DA AA Costat i FS V C N us A A MD us D D Register file A MUX us Fuctio uit F MUX D A M DATAPATH Address out Data out MW Data i Address Data i Data memory Data out Datapath Modificatios New Istructio Path Use a sigle memory for both istructios ad data Requires ew MUX M with cotrol sigal MM to select betwee the istructio address from the PC ad the data address Ist. & Data Address Mux Requires path from Memory Data Out to the istructio register i the cotrol uit Ist. & Data Memory 26

27 Datapath Modificatios (Cotiued) Additioal registers eeded to hold operads betwee cycles Add 8 temporary storage registers to the Register File Register File becomes 6 x 6 Addresses to Register File icrease from 3 to 4 bits Register File addresses come from: The istructio for the Storage Resource registers ( to 7) The cotrol word for the Temporary Storage registers (8 to 5) Add Register Address Logic to the Register File to select the register address sources Three ew cotrol fields for register address source selectio ad temporary storage addressig: DX, AX, X Register Address Logic 6 x 6 Register File 27

28 Cotrol Uit Modificatios Must hold istructio over the multiple cycles to draw o istructio iformatio throughout istructio executio Requires a Istructio Register (IR) to hold the istructio Load cotrol sigal IL Requires the additio of a "hold" operatio to the PC sice it oly couts up to obtai a ew istructio New ecodig for the PC operatios uses 2 bits Add "hold" operatio Istructio Register IR 28

29 Overview Part Datapaths Itroductio Datapath Example Arithmetic Logic Uit (ALU) Shifter Datapath Represetatio ad Cotrol Word Part 2 A Simple Computer Istructio Set Architecture (ISA) Sigle-Cycle Hardwired Cotrol Part 3 Multiple Cycle Hardwired Cotrol Sigle Cycle Computer Issues Sequetial Cotrol Desig Sequetial Cotrol Desig To cotrol microoperatios over multiple cycles, a Sequetial Cotrol replaces the Istructio Decoder Iput: Opcode, Status its, Cotrol State Output: Cotrol Word (Modified Datapath Cotrol part) Next State: Cotrol Word (New Sequecig Cotrol part) Cosists of: Register to store the Cotrol State Combiatioal Logic to geerate the Cotrol Word (both sequecig ad datapath cotrol parts) The Combiatioal Logic is quite complex so we assume that it is implemeted by usig a PLA or sythesized logic ad focus o ASM level desig 29

30 Cotrol State Register Combiatioal Cotrol Logic New/ Modified Cotrol Word Cotrol Word NS PS I L Sequecig M DX AX X FS Datapath Datapath part: field MM added, ad fields DX, AX, ad X replace DA, AA, ad A, respectively If the MS of a field is, e.g., AX = XXX, the AA is cocateated with SA (3bits) field i the IR If the MS of a field is, e. g. AX =, the AA = Sequecig part: IL cotrols the loadig of the IR PS cotrols the operatios of the PC NS gives the ext state of the Cotrol State register E.g., NS is 4 bits, the legth of the Cotrol State register - 6 states are viewed as adequate for this desig M D R M M W M W 3

31 Ecodig for Datapath Cotrol DX AX X Code M Code FS Code MD RW MM MW Code R[DR] R[SA] R[S] XXX Register F A FUt No write Address Out No write R8 R8 R8 Costat F A + Data I Write PC Write R9 R9 R9 F A + R R R Uused R R R Uused R2 R2 R2 F A + + R3 R3 R3 F A R4 R4 R4 Uused R5 R5 R5 F A ^ F A v F A + F A F F sr F sl Uused Ecodig for Sequecig Cotrol NS PS IL Next State Actio Code Actio Code Gives ext state of Cotrol State Register Hold PC No load Ic PC Load istr. rach Jump 3

32 ASM Charts for Sequetial Cotrol A istructio requires two steps: Istructio fetch obtaiig a istructio from memory Istructio executio the executio of a sequece of microoperatios to perform istructio processig Due to the use of the IR, these two steps require a miimum of two clock cycles ISA: Istructio Specificatios ad ASM charts for the istructios (that all require two clock cycles) A vector decisio box is used for the opcode Scalar decisio boxes are used for the status bits ISA: Istructio Specificatios (for referece) Istructio Speci ficatios for the SimpleComputer - Part Istr uctio Opcode Memoic Format Descriptio St atus its Move A MOVA RD,RA R[DR] R[SA] N, Icremet INC RD,RA R[DR] R[SA] + N, Add ADD RD,RA,R R[DR] R[SA] + R[ S] N, Subtract SU RD,RA,R R[DR] R[SA] - R[S] N, Decremet DEC RD,RA R[DR] R[SA] - N, AND AND RD,RA,R R[DR] R[SA] R[S ] N, OR OR RD,RA,R R[DR] R[SA] R[S] N, Exclusive OR XOR RD,RA,R R[DR] R[SA] R[S] N, NO T NO T RD,RA R[DR] R[SA ] N, 32

33 ASM Chart for 2-Cycle Istructios - Part R[DR] R[SA] R[DR] R[SA] + R[S] R[DR] R[SA] R[DR] R[SA] v R[S] R[DR] R[SA] PC PC + R[DR] R[SA]+ R[DR] R[SA] + R[S] + R[DR] R[SA] R[S] R[DR] R[SA] + R[S] IN F EX IR M[PC] Opcode ISA: Istructio Specificatios (for referece) Istructio Specificatios for the Simple Computer - Part 2 Istr uctio Opcode Memoic Format Descriptio St atus its Move MOV RD,R R[DR] R[S] Shift Right SHR RD,R R[DR] sr R[S] Shift Left SHL RD,R R[DR] sl R[S] Load Immediate LDI RD, OP R[DR] zf OP Add Immediate ADI RD,RA,OP R[DR] R[SA] + zf OP Load LD RD,RA R[DR] M[SA] Store ST RA,R M[SA] R[S] rach o ero R RA,AD if (R[SA] = ) PC PC + se A D rach o Negative RN RA,AD if (R[SA] < ) PC PC + se A D Jump JMP RA PC R[SA] 33

34 Portio i Red duplicated from previous ASM chart IN F IR M[PC] EX Opcode PC PC + R[DR] M[ R[SA] ] R[DR] zf OP R[DR] R[S] M[ R[SA] ] R[S] ASM Chart for 2-Cycle Istructios - Part 2 R[DR] R[SA] + zf OP To INF N PC PC + se AD PC R[SA] Chapter Part 2 State Table for 2-Cycle Istructios State Opcode Iputs VCN Next st ate I L Outputs P S DX AX X M FS M D R M M W M W Comme ts INF XXXXXXX XXXX EX XXXX XXXX XXXX X XXXX X IR M[PC ] EX XXXX INF XXX XXX XXXX X X MOVA R[DR] R[SA]* EX XXXX INF XXX XXX XXXX X X INC R[DR] R[SA] + * EX XXXX INF XXX XXX XXX X ADD R[DR] R[SA] + R[S]* EX XXXX INF XXX XXX XXX X SU R[DR} R[SA] + R[ S] + * EX XXXX INF XXX XXX XXXX X X DEC R[DR] R[SA] + (- )* EX XXXX INF XXX XXX XXX X AND R[DR] R[SA] ^ R[S]* EX XXXX INF XXX XXX XXX X OR R[DR] R[SA] v R[S]* EX XXXX INF XXX XXX XXX X XOR R[DR] R[SA] + R[S]* EX XXXX INF XXX XXX XXXX X X NOT R[DR] R [ SA ] * EX XXXX INF XXX XXXX XXX X MOV R[DR] R[S]* EX XXXX INF XXX XXX XXXX X XXXX LD R[DR] M[R[SA]]* EX XXXX INF XXXX XXX XXX XXXX X ST M[R[SA]] R[S]* EX XXXX INF XXX XXXX XXXX LDI R[DR] zf OP* EX XXXX INF XXX XXX XXXX ADI R[DR] R[SA] + zf OP* EX XXX INF XXXX XXX XXXX X X R PC PC + se AD EX XXX INF XXXX XXX XXXX X X R PC PC + EX XXX INF XXXX XXX XXXX X X RN PC PC + se AD EX XXX INF XXXX XXX XXXX X X RN PC PC + EX XXXX INF XXXX XXX XXXX X X JMP PC R[SA] * For this state ad iput combiatios, PC PC+ also occurs 34

35 3-Process ASM VHDL Code etity cotroller is port ( opcode : i std_logic_vector(6 dowto ); reset, clk : i std_logic; zero, egative : i std_logic; IL, M, MD, MM, RW, MW : out std_logic; PS : out std_logic_vector( dowto ); DX, AX, X, FS : out std_logic_vector(3 dowto ); ); ed cotroller; architecture ehavioral of cotroller is type state_type is (RES, FTH, EX); sigal cur_state, ext_state : state_type; begi state_register:process(clk, reset) begi if (reset='') the cur_state<=res; elsif (clk'evet ad clk='') the cur_state<=ext_state; ed if; ed process; 3-Process ASM VHDL Code out_fuc: process (cur_state, opcode, zero, egative) begi (IL,PS, M, FS, MD, RW, MW, MM) <= std_logic_vector'(x""); FS<=""; case cur_state is whe RES => ext_state <= FTH; whe FTH => -- set the cotrol vector values ext_state <= EXE; whe EXE => case opcde is: whe +> ed process; ed ehavioral; 35

36 ASM Chart for Multiple its Right Shift EX Opcode R8 R[SA] R8 used to perform shifts EX R9 used to store ad decremet shift cout EX2 R9 zf OP Opcode ero test i EX is to determie if the shift amout is ; if so, goes to state INF Opcode R8 sr R8 EX3 R9 R9 - Opcode EX4 PC PC+ Opcode R[DR] R8 To INF State Table For Multiple its Right Shift St at e Opcode Iputs VCN Next st at e Outputs I L PS DX AX X M FS MD RW MM M W Co mmets EX XXX EX XXX XXXX X X SRM R8 R[SA], : EX EX XXX INF XXX XXXX X X SRM R8 R[SA],: INF* EX XXX EX2 XXXX XXXX X SRM R9 zf OP, : EX2 EX XXX INF XXXX XXXX X SRM R9 zf OP,: INF* EX2 XXXX EX3 XXXX X SRM R8 sr R8, EX3 EX3 XXX EX2 XXXX X X SRM R9 R9 -, : EX2 EX3 XXX EX4 XXXX X X SRM R9 R9 -,: EX4 EX4 XXXX INF XXX XXXX X X SRM R[DR] R8, INF* * For this state ad iput combiatios, PC PC+ also occurs 36

37 Summary Cocept of Datapath for implemetig computer microistructios Cotrol word provides a meas of orgaizig the cotrol of the microoperatios Cocept of ISA ad istructio formats ad operatios of Simple Computer (SC) Sigle clock cycle vs. multiple cycle (istructio fetch + istructio executio) 37