Chapter 8. I/O operations initiated by program instructions. Requests to processor for service from an I/O device

Transcription

1 hapter 8 The I/O subsystem I/O buses and addresses Programmed I/O I/O operations initiated by program instructions I/O interrupts Requests to processor for service from an I/O device irect Memory ccess (M) Moving data in and out without processor intervention I/O data format change and error control Error detection and correction coding of I/O data omputer ystems esign and rchitecture

2 eparate Memory and I/O onnections to Processor llows tailoring bus to its purpose, but Requires many connections to PU (pins) Memory & I/O access can be distinguished Timing and synch. can be different for each Least expensive option peed penalty omputer ystems esign and rchitecture

3 Memory Mapped I/O ombine memory control and I/O control lines to make one unified bus for memory and I/O This makes addresses of I/O device registers appear to the processor as memory addresses Reduces the number of connections to the processor chip Increased generality may require a few more control signals tandardizes data transfer to and from the processor synchronous operation is optional with memory, but demanded by I/O devices omputer ystems esign and rchitecture

4 ddress pace of Memory Mapped I/O omputer ystems esign and rchitecture

5 Programmed I/O evice Interface tructure Focus on the unified I/O interface between the memory bus and an arbitrary device. everal device registers (memory addresses) share address decode and control logic. omputer ystems esign and rchitecture

6 R I/O Register ddress ecoder elects the I/O space elects this device ssumes R addresses above FFFFF are reserved for I/O registers llows for 1024 registers of 32 bits The range from FFFF to FFFFFFFF 16 is addressable by a negative displacement omputer ystems esign and rchitecture

7 Interface esign for R haracter Output omputer ystems esign and rchitecture

8 ynchronous and emi-synchronous ata Input Used for register to register inside PU Used for memory to PU read with a few cycle memory Used for I/O over longer distances (feet) omputer ystems esign and rchitecture

9 synchronous ata input May I? Yes, you may. Thanks. You re welcome. Ready cknowledge at a v alid t robe dat a (c) synchronous input omputer ystems esign and rchitecture

10 Example: Programmed I/O evice river for haracter Output evice requirements: 8 data lines set to bits of an II character tart signal to begin operation ata bits held until device returns one signal esign decisions matching bus to device Use low order 8 bits of word for character Make loading of character register signal tart lear Ready status bit on tart & set it on one Return Ready as sign of status register for easy testing Output Register tatus Register Ready Unused haracter Unused omputer ystems esign and rchitecture

11 Fig 8.8 haracter Output Program Fragment tatus register OTT = FFFFF110H Output register OUT = FFFFF114H lar r3, Wait ;et branch target for wait. ldr r2, har ;Get character for output. Wait: ld r1, OTT ;Read device status register, brpl r3, r1 ; test for ready, and repeat if not. st r2, OUT ;Output character and start device. For readability: I/O registers are all caps., program locations have initial cap., and instruction mnemonics are lower case 10 MIP R would execute 10,000 instructions waiting for a 1,000 character/sec printer omputer ystems esign and rchitecture

12 implified Interrupt Interface Logic Request and enable flags per device Returns vector and interrupt information on bus when acknowledged omputer ystems esign and rchitecture

13 aisy-hained Interrupt How does acknowledge signal select one and only one device to return interrupt info.? One way is to use a priority chain with acknowledge passed from device to device omputer ystems esign and rchitecture

14 Interrupt Logic for an R I/O Interface Request set by Ready, cleared by acknowledge iack only sent out if this device not requesting omputer ystems esign and rchitecture

15 Interrupt Response Time Response to another interrupt is delayed until interrupts reenabled by rfi haracter input handler disables interrupts for a maximum of 17 instructions If the PU clock is 20MHz, it takes 10 cycles to acknowledge an interrupt, and average execution rate is 8 PI Then 2nd interrupt could be delayed by ( sec omputer ystems esign and rchitecture

16 Priority Interrupt ystem with m = 2 k Levels omputer ystems esign and rchitecture

17 irect Memory ccess (M) llows external devices to access memory without processor intervention Requires a M interface device Must be set up or programmed, and transfer initiated. omputer ystems esign and rchitecture

18 teps a M evice Interface Must Take to Transfer Block of ata 1. Become bus master 2. end memory address and R/W signal 3. ynch. sending and receiving of data using complete 4. Release bus as needed (perhaps after each xfer) 5. dvance memory address to point to next data item 6. ount number of items transferred, check for end of data block 7. Repeat if more data to be transferred omputer ystems esign and rchitecture

19 I/O Interface rchitecture for a M evice omputer ystems esign and rchitecture

20 Multiplexer and elector M hannels omputer ystems esign and rchitecture

21 Error etection and orrection Bit Error Rate, BER, is the probability that, when read, a given bit will be in error. BER is a statistical property Especially important in I/O, where noise and signal integrity cannot be so easily controlled inside processor or worse in outside world Many techniques Parity check EE Encoding R omputer ystems esign and rchitecture

22 Parity hecking dd a Parity Bit to the word Even Parity: Make the parity bit 1 if needed to make number 1 of bits even, else make it 0 Odd Parity: Make the parity bit 1 if needed to make number of 1 bits odd, else make it 0 Example: for word , to add odd parity bit: omputer ystems esign and rchitecture

23 Multiple Parity hecks for a Hamming ode dd parity bits, P i, to data bits, i Reserve bit numbers that are a power of 2 for Parity Bits Example: P 1 =001, P 2 = 010, P 4 =100, etc. Each parity bit, P i, is computed over those data bits that have a "1" at the bit number of the parity bit. Example: P 2 (010) is computed from 3 (011), 6 (110), 7 (111),... Thus each bit takes part in a different combination of parity checks. When the word is checked, if only one bit is in error, all the parity bits that use it in their computation will be incorrect. omputer ystems esign and rchitecture

24 Motivating Example: use the Venn iagram to Explain Error etection and orrection using the Hamming ode b. insert data c. ender omputes and inserts even parity bits d. Receiver recomputes parity bits, detects and corrects error. omputer ystems esign and rchitecture

25 Example:Encode 1011 Using the Hamming ode and Odd Parity Insert the data bits: P 1 P 2 1 P P 1 is computed from P = 1, so P 1 = 1. P 2 is computed from P = 1, so P 2 = 0. P 4 is computed from P = 1, so P 4 = 1. The final encoded number is Note that the Hamming encoding scheme assumes that at most one bit is in error. omputer ystems esign and rchitecture

26 EE (ingle Error orrect, ouble Error etect) dd another parity bit, at position 0, which is computed to make the parity over all bits, data and parity, even or odd. If one bit is in error, a unique set of Hamming checks will fail, and the overall parity will also be wrong. Let c i be 1 if check i fails, otherwise 0. In the case of a 1-bit error, the string c k-1,..., c 1, c 0 will be the binary index of the erroneous bit. For Example if the c i string is 0110 then bit at position 6 is in error. If two bits are in error, one or more Hamming checks will fail, but the overall parity will be correct. Thus the failure of one or more Hamming checks, coupled with correct overall parity means that 2 bits are in error. This assumes that the probability of 3 or more bits being in error is negligible. omputer ystems esign and rchitecture

27 Example: ompute the odd parity EE encoding of the 8-bit value The 8 data bits would have 5 parity bits added to them to make the 13-bit value P 0 P 1 P 2 0 P P Now P 1 = 0, P 2 = 1, P 4 = 0, and P 8 = 0, and we can compute that P 0, overall parity, = 1, giving the encoded value: omputer ystems esign and rchitecture

28 Example: Extract the orrect ata Value from the EE- Encoded tring , ssuming odd Parity The string shows even parity, so there must be a single bit in error. hecks c 2 and c 4 fail, giving the binary index of the erroneous bits as 0110 = 6, so 6 is in error. It should be 0 instead of 1 omputer ystems esign and rchitecture

29 yclic Redundancy heck, R When data is transmitted serially over communications lines, the pattern of errors usually results in several or many bits in error, due to the nature of line noise. The "crackling" of telephone lines is this kind of noise. Parity checks are not as useful in these cases. Instead R checks are used. The R can be generated serially. It usually consists of XOR gates. omputer ystems esign and rchitecture

30 R Generator Based on the Polynomial x 16 + x 12 + x The number and position of XOR gates is determined by the polynomial R does not support error correction but the R bits generated can be used to detect multi-bit errors. The R results in extra R bits, which are appended to the data word and sent along. The receiving entity can check for errors by recomputing the R and comparing it with the one that was transmitted. omputer ystems esign and rchitecture

31 erial ata Transmission with ppended R ode omputer ystems esign and rchitecture