Introduction to HW design flows

Transcription

1 Graphics: Alexandra Nolte, Gesine Marwedel, 2003 Introduction to HW design flows

2 What you will get from this class This class will teach you how to use Hardware Description Languages (HDLs) to design, verify, and validate digital logic You will learn how to synthesize HDLs into hardware using the same tools used in industry (FPGA) You will participate in the always enlightening process of working to design a digital system in a team environment (optional) 2

3 Mobile SoC

4 A SoC Example

5 System Design & Verification

6 Design Abstraction Levels Applications Generic Software Operating System Controlling Software Architecture HW/SW Interface System High-level organization Digital Logic Building-block Modules Logic Building-block Gates Circuit Transistors, Capacitors, etc. Devices & Interconnects Structures, interconnects Physics Electrons, Ions, etc. Software HW/SW Hardware

7 Moore s Law The velocity of IC complexity growth is proportional to IC complexity at the moment [Gordon Moore, 1964] Comparison coefficient: 0.2 for processors, 0.4 for memory Intel386 Processor Intel Itanium Processor Intel Pentium 4 Processor Intel Core i7 6x Intel Xeon 8x Sun SPARC T3 16-Core Intel Xeon 7500 Processor Dual Core Intel Itanium 2 Processor Intel Pentium Processor Intel486 Processor Intel Itanium 2 Processor Intel Pentium III Processor Intel Pentium II Processor Xilinx Virtex-7 6,800,000,000 transistors dn N dt N=digital estimation of complexity

8 Logic IC Gates (Chip) Universität Dortmund Evolution of Circuits Complexity 1M 100K Fujitsu Hitachi IBM NEC K 1K 100 Logic IC (gates/chip) 10times/5years M M-200H M-880 ACOS3800 M-1800 M-780 ES M M-680H 3090S ACOS2000 M-280H 64M M-380 ACOS M 4M DRAM (bits/chip) 4times/3years DRAM Bits/Chip H K 64K 1M Lithography (µm)

9 Complexity Evolution Intel Pentium IV Intel Core i7 stmere jpg microprocessor-set-to-produce.html

10 Application Specific Integrated Circuits (ASICs)

11 Hardware Implementations HDLs can be compiled to semi-custom and programmable hardware implementations Full Custom Semi- Custom Programmable Manual VLSI Standard Cell Gate Array FPGA less work, faster time to market implementation efficiency PLD 11

12 ASIC Application Specific Integrated Circuit A chip designed to perform a particular operation as opposed to General Purpose integrated circuits An ASIC is generally NOT software programmable to perform a wide variety of different tasks An ASIC will often have an embedded CPU to manage suitable tasks An ASIC may be implemented as an FPGA Sometimes considered a separate category

13 Examples of ASICs Video processor to decode or encode MPEG-2 digital TV signals Low power dedicated DSP/controller /convergence device for mobile phones Encryption processor for security Many examples of graphics chips Network processor for managing packets, traffic flow, etc.

14 ASIC Styles Full Custom ASICs Every transistor is designed and drawn by hand Typically only way to design analog portions of ASICs Gives the highest performance but the longest design time Full set of masks required for fabrication

15 ASIC Styles (Contd.) Standard-Cell-Based ASICs or Cell Based IC (CBIC) or semi-custom Standard Cells are custom designed and then inserted into a library These cells are then used in the design by being placed in rows and wired together using place and route CAD tools Some standard cells, such as RAM and ROM cells, and some datapath cells (e.g. a multiplier) are tiled together to create macrocells D-flip-flop: NOR gate:

16 Standard Cell ASICs Sample ASIC floorplan: Standard Cell designs are usually synthesized from an RTL (Register Transfer Language) description of the design Intellectual Property Blocks (IPs) are often used to decrease Time to Market Hard IP (like SRAM): Technology Dependent, GDSII and libs Soft IP (DW library): Tech independent, delivered as RTL, with synthesis and verification scripts Standard-cell area (Soft Macro) Fixed blocks (Hard Macros) I/O cells

17 Standard Cell ASICs (cont d) Fabless semiconductor company model Company does design only. Fab performed by another company (e.g. TSMC, UMC, IBM, Philips, LSI). Back-end (place and route, etc.) might be performed at that company or with their assistance

18 FPGA Sample internal architecture: Store logic in look-up table (RAM) Programmable interconnect Programmable Interconnect Array: Configurable Logic Block (CLB):

19 FPGA (cont d)

20 Example Total cost calculation:

21 IC Cost The cost of non-recurrent engineering, NRE Design and mask preparation The cost factor of one time action The cost of recurrent engineering Semiconductor manufacturing, packaging, testing Proportional to size Proportional to IC area

22 NRE Value Increases Exploding NRE / Mask Costs Mask Costs (SM) ,05 0,1 0,15 0,2 Process Geometry (Micron) 70nm ASICs will have $4M NRE

23 Die Value One die Wafer Up to 16 (40cm) Source: AMD

24 Yield Y N N g t 100% C D N C t W Y N t d A w d /2 2 d w 2 A d N t, N g total number and number of yield ICs on one wafer C W, C D - wafer and die cost D w wafer diameter, A d die area d

25 Defects Y 1 n d A d 4 D d ) C f(a n d number of defects on unit area, α-approximately 3

26 Comments Market currently dominated by standard cell ASICs and FPGAs Ideally standard cell designs would be used for higher volume applications that justify the Nonrecurring engineering (NRE) Many consider FPGAs separate from ASICs. Why? Different level of design skills required, especially in back end (place and route or physical design) Reduced level of verification required before sending to factory Again reduces sophistication required of team Low-cost (barrier) of entry Often different, lower cost Design Automation (CAD) tools Lower performance However, front-end design (RTL coding) is virtually identical for each implementation style Sometimes FPGA done first and standard cell ASIC done later

27 ASIC DESIGN FLOW

28 Electronics Design Spec System Design Hardware Design Software Design Integration Production Abstract Detailed Algorithm Design Architectural Design HW/SW Partitioning Analog/Digital Partitioning Specs Models Specs Models Analog Design Digital Design Mask Design Circuit Board Design Package Design Specs Models Hardware Hardware Host Coding Embedded Coding Software System Test Parts Lists Schematics Code Test Procedures Etc Manufacturin g Analysis and Verification Tasks Functional, Performance, Power, Cost, Reliability, Testability

29 ASIC Design Flow Major Steps: 1.High Level Design Specification Capture Design Capture in C, C++, SystemC or SystemVerilog (etc.) HW/SW partitioning IP selection (choose from pre-existing designs or Intellectual Property ) IP REUSE 2.RTL Design Register Transfer Level description 3.System, Timing and Logic Verification Is the logic working correctly?

30 ASIC Design Flow 4. Logic Synthesis 5. Physical Design Floorplanning, Place and Route, Clock insertion 6. Performance and Manufacturability Verification Extraction of Physical View (PEX) Design Rule Checking (DRC) Layout vs Schematic (LVS) Verification of timing and signal integrity

31 ASIC Design Flow Spec RTL Coding Synthesis Design For Test Floorplanning Place and Route Chip Finishing GDSII Digital Implementation HDL Coding (Verilog/VHDL ) RTL Synthesis Clock Gating Gate Optimization (DC, DCT) Scan Insertion Scan Compressio n JTAG Integration (DC,DCT) Virtual Flat Planning Power Mesh Creation Prototype Route and IPO Pin Assignment Macro Processing Budgeting (JXT) Placement Optimization HFNS, Clock Optimization Route Optimization Power Closure Timing Closure (PC,Astro) Design For Manufacturing (Astro, Hercules) Timing Closure (Astro) ECO (Astro) Iteration Analysis and Verification Design Rules, Functionality, Timing, Area, Power, Testability, Reliability, Manufacturability (Leda,VCS,Magellan,PrimeTime,Star-RCXT,Formality,PrimeTime-PX,Tetramax,PrimeRail,Hercules)

32 RTL Coding Register Transfer Level (RTL) is a way of describing the operation of a synchronous digital circuit Circuit's behavior is defined in terms of the flow of signals (or transfer of data) between hardware registers, and the logical operations performed on those signals.

33 RTL Coding (Cntd) Most ASICs are designed using a RTL/Synthesis based methodology Design details captured in a simulatable description of the hardware Captured as Register Transfer Language (RTL) Simulations done to verify design

34 RTL Coding Spec clk) begin if (rstp == 1'b1) begin count <= 0; end else begin case ({readp, writep}) 2'b00: count <= count; 2'b01: // WRITE if (!fullp) count <= count + 1; 2'b10: // READ if (!emptyp) count <= count - 1; 2'b11: count <= count; endcase end end RTL Coding (Verilog/VHDL) VERIFICATION Meets Spec? No RTL Yes Synthesis

35 Verification Purpose of Verification: Discover as many potential bugs in the design as reasonable before sending chip out for fabrication Do this by simulating chip (and chip components) in Verilog Why is verification important? Chip fab might cost $4M and take 8 weeks Very expensive and time consuming to iterate chip fab! Want to get prototype correct in one to two fab cycles FPGAs can rely more on using the prototype for debug But, note, it is more difficult to debug hardware than a simulation

36 Verification (Cntd) Verification consumes more than 60% of design resources People, compute cycles Verification mainly done with pre-synthesis code Through some simulation, and other checks, are done to make sure the netlist is correct With increased reuse of existing Intellectual Property ( IP ), verification has become very challenging IP = Predesigned blocks, internally developed, purchased or obtained from open source Debugging is often harder than design! Focus of these Notes Primarily on verification tasks likely to be performed by module level designer, and code constructs commonly used

37 Verification Tools and Methods It is impossible to know that you have eliminated all the bugs in a design Thus it is important to use a variety of tools, techniques and methods that give you a high probability of discovering bugs And to have a plan to apply them! Get as many avenues of attack as possible Available tools and methods include: Simulation through test fixtures Including mixed level simulation Inserting and tracking assertions Formal verification Emulation

38 Simulations Through Test Fixtures Basic concept: Apply vectors to design as stimulus Observe outputs, and internal nodes, for correct functionality Key Questions: Where do you get the vectors? How do you observe the outputs? What are the available coding styles?

39 Functional Verification - RTL Behavioral simulation no delays for processing No performance parameters only functionality is verified Hardware description Not every construct in VHDL or Verilog can be implemented in hardware. This simulation will not show this.

40 Functional Verification Testbench

41 What is synthesis? The process of converting a hardware design described in a HDL into a structural netlist

42 In detail Design constraints Technology library (eg UMC 0.18) HDL Specification Module FSM(xx,xx) Begin xxx end HW inference Structural RTL (tech. Indep) Physical DA Logic Synthesis & Optimization Gate netlist

43 Logic Synthesis Automatic synthesis is used to turn the RTL into a gatelevel description ie. AND, OR gates, etc. Chip-test features are usually inserted at this point Gate level design verified for correctness Output of synthesis is a net-list i.e. List of logic gates and their implied connections NOR2 U36 (.Y(n107),.A0(n109),.A1(\value[2] ) ); NAND2 U37 (.Y(n109),.A0(n105),.A1(n103) ); NAND2 U38 (.Y(n114),.A0(\value[1] ),.A1(\value[0] ) ); NOR2 U39 (.Y(n115),.A0(\value[3] ),.A1(\value[2] ) );

44 Logic Synthesis Timing/Logic Library IP Library(DW) Physical Library RTL Timing Constraints Floorplan Synthesis (DC, DCT) residue = 16 h0000; if (high_bits == 2 b10) else residue = state_table[index]; state_table[index] = 16 h0000; Hardware Description Language (HDL) Synthesis HDL Translation Mapping Static Timing (DC/DCT/PC/PT) Formal Equivalence (FM) Power Analysis (DC/DCT/PC/PT-PX) Static Timing Placement Routing Estimation Meets Spec? No Optimization Design Rule Fixing Scan-Ready Netlist DFT Yes Target Technology (standard cells)

45 Floorplanning Corner cell I/O cell P/G buses Pad Die edge Bonding wire SOFT Macro Digital core Std Cell PLL RAM Leadframe Die Bonding Wire Core Area Resin mould Leadframe

46 Placement Physical Design tools used to turn the gate-level design into a set of chip masks (for photolithography) or a configuration file for downloading to an FPGA Floorplanning and Power Planning Positioning of major functions Placement of the Standard cells Gates arranged in rows

47 Clock Tree Synthesis (CTS) Clock and buffer Insertion Distribute clocks to cells and locate buffers for use as amplifiers in long wires

48 Routing Routing Logic Cells wired together Clock Routing Global Routing Detailed routing

49 Signoff & Chip Finishing Route Database Timing/Logic Library Hard Macro Library Physical Library Chip Finishing (Astro) Metal Fill Chip Finishing Double Via Insertion Filler Cell Insertion Critical Area Optimization Route Optimization STA with SI and SSTA for variations Antenna Fixing Route DRC Fixing IR drop and EM Analysis Design Rule Fixing Static Timing (PT/Star-RCXT) Formal Equiv (FM) Power Analysis (PTPX/PrimeRail) Route DRC (Hercules) LVS (Hercules) GDSII Meets Spec? Yes Mask Synthesis No GDSII

50 IC Fabrication General Technology Flow Diagram

51 Lithography Lithography is a basic method of IC fabrication process. Process is used to transfer patterns from masks to each layer of the IC on the surface of a wafer by employing a photosensitive, chemically resistant layer (photoresist). Masks are created using the layout information provided by the designer. The lithographic process is repeated on each physical layer, but the process sequence is always the same:

52 Photolithography

53 Photolithography Equipment Resistors in photoresist pattern Resistors after etching Stepper (AMS Lithography) Wave length, nm NA Resolution, nm K ,60 0, ,58 0, ,57 0, ,57 0, ,75 0, ,39 0,35 The main characteristics of up to date steppers

54 PACKAGING Overview