Dependable VLSI Platform Using Robust Fabrics

Transcription

1 Dependable VLSI Platform Using Robust Fabrics Hidetoshi Onodera, T. Sato, A. Tsuchiya (Kyoto Univ.) T. Onoye, M. Hashimoto, Y. Mitsuyama (Osaka Univ.) H. Ochi (Kyoto U.), K. Kobayashi (KIT), H. Shimada (NAIST), H. Kanbara (ASTEM)

2 Outline Background: Challenges to be Resolved Project Overview Current Activities Robust Fabric Reconfigurable Architecture, Mapping Reconfigurable Processor, Application Summary/Project Status

3 Background: challenges to be resolved Manufacturability loss Soft errors Variability source: Synopsys Reliability loss source: Sanyo NBTI LER, RDF courtesy: Prof. Asenov Source: Semiconductor International, ΔTd ~ 10%@10Ys

4 Background: challenges to be resolved NRE-cost explosion Source: Semiconductor International, Required level of dependability/reliability widely differs application-by-application Satellite, aerospace, automotive, banking,, Gaming,,,

5 Project Overview Background Loss of dependability due to physical/natural faults (Manufacturability loss, Variability, Soft errors, Reliability loss, etc.) NRE-cost explosion Wide spectrum of dependability Reconfigurable VLSI Platform for Flexible Dependability Collaborative Researches for Layout/Circuit/Architecture/Mapping Layout: Robust structure Circuit: Adaptive performance tuning Architecture: Adaptive redundancy Mapping: Dependability-aware mapping

6 Dependable VLSI Platform using Robust Fabrics Reconfigurable Architecture Parallel Processing Spatial Redundancy Temporal Redundancy Mapping Dependability -awareness Reconf. 自己修復制御 Processor CPU for Sequential Processing Self-Repair by hot swap Dependable VLSI with reconfigurable structure using Robust (variation-tolerant and manufacturability-enhanced) fabric array Robust Fabric Self-Test Self-Adjust Application

7 Cross-Disciplinary Collaborative Research Limiting factor of Dependability Manuf. Loss Variabi lity Soft Error Aging Software Key technologies DFM 製造容易構造 structure Adaptive Redund 適応的 ancy 冗長化自己調整 Self tuning Self 自 Rep 己 air 修復 Reconf. Processor Mapping Reconfigurable Architecture Robust Fabric Device

8 Our Team Robust Fabric DFM &Variation-tolerant Fabrics H. Onodera, T. Sato, A. Tsuchiya Reconfigurable Architecture Flexible Dependability with Hot Swap T. Onoye, M. Hashimoto, Y. Mitsuyama Mapping Dependability-aware mapping H. Ochi Reconfigurable Processor Reliability-aware Processor K. Kobayashi, H. Shimada Application Evaluation/Application H. Kanbara

9 Outline Background: Challenges to be Resolved Project Overview Current Activities Robust Fabric Reconfigurable Architecture, Mapping Reconfigurable Processor, Application Summary/Project Status

10 Robust Fabric Target Manufacturability-enhanced and Variation-tolerant Fabrics (Logic/Memory/Interconnect) BIST and Self-tuning of Fabric Performance Current Activities Variability Characterization Gate-level Delay Variability Analysis (WID Variability Decomposition) Chip-level Variability Analysis DFM & Variation-tolerant Design Manufacturability vs. Overhead trade-off analysis of Regularity-enhanced Layout DFM-aware Library(180nm) for academic use

11 decoder selector controller Variability Characterization RO-array Test Structure for Variability Characterization out enable Ring Osc. 68μm 22 ROs 40μm Section... 15x15 Sections... 15x15 Sections 1.3mm Variability TEG 1.2mm Freq[MHz] WID Variability nm 90 nm 65 nm Ref: IEDM2008, pp , ASICON2009 D2D Variability (Wafer Map)

12 Decomposition of WID Variability (90nm) Freq[MHz] Freq[MHz] stage INV RO Measured data (σ/μ=1.6%) Systematic (σ/μ=0.01%) Freq[MHz] Freq[MHz] Deterministic (σ/μ=0.68%) Random (σ/μ=1.36%)

13 Variability Breakdown for 7-stage INV ROs Component Standard Deviation σ/μ [%] 180nm 90nm 65nm D2D 4.6* * WID Deterministic Systematic Random Single Gate * Obtained from 20 chips. Locations on the wafer are not known.

14 DFM by Regularity-Enhancement: 45nm D-FF Lithography Simulation 2.5 Compact (Area:1) Standard Deviation [nm] Compact 2D_regular 1D_regular Hot Spot Hot Spot 2D_regular (Area:1.08) 1D_regular (Area: 1.08) Defocus [nm] Standard deviation of gate-length variation under defocus Compact is vulnerable to defucus Regularity enhances robustness

15 Built-in Self Measurement and Performance Tuning Performance Monitor by Process-Parameter Sensitive RO Performance Tuning (-20% %) by Substrate Biasing. 65nm example Vth (normalized): PCM vs. Estimated PCM Estimated nmos -1 to to pmos -1 to to 0.32 average frequency [MHz] measured (chip02 INV59) simulation (hspice) backgate bias[v]

16 Our Team Robust Fabric DFM &Variation-tolerant Fabrics H. Onodera, T. Sato, A. Tsuchiya Reconfigurable Architecture Flexible Dependability with Hot Swap T. Onoye, M. Hashimoto, Y. Mitsuyama Mapping Dependability-aware mapping H. Ochi Reconfigurable Processor Reliability-aware Processor K. Kobayashi, H. Shimada Application Evaluation/Application H. Kanbara

17 Reconfigurable Architecture Target Reconfigurable Architecture that enables Spatial/Temporal Redundancy and Hot Swap Run-time Recovery by Self-Repair Current Activities Coarse-Grained Cluster-cell Architecture Reliability analysis of 4 operation modes Chip design of ALU-cluster Architecture design of Register and Multiplier clusters Trade-off analysis: Reliability vs. Power/Performance Conventional architecture ALU fabric LUT fabric Dependable architecture TMR hot swap spare fabric memory fabric duplication

18 Objective Develop a coarse-grained dynamically reconfigurable architecture with flexible reliability JPEG MPEG H.264 Mapping CTRL I/O Datapath High reliability configuration Intermediate reliability configuration Low reliability configuration Reliability level is individually selectable for each basic element. Selective redundant configuration is possible for reducing area overhead while satisfying reliability requirement.

19 Classification of Required Reliability Sensitivity to Soft errors Errors in : permanent. Errors in EM : temporary. Consideration of four cases 1. Functionality must be correct, and computed data must be correct as well. Configuration information memory Data in Execution module Data out 2. Functionality must be correct, and errors in computed data can be detected, however some of them can be corrected. 3. Functionality must be correct, and errors in computed data are not considered. 4. No consideration for error recovery and detection is necessary. 4 Operation modes EM Basic element structure 1 TMR (Triple modular redundancy) 2 DMR (Double modular redundancy) 3 SMS (Single modular with single context) 4 SMM (Single modular with multi-context)

20 Proposed Architecture Cluster Placed in 2-D array Connects with next clusters via tracks Contains 4 cells; reconfigurable unit (RCU), redundancy control unit (RDU), and comparing & voting unit (CVU). Contains 3 configuration memories (), voters (), an execution module (EM) and a selector (a part of SM) Execution/Register Module Different for each cluster RDU Cluster array Inputs from four cell - SM Cluster EM/RM EM/RM EM/RM EM/RM CVU Outputs to four cell RCU I/O I/O I/O I/O I/O I/O I/O I/O Track0 Track1 Track2 Track3 Cluster interconnect I/O I/O Track3 Track2 Track1 Track0 EM/RM architecture depends on cluster type (3 types) ALU cluster Multiplier cluster Register cluster Ref: SELSE2009

21 Four Operation Modes [Context0] [Context1] [Context2] [Context0] High reliability High Area-efficiency CS [Context0] [Context0] CS CS [Context1] [Context0] [Context1] [Context0] [Context1] (a) [Context2] TMR [Context2] (c) SMS Operatio n mode TMR DMR SMS SMM VD VD VD Output data Input data Parity check Input data EM/RM EM/RM EM/RM EM/RM Output data [Context0] [Context1] [Context2] Redundancy Reliability Utilization EM/RM SEU in [Context0] CS CS [Context1] CS CS CS CS (c) SMS (d) SMM (a) TMR (b) DMR Parity check SEU in EM/RM Input data EM/RM SET in EM/RM Input data : detect and recover : detect : cannot detect #contex t CS EM Input data EM/RM EM/RM EM (b) DMR Parity EM/RM Output check data C&S Output data Output data CS CS VD VD VD(d) SMM Parity check Output data Parity check Input data EM/RM #cells Input data EM EM C&S Output data

22 Mapping Architecture Design Support by Mapping and Simulation Fault model Feedback to Architecture Design Architecture Architecture Architecture Simulation Application Mapping Area Delay Power Dependability Soft error Aging Fault Dependability-aware Mapping

23 Mapping Viterbi Decoder Viterbi decoder uses the Viterbi Algorithm for decoding a bit stream that has been encoded using forward error correction. Calculate branch metric based on the humming distance Calculate path metric add and compare branch metrics Path memory memorize the paths with higher metric

24 Fault-Tolerant Evaluation Apply fault-tolerant evaluation Cycle-based simulation for counting the number of sensitive bits in memory for every cell. Sensitive bits are bits that have impact on the primary output when its value crashes. cells with more sensitivity bits require more reliability consideration. SEU configuration memory configure Error sensitive bit Input cell output Correct non-sensitive bit

25 Results of Mapping 790/12096 sensitivity bits 0 sensitivity bits The area overhead is about 3.9 times With mixed-mode mapping a considerable trade-off between reliability and area overhead can be achieved

26 Our Team Robust Fabric DFM &Variation-tolerant Fabrics H. Onodera, T. Sato, A. Tsuchiya Reconfigurable Architecture Flexible Dependability with Hot Swap T. Onoye, M. Hashimoto, Y. Mitsuyama Mapping Dependability-aware mapping H. Ochi Reconfigurable Processor Reliability-aware Processor K. Kobayashi, H. Shimada Application Evaluation/Application H. Kanbara

27 Reconfigurable Processor Target Reconfigurable Processor with Adaptable Redundancy on Dependable VLSI Platform Current Activities Multi-core pipe-lined processor with dynamic redundancy control Normal Operation: Single or DMR Permanent Fault: Fault-location Identified by TMR TMR Power DMR?? Off? DMR Single Power Off Power Off Power Off Single Power Off Power Off Power Off Single Normal Operation DMR for reliable operation, or single core execution for normal operation Power-off for sleep cores Fault Identified by TMR Fault-location identified by TMR Disabling Fault Core Separation of Identified Fault Core Single core hopping for aging

28 Application Target Specification and Evaluation of Reliability and Security Requirement Application of Dependable VLSI Platform Current Activities Embedded System IP development (Processor, Encryption) FPGA Board SRAM Spartan 3 Mem IF AES Encryption Block RAM Start-up Interrupt gdb stub SEL Arbiter 8bit SW KeyBoard(PS2) Mips Processor (R3000 equiv) Interrupt HW RS232C VGA 7Segment LED x 4

29 Outline Background: Challenges to be Resolved Project Overview Current Activities Robust Fabric Reconfigurable Architecture, Mapping Reconfigurable Processor, Application Summary/Project Status

30 Dependable VLSI Platform using Robust Fabrics Parallel Processing Spatial TMR Temporal TMR Mapping Self-Repair Control CPU for Sequential Processing Self-Repair by hot swap Self-Adjust Dependable VLSI with reconfigurable structure using Self-Test Robust (variation-tolerant and manufacturability-enhanced) fabric array Extreme scaling imposes enormous challenges on LSI design such as manufacturability degradation, variability increase, performance aging, and soft-error vulnerability. In order to overcome these difficulties, we investigate a reconfigurable VLSI platform that can realize dependable circuits with required reliability. The platform consists of variation-tolerant robust fabrics with self-repairing capability of deteriorated circuits. We will demonstrate that the platform can be applicable to various embedded systems ranging from satellite applications to consumer products with a wide variety of dependability.

31 Dependable VLSI Platform using Robust Fabrics Robust Fabric Reconfigurable Architecture Reconfigurable Processor Mapping Application Current Status Tradeoff analysis: regularity vs variability Variability Characterization Basic design of reconf. architecture for flexible dependability Architecture design of processor for flexible dependability Dependability-aware mapping Reliability simulation environment Embedded system IP User hearing Next Issue Robust Fabric Design Guideline Static/ Dynamic Dependability Requirement Definition Target Static/Dynamic Dependability Assurance/Allocation Dependable VLSI Platform using Robust Fabrics