s1 s2 d B (F/D.IR.RS1 == D/X.IR.RD) (F/D.IR.RS2 == D/X.IR.RD) (F/D.IR.RS1 == X/M.IR.RD) (F/D.IR.RS2 == X/M.IR.RD) = 1 = 1

Transcription

1 Hrwre Interlock Exmple: cycle Hrwre Interlock Exmple: cycle ile s s / / / t em / ile s s / / / t em / nop nop hzr hzr $,$,$ $,$,$ (/..R == /..R) (/..R == /..R) (/..R == /..R) (/..R == /..R) = (/..R == /..R) (/..R == /..R) (/..R == /..R) (/..R == /..R) = 00 niel J. orin from Roth 00 niel J. orin from Roth Hrwre Interlock Exmple: cycle ipeline Control Terminology ile s s / / / nop hzr t em / Hrwre interlock mneuver is clle stll or bubble echnism is clle stll logic rt of more generl pipeline control mechnism Controls vncement of insns through pipeline istinguishe from pipeline tpth control Controls tpth t ech stge ipeline control controls vncement of tpth control $,$,$ (/..R == /..R) (/..R == /..R) (/..R == /..R) (/..R == /..R) = 0 00 niel J. orin from Roth 00 niel J. orin from Roth

2 ipeline igrm with t Hzrs t hzr stll inicte with * tll propgtes to younger insns Hrwre Interlock erformnce me el rnch: 0%, lo: 0%, store: 0%, other: 0% $,$,$ sw $,($) * * Hrwre interlocks: sme s softwre interlocks 0% of insns require cycle stll (i.e., insertion of nop) % of insns require cycle stll (i.e., insertion of nops) This is not K (why?) $,$,$ sw $,($) * * CI = + 0.0* + 0.0* =. o, either CI stys t n #insns increses 0% (softwre) r, #insns stys t (reltive) n CI increses 0% (hrwre) me ifference nywy, we cn o better 00 niel J. orin from Roth 00 niel J. orin from Roth bserve ypssing ile s s / / / $,$,$ This sitution seems broken hs lrey re $ from regfile $,$,$ hsn t yet written $ to regfile ut funmentlly, everything is still K hsn t ctully use $ yet $,$,$ hs lrey compute $ t em / ile s s / / / t em $,$,$ / ypssing Reing vlue from n intermeite (μrchitecturl) source Not witing until it is vilble from primry source (Regile) Here, we re bypssing the register file lso clle forwring 00 niel J. orin from Roth 00 niel J. orin from Roth 0

3 ypssing LUin ypssing ile s s / / / t em / ile s s / / / t em / $,$,$ $,$,$ $,$,$ ht bout this combintion? nother bypss pth n U input irst one ws n bypss This one is bypss Cn lso bypss to LU input 00 niel J. orin from Roth 00 niel J. orin from Roth ypssing? ypss Logic ile t s s em / / / / ile s s / / / t em / sw $,0($) lw $,0($) oes bypssing mke sense? Not to the ress input (why not?) ut to the store t input, yes bypss Ech U hs its own, here it is for U LUin (/..R == /..R) mux select = 0 (/..R == /..R) mux select = Else mux select = 00 niel J. orin from Roth 00 niel J. orin from Roth

4 ypss n tll Logic Two seprte things tll logic controls pipeline registers ypss logic controls muxes ut complementry or given t hzr: if cn t bypss, must stll lie # shows full bypssing: ll bypsses possible Is stll logic still necessry? Yes, Lo utput to LU Input ile t s s em / / / / nop stll $,$,$ $,$,$ lw $,0($) lw $,0($) tll = (/.. == L) && ((/..R == /..R) ((/..R == /..R) && (/..!= TRE)) 00 niel J. orin from Roth 00 niel J. orin from Roth ipeline igrm ith ypssing $,$,$ i $,$, ometimes you will see it like this enotes tht stll logic implemente t stge, rther thn Equivlent, oesn t mtter when you stll s long s you o $,$,$ i $,$, * * ipelining n ulti-cycle pertions ile s s / / / ht if you wnte to multi-cycle opertion? E.g., -cycle multiply /: seprte output ltch connects to stge Controlle by pipeline control n multiplier ctrl / t em 00 niel J. orin from Roth 00 niel J. orin from Roth

5 ipeline ultiplier ht bout tll Logic? ile s s / / / t em ile s s / / / t em /0 0/ / / ultiplier itself is often pipeline: wht oes this men? rouct/multiplicn register/lus/ltches replicte Cn strt ifferent multiply opertions in consecutive cycles /0 0/ / / tll = (ltlllogic) (/..R == /0..R) (/..R == /0..R) (/..R == 0/..R) (/..R == 0/..R) (/..R == /..R) (/..R == /..R) 00 niel J. orin from Roth 00 niel J. orin from Roth 0 ctully, It s omewht Nstier Honestly, It s Even Nstier Thn Tht ile s s / / / t em ile s s / / / t em /0 0/ / / ht oes this o? Hint: think bout structurl hzrs tll = (ltlllogic) (/..R!= null && 0/..R!= null) /0 0/ / / n wht bout this? tll = (ltlllogic) (/..R == /0..R) (/..R == 0/..R) 00 niel J. orin from Roth 00 niel J. orin from Roth

6 ipeline igrm with ultiplier ore ultiplier Nsties mul $,$,$ i $,$, 0 * * * This is the sitution tht slie # logic tries to voi is-orere writes to the sme register Compiler thinks gets $ from i, ctully gets it from mul This is the sitution tht slie #0 logic tries to voi Two instructions trying to write Regile in sme cycle mul $,$,$ i $,$, $,$,$0 0 mul $,$,$ i $,$, $0,$,$ ulti-cycle opertions complicte pipeline logic They re not impossible, but they require more complexity 0 00 niel J. orin from Roth 00 niel J. orin from Roth