1. Be able to do System Level Designs by: 2. Become proficient in a hardware-description language (HDL)

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1 Ojetives CENG53 Digitl Sstem Design Digitl Mhine Design Overview 1. Be le to do Sstem Level Designs : Mstering design issues in ottom-up fshion nd Designing sstems for speifi pplitions in top-down methodolog reognizing the differenes etween: Behviorl nd Struturl pprohes Simultion nd Snthesis of digitl designs Controlpth nd Dtpth designs. 2. Beome profiient in hrdwre-desription lnguge (HDL) to simulte nd to snthesize digitl designs. 3. Be fmilir with design utomtion tools to relize the ove ojetive 1 2 Speifition: Informl (English), Forml (C,, Verilog) Design Snthesis: Levels of Design Speifitions Sstem snthesis: Speifitions Arhiteture snthesis: Algorithms Sequentil snthesis: Finite-Stte Mh. Logi snthesis: Boolen expressions Tehnolog mpping: The logi ehvior Design Anlsis: proessors, memor, ASIC, registers, dders, gtes nd flip-flops gte level omponents trnsistor nd lout (CMOS, ) ensure tht design meets spes nd testle Sheduling Unit Binding Stte Minimiztion FSM Snthesis Tehnolog Mpping Ple nd Route Behviorl HDL Desription Register Trnsfer Level Gte Level Trnsistor/ Lout Level Prtitioning Hrdwre Allotion Optimiztion Logi Snthesis Trnsistor Optimiztion Interonnet Optimiztion 3 Digitl Mhine 1

2 Levels of Hrdwre Snthesis Rnge of Design Stles Custom Design Stndrd Cell Gte Arr/FPGA/CPLD Arhiteturl Level Logi Level Ciruit Level (i: 1..16) :: sum = sum*z 1 + oeff[i]*in*z 1 Arhiteture Snthesis stte Logi Snthesis t p x Ciruit Snthesis Custom Control Logi Custom ALU Custom Register File Gtes Stndrd ALU Stndrd Registers Gtes Routing Chnnel Gtes Routing Chnnel Gtes mem * fsm D x Performne Design Complexit (Design Time) Compt Longer wires 5 6 Sstem Definition Copright 1995, 1996 RASSP E&F Primril softwre Funtion Design HW & SW CODESIGN Rodmp RASSP DESIGN LIBRARIES AND DATABASE HW - SW Prtitioning VIRTUAL PROTOTYPE HW DESIGN SW DESIGN HW FAB SW CODE Primril hrdwre Integrtion & TEST Rpid Prototping of Applition Speifi Signl Proessors Progrm Hrdwre Desription Lnguge From struturl to ehviorl design: Flexiilit Reusilit Lrge nd omplex digitl sstems: Costl prototpes Anlsis nd simultion of hrdwre nd softwre Different models different designers: Inonsistenies etween different models Loss of informtion Different tools for different models Redesign of digitl sstems: > $10 illions / er 7 8 Digitl Mhine 2

3 Wh HDL? A unified environment Top-down trnsition in step-wise mnner An integrted nlsis nd design Performne, dependilit, nd funtionl modeling t ll levels Flexiilit to model digitl sstems t mn different levels of desription VHSIC (Ver High Speed Integrted Ciruit) Hrdwre Desription Lnguge IEEE : IEEE stndrd speifition lnguge for desriing digitl hrdwre used industr worldwide Enles hrdwre modeling from the gte to sstem level Provides mehnism for digitl design nd reusle design doumenttion 9 10 Histor 1983: A tem of Intermetris, IBM nd TI were wrded ontrt to develop 1985: The finl version of the lnguge under government ontrt ws relesed: Version 7.2 Design Exmple: Speifitions Design single it hlf dder with rr nd enle Inputs nd outputs re eh one it When enle is high, result gets x plus When enle is high, rr gets n rr of x plus 1987: eme IEEE Stndrd nd in 1988 n ANSI stndrd 1993: ws restndrdized to lrif nd enhne the lnguge Outputs re zero when enle input is low x enle sum rr Digitl Mhine 3

4 Exmple: Entit Delrtion Exmple: Behviorl Speifition First step, the entit delrtion desries the interfe of the omponent input nd output ports. Desrie the funtion of the dder tht n e simulted to verif orret funtionlit of the omponent ENTITY hlf_dder IS PORT(x,, enle: IN BIT; rr, sum: OUT BIT); END hlf_dder; x sum rr enle ARCHITECTURE hlf_dder_ OF hlf_dder IS PROCESS (x,, enle) IF enle = 1 THEN result <= x XOR ; rr <= x AND ; ELSE rr <= 0 ; result <= 0 ; END IF; END PROCESS; END hlf_dder_; 13 1 Exmple: Dt Flow Speifition Use logi equtions to develop dt flow desription tht n e simulted t this level to onfirm the logi equtions Exmple: Struturl Speifition from predesried omponents (lirr) ARCHITECTURE hlf_dder_ OF hlf_dder IS COMPONENT nd2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT nd3 PORT (in0, in1, in2 : IN BIT; out0 : OUT BIT); END COMPONENT; ARCHITECTURE hlf_dder_ OF hlf_dder IS rr <= enle AND (x AND ); result <= enle AND (x XOR ); END hlf_dder_; COMPONENT xor2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; FOR ALL : nd2 USE ENTITY gte_li.nd2_nt(nd2_); FOR ALL : nd3 USE ENTITY gte_li.nd3_nt(nd3_); FOR ALL : xor2 USE ENTITY gte_li.xor2_nt(xor2_); SIGNAL xor_res : BIT; -- internl signl A0 : nd2 PORT MAP (enle, xor_res, result); A1 : nd3 PORT MAP (x,, enle, rr); X0 : xor2 PORT MAP (x,, xor_res); END hlf_dder_; Digitl Mhine

5 Conurrent/Sequentil Sttements Exmples: Flip/Flops Comintionl Logi - Conurrent Sttements (Dtflow) Boolen Equtions (onurrent or sequentil); Logil Opertors; Reltionl Opertors; With-Selet-When (~Cse), When-Else (~ If-Then); Aggregte nd Contention, Don t Cre omprisons Rising edge triggered D flip-flop: q <= d WHEN (lk EVENT AND lk = 1 ) ELSE q; Comintionl Logi - Sequentil Sttements (Behviorl) Flling edge triggered D flip-flop: If-Then-Else (~ When-Else), Cse-When (~ With-Selet); Implied Lth Sequentil Logi (onurrent or sequentil) Cloking, Wit-Until, Rising_edge(); Reset/Preset, Asn/Sn; Registers; Arithmeti Opertors, Counters; Three-Stte Buffers, Bidiretionl Buses; For-Generte; For Loop, While Loop, Next, Exit q <= d WHEN (lk EVENT AND lk = 0 ) ELSE q; Pulse triggered D lth: q <= d WHEN (lk = 1 ) ELSE q; Rising edge triggered T flip-flop: q <= NOT q WHEN (lk EVENT AND lk = 1 ) ELSE q; An exmple: Adder Bsis Entit - Arhiteture Struture Entit Delrtions (Ports) Stles Effets of Stle on Snthesis Modeling for Simultion Timing Conepts Resolution Funtions Dt Ojets Identifiers, Tpes, Attriutes Exmple Digitl Mhine 5

6 Exmple Code Model it, 2-to-1 Multiplexer 2 ENTITY mmux1 IS 3 PORT (,: IN it_vetor(3 DOWNTO 0); --inputs sel: IN it; 5 : OUT it_vetor(3 DOWNTO 0)); --output 6 END mmux1; 7 8 ARCHITECTURE ehvior OF mmux1 IS 9 10 mux: PROCESS (,,sel) IF sel = 0 THEN <= ; 13 ELSE <= ; 1 END IF; 15 END PROCESS mux; 16 END ehvior; sel Smol 21 Entit Entit Delrtion (Interfe) (Funtion) 22 Devie Model Ports- externl onnetion points tht hve lss, tpe, nd mode Single-proess Entit: <= ( AND ) OR (NOT ) Entit- olletion of onurrent proesses tht desrie the funtion Multiple-proess Entit: Entit Delrtion Entit Delrtion defines externl interfe to this entit or devie omes efore the rhiteture setion Bsi entit sntx: t1 <= AND t2 <= NOT t1 t2 <= t1 OR t2 ENTITY entit_nme IS PORT (port1, port2: MODE TYPE; port3, port: MODE TYPE; port5: MODE TYPE); END entit_nme; 23 2 Digitl Mhine 6

7 Ports Port Delrtion is primr ontent of the Entit Delrtion Eh port represents either externl pin(s) of the devie, or wire(s) onneting two or more entities within omplete devie Eh port hs Port nme (identifier ou rete) Mode (diretion) Port Tpes Ports re lws signls (others: vriles, onstnts, files) Tpes useful for snthesis nd simultion it, it_vetor std_logi, std_logi_vetor oolen integer Tpe (kind of vlues possile) ENTITY entit_nme IS PORT (port1, port2: MODE TYPE; port3, port: MODE TYPE; port5: MODE TYPE); END entit_nme; Tpes onl useful for simultion rel time defines the funtion of the entit follows the entit delrtion Bsi rhiteture sntx: Levels of strtion ( stles) ehviorl dtflow struturl ARCHITECTURE rh_nme OF entit_nme IS CONCURRENT_STATEMENT1; CONCURRENT_STATEMENT2; END rh_nme ; An rhiteture m e written entirel in one stle, or in mixture of stles (more ommon) Vrious stles llow designer to desrie the funtion of devie in the simplest or most nturl form Digitl Mhine 7

8 1- Behviorl Stle 1- Behviorl Stle High-level, Algorithmi Es to write nd understnd Proess with sequentil sttements - order is importnt! Exeutes in zero simultion time ARCHITECTURE ehvior OF mmux1 IS mux: PROCESS (,,sel) IF sel = 0 THEN <= ; ELSE <= ; END IF; END PROCESS mux; END ehvior; Another ehviorl desription of sme devie ARCHITECTURE ehvior2 OF mmux1 IS PROCESS (,,sel) <= ; IF sel = 1 THEN <= ; END IF; END PROCESS; END ehvior2; Dtflow Stle 2- Dtflow Stle RTL (Register Trnsfer Lnguge) stle M e hrder to write nd understnd Multiple onurrent signl ssignment sttements Exeutes in non-zero simultion time ARCHITECTURE dtflow OF mmux1 IS <= WHEN (sel = 0 ) ELSE ; END dtflow ; Another dtflow desription of sme devie Conurrent sttements - order is irrelevnt ARCHITECTURE oolen_dtflow OF mmux1 IS (3) <= ((3) AND NOT sel) OR ((3) AND sel); (2) <= ((2) AND NOT sel) OR ((2) AND sel); (1) <= ((1) AND NOT sel) OR ((1) AND sel); (0) <= ((0) AND NOT sel) OR ((0) AND sel); END oolen_ dtflow ; Digitl Mhine 8

9 3- Struturl Stle Low-level, netlist - omponent instntitions nd wiring Essentill the text version of shemti Hierrhil Uses pkge of pre-defined lower-level omponents M e hrd to write nd understnd (ver detiled nd low level) No Proess or onurrent signl ssignment sttements 3- Struturl Stle USE work.gtes_pkg.ll; ARCHITECTURE struturl OF mmux1 IS SIGNAL t, t: it_vetor (3 downto 0); SIGNAL seln: it; u0: nd2 PORT MAP ((3),seln, t(3)); u1: nd2 PORT MAP ((2),seln, t(2)); u2: nd2 PORT MAP ((1),seln, t(1)); u3: nd2 PORT MAP ((0),seln, t(0)); u: nd2 PORT MAP ((3),sel, t(3)); u5: nd2 PORT MAP ((2),sel, t(2)); u6: nd2 PORT MAP ((1),sel, t(1)); u7: nd2 PORT MAP ((0),sel, t(0)); u8: or2 PORT MAP (t(3), t(3), (3)); u9: or2 PORT MAP (t(2), t(2), (2)); u10: or2 PORT MAP (t(1), t(1), (1)); u11: or2 PORT MAP (t(0), t(0), (0)); u12: not PORT MAP (sel, seln); END struturl; 33 3 Digitl Mhine 9