c s ha2 c s Half Adder Figure 2: Full Adder Block Diagram

Transcription

1 Adder Tk: Implement 2-it dder uing 1-it full dder nd 1-it hlf dder omponent (Figure 1) tht re onneted together in top-level module. Derie oth omponent in VHDL. Prepre two implementtion where VHDL omponent re intntited in: VHDL top-level file Blok Deign top-level file Simulte nd implement eh projet on FPGA development ord. A0 B0 A1 B1 Hlf Adder Full Adder CARRY Figure 1: 2-it Adder SUM0 SUM1 CARRY Struturl deign The ytem n e repreented olletion of omponent nd their interonnetion uing truturl deign pproh. In thi wy the hrdwre i deried hemti or netlit, where internl truture of the interonneted omponent i hidden. The omponent n e either regulr truture (like logi gte, dder, omprtor, regiter, et.) or previouly defined oure, whih re ued within nother higher level deign to rete hierrhy. rry in h1 Hlf Adder h2 Hlf Adder h3 Hlf Adder rry um Figure 2: Full Adder Blok Digrm A imple 1-it full dder iruit h three input nd two output. It n e uilt from three

2 hlf dder hown in Figure 2. Note tht the rry output of the h3 hlf dder i left floting, it would lwy equl to 0 (other hlf dder nnot hve their rry output equl to 1 oth t the me time). Struturl deign uing VHDL In order to ontrut the full dder in Figure 2 uing VHDL, the truturl deription tyle n e ued. The hlf dder deign n e ued omponent, thu effetively reting textul deription of hemti in Figure 2. Component i piee of onventionl VHDL ode, whih n e ued within nother deription. Thi llow to prtition, hre nd reue VHDL ode. The hlf dder omponent hould e deigned firt (refer to the exmple in the Comprtor l ppendix). One the hlf dder h een deried, it n e ued to form full dder deign y delring it omponent in the delrtive prt of the full dder rhiteture (efore egin keyword). The omponent delrtion i very imilr to entity delrtion with keyword entity utituted for keyword omponent (Liting 1). Liting 1: VHDL Delrtion of Component Hlf Adder omponent hlf_dder i port (, : in td_logi; um, rry: out td_logi); end omponent; The next tep i to intntite omponent in the rhiteture ody. Component intntition trt with lel, followed y omponent nme. The lel i required to differentite etween multiple intne of the me omponent. The finl omponent intntition prt i mpping of omponent input/output to the port nd ignl of the higher level deription. The mpping n e done in two wy hown in Liting 2. The nmed oition mp eh input/output of the omponent (to the left of => opertor) to orreponding ignl (to the right of => opertor) of the higher level deription. Note, tht the order, in whih the port re eing mpped, doe not orrepond

3 to the order in omponent delrtion. Thi i due to the ft tht oition i eing tted expliitly. On the other hnd, in the poitionl oition the ignl re ordered extly in omponent delrtion. Thi in turn llow to omit the => opertor. Liting 2: ) Poitionl nd ) Nmed Aoition of Component Hlf Adder h1: hlf_dder port mp (h1_, h1_, h1_um, h1_rry); h1: hlf_dder port mp ( => h1_, um => h1_um, => h1_, rry => h1_rry); ) ) Liting 3 how three intntition of hlf_dder omponent (ll three uing poitionl oition for port mpping), whih form the full dder hown in Figure 2. Note, tht the order of omponent i not importnt, ine they re working onurrently (in prllel). The hemti, whih n e reontruted from thi truturl VHDL deription, hould e identil to the one in Figure 2. Liting 3: Struturl Deription of Full Adder h3: hlf_dder port mp (_, _, rry, open); h1: hlf_dder port mp (,, _, _); h2: hlf_dder port mp (_, rry_in, um, _); Note, tht in order to form internl onnetion etween omponent, three dditionl ignl mut e delred: _, _, _. The onnetion i reted y mpping the me ignl (e.g., _) to output port for one omponent (h1) nd to input for the other omponent (h3). Thi ignl n e viewed orreponding wire from full dder hemti in Figure 2. The floting rry output of the h3 hlf dder i peified with the keyword open. Struturl deign uing Vivdo Blok Deign Similrly the full dder in Figure 2 n e reted uing Vivdo Blok Deign. The VHDL deription of hlf dder n e pkged into IP nd intntited from the lit of IP (refer to the Vivdo Tutoril in Ueful Link nd Mteril on the l we pge). However,

4 for uh trivil deign IP genertion my not e needed. A n lterntive, VHDL oure file n e dded to the lok deign n RTL module. Selet Crete Blok Deign option in the Flow Nvigtor under IP Integrtor flow etion, provide Deign nme nd lik OK to rete new Blok deign oure file. Right-lik on n empty pe in the lok deign nd elet Add Module option. Highlight hlf dder deign nd lik OK to ple it in the lok deign. Add two more hlf dder nd onnet them. For eh port tht hould e onneted to the pin of the FPGA (e.g. A nd B of HA_2), right-lik on the port nd elet Mke Externl option. Thi will rete n Externl Port nd onnet it to the eleted port of RTL Module. Alo, it i poile to right-lik on the RTL Module itelf nd elet Mke Externl option to rete Externl Port for ll unonneted port of tht RTL Module. The Externl Port nme n e hnged in the Externl Port Propertie. The end reult hould look imilr to the one hown in Figure 3. Note tht rry output of the hlf dder HA_0 i left floting. The logi oited with tht output (AND gte) will e utomtilly removed during implementtion phe. Figure 3: Full Adder Blok Deign When the lok deign i redy, it hould e et the top oure file of the projet. However, it i not poile to et lok deign top oure file diretly. Right-lik lok deign oure file in the Soure window under Deign Soure tegory in the Projet Mnger flow etion lyout. Selet Crete HDL Wrpper option nd lik OK. Leve the defult Let Vivdo mnge wrpper nd uto-updte option o tht in e ny hnge re mde to the lok deign, the wrpper would updte utomtilly. When HDL wrpper i reted for the lok deign, it n now e et the top oure file. Thi i done

5 utomtilly y the tool, however, if thi i not the e (or in order to et different oure file top), right-lik the wrpper nd elet Set Top option. From thi point the deign flow eome identil to VHDL-ed deign flow.