Power-Optimal Pipelining in Deep Submicron Technology Λ

Transcription

1 8. Power-Optimal Pipelining in Deep Submicron Technology Λ Seongmoo Heo and Krste Asanović MIT Computer Science and Artificial Intelligence Laboratory Vassar Street, Cambridge, MA 9 fheomoo,krsteg@csail.mit.edu ABSTRACT This paper explores the effectiveness of pipelining as a power saving tool, where the reduction in logic depth per stage is used to reduce supply voltage at a fixed clock frequency. We examine poweroptimal pipelining in deep submicron technology, both analytically and by simulation. Simulation uses a nm predictive process with a fanout-of-four ierter chain model including input/output flipflops, and results are shown to match theory well. The simulation results show that power-optimal logic depth is to 8 FO and optimal power saving varies from to 8% compared to a FO logic depth, depending on threshold voltage,, and presence of clock-gating. We decompose the power consumption of a circuit into three components, switching power, leakage power, and idle power, and present the following insights into power-optimal pipelining. First, power-optimal logic depth decreases and s increase for larger s, where switching power dominates over leakage and idle power. Second, pipelining is more effective with lower threshold voltages at high s, but higher threshold voltages give better results at lower s where leakage current dominates. Lastly, clock-gating enables deeper pipelining and more power saving because it reduces timing element overhead when the is low. Categories and Subject Descriptors: B.. [Integrated Circuits]: Types and Design Styles Advanced Technologies, Microprocessors and Microcomputers, VLSI General Terms:Performance, Design, Theory Keywords:Pipelining, Supply Voltage Reduction, Power Scaling. INTRODUCTION Pipelining reduces the number of logic levels between registers and is usually employed by digital systems designers to increase achievable clock frequency. But the time slack obtained from pipelining can also be used to reduce power consumption by low- Λ This work was partly funded by NSF CAREER award CCR- 9, NSF ITR award CCR-9, and a donation from Intel Corporation. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ISLPED, August 9,, Newport Beach, California, USA. Copyright ACM //8...$.. ering supply voltage at a fixed clock frequency. This technique can be very effective for digital systems with fixed throughput requirements and highly parallel computations. Supply voltage scaling is by far one of the most effective techniques for trading time slack for power. Supply voltage reduction leads to a quadratic reduction in active power and also a super-linear reduction in leakage power, as leakage current has a strong dependency on drain voltage in deep submicron processes. A parallel architecture could also be used to provide excess performance to trade for lower power, but pipelining has the advantage of a lower area penalty. Power reductions from pipelining are eventually limited by the power overhead of the additional pipeline latches or flip-flops required for each additional pipe stage, leading to a power-optimal level of pipelining. In this paper, we show how power-optimal pipelining varies for different operating regimes in deep submicron technology. We examine the tradeoffs between pipeline depth, supply voltage, threshold voltage, and total power using circuit-level simulations and analytical models. We also explore the effect of and clock gating.. RELATED WORK The trend towards deeper pipelines in microprocessors is clearly seen in the evolution of Intel x8 family, with a factor of reduction in logic depth per stage over the last decade [9]. This reduction in logic depth has combined with improvements in transistor speed from technology scaling to yield an even larger increase in processor clock frequency. Increasing the number of pipeline stages for an operation increases its latency in clock cycles, which in turn increases the number of pipeline stalls experienced by dependent operations. The resulting reduction in instructions completed per cycle (IPC) reduces the performance advantage from greater clock frequency, with greater impact on codes with lower instructionlevel parallelism (ILP). Processor architects have explored this tradeoff between increased clock frequency and reduced IPC to determine performance-optimal pipelining depth. Early work by Kunkel and Smith [] considered pipelining in vector supercomputers and found that 8 ECL gate levels was performance-optimal for scalar code, and as little as gate levels for more parallel vector code. Recently, several authors have iestigated the performanceoptimal pipeline depth for superscalar microprocessors [, 9, ], with a consensus in the range of 8 FO delays for SPEC integer codes and around FO delays for SPEC floating-point codes, which generally have higher ILP. These performance-optimal numbers ignore power as well as the design and verification complexity that would accompany such high-frequency designs (roughly twice the clock rate of existing systems []). Several authors have extended superscalar performance mod- 8

2 els with power models that include the power overhead of additional pipeline latches [, ]. Srinivasan et al. [] found that power-performance optimal logic depth increases to about 8 FO for SPEC benchmarks and around 8 FO for TPC-C, a commercial application. Hartstein and Puzak [] found. FO is the power-performance optimum according to their powerperformance metric. They also found that clock gating pushes the optimum back to deeper pipelines [] which agrees with our results. This previous work focuses on processor performance, where limited instruction parallelism reduces the benefits of deep pipelines, and these studies limit power optimization to the selection of the correct number of additional pipeline stages. Other types of digital system, including digital signal processors, network processors, and graphics engines, have much greater levels of parallelism and often have fixed throughput requirements. For these systems, pipelining can be used together with voltage and threshold scaling to reduce total energy consumption while maintaining a fixed clock rate. The use of pipelining for power reduction was proposed by Chandrakasan et al.[] but without an attempt to determine the power-optimal pipelining strategy.. METHODOLOGY In this paper, our main target is a logic-dominant pipeline stage. We make several simplifying assumptions in our analysis. We are interested in fixed-throughput designs for highly parallel computations and so do not include any performance loss from an increased frequency of pipeline stalls as pipeline depths increase. Global wire delay does not scale as fast as gate delay as feature size is reduced, and some modern microprocessors have so-called drive stages which include only wires and repeaters [8]. We leave wire-dominant pipeline stages for future work but note that wire RC delay become relatively less important as supply voltage is scaled down in a fixed technology, because wire resistance remains constant while effective transistor resistance increases. We do not include local wire capacitance due to the absence of detailed circuit layouts, but note that wire cap can be an important component of total load in deep submicron technology even for a logic-dominant stage. INPUT stages OUTPUT Figure shows the baseline pipeline stage model assumed in our study. To model a well-designed path in a circuit, we use a simple static ierter chain with each ierter driving four copies of itself to yield a FO load. We use FO delays as a baseline clock period, representing a current high-performance processor circuit (the high-frequency Pentium- has a FO cycle time [], and most other designs have somewhat shallower pipelines). Even though different circuit styles and logic gates might lead to different power-optimal pipelining results, we assume that our FO ierter chain model is fairly representative and insights gathered from our simulation results can be applied to other cases. Flipflops were chosen as the timing elements rather than latches due to their simplicity of usage, and the PowerPC transmission-gate flipflop was chosen because it is a popular choice due to its robustness and energy-efficiency []. While the transistor sizes of ierters and flip-flops were fixed, the sizes of clock buffers were varied to ensure the appropriate clock rise and fall times when varying the depth of pipelining. We used the BPTM nm transistor models with different threshold voltages [] and HSPICE for circuit simulation. Throughout the paper, clock frequency was fixed at GHz and temperature was constant at o C. We only considered subthreshold leakage; although gate leakage might become significant at some point in these technology generations, it is also likely that new gate dielectrics will make gate leakage insignificant again.. PIPELINING AND SUPPLY VOLTAGE We begin by showing the effect of pipeline depth on supply voltage. With delay fixed, supply voltage scales down as pipelining deepens because the logic amount per pipeline stage decreases. Synchronous circuit delay is approximately given by delay / (N + k) V dd (V dd V th ) ff () where N is the logic depth per pipeline stage in term of FO delay (or the ierters per pipeline stage), k is the timing element delay normalized by FO delay, ff is a velocity saturation effect factor, V dd and V th are supply and threshold voltages respectively. Assuming ff is (actual value of ff in deep submicron technology is close to. due to the short-channel effect), N + k / V dd V th + V th V dd () Now assuming V th V dd is close to zero, we get a simple linear equation between V dd and N, wherea is a constant: V dd = a N + a () ( a = k + V th ) () a a Figure shows the simulated supply voltages when varying the ierters per stage for different threshold voltages. LV T, MV T, andhv T represent low, medium, and high threshold voltages respectively and their values are shown in Table. Low threshold voltage results in low supply voltage for the same delay. a and a were calculated using least square method and shown in Table. We can see that a is proportional to V th as well as a (our simplified equations fail to explain the effect). Figure : Baseline pipeline stage model. Input and clock buffers are not shown..9.8 Vdd (V) Figure : Supply voltage scaling shown as voltage required to achieve GHz with given logic levels per pipeline stage. 9

3 V th (V) NMOS(PMOS) name a a. (-.)...9 (-.)..9. (-.).8.89 Table : Threshold voltages and supply voltage scaling coefficients.. PIPELINING POWER COMPONENTS In this section, we explore the impact of pipelining on the components of total power consumption when delay is fixed. We use the supply voltage scaling results shown above in Section and iestigate switching, leakage, and idle components of power consumption assuming no clock-gating mechanism.. Pipelining and Switching Power Switching power remains the dominant component of total power consumption when the is high, even in leaky deep submicron technology. Switching power is the power consumed while charging and discharging load capacitances. The load capacitances include transistor parasitic and wire capacitances. Because we assume our pipeline stage is logic-dominant, wire capacitances are not included in our simulation. The switching power of a pipelined logic stage can be divided between that due to logic gates and that due to timing elements, and can be modeled as: P switching = (b + b N )V dd () = b a( + b a )(N + ) () b N a The overhead includes clock and switching power of timing elements and it is iersely proportional to, N, the number of logic gates per stage. We assume that the number of latches increases linearly with the number of pipeline stages. All the switching power components are proportional to Vdd. The ratio of switching power coefficients b b is approximately the ratio of the parasitic capacitances of one FO ierter and one timing element. When N is much greater than a a and b b, P switching becomes quadratic to N as shown in Eq., which represents the dominance of logic gate switching power. P switching ß b a N () On the other hand, if N gets much smaller than a a and b b, P switching becomes iersely proportional to N, as shown in Eq. 8, which represents the dominance of timing element switching power: P switching ß b a N Note that the (N + a a ) term in Eq. makes relative P switching scaledownslowlywhen a a is large. Since a higher V th process has a higher a a, as shown in Table, a higher V th process gets less switching power saving from pipelining. The optimal logic depth N Λ is given by: s N Λ = ( b b (8) +8 a a b b b b ) (9) The equation indicates that the capacitance ratio of a timing element and an FO ierter b b is positively correlated to N Λ.Thatis, larger timing element parasitics lead to less deep pipelining. However, N Λ is not as sensitive to b b as it is to a a. This means that V th and timing element delay k affect N Λ and correspondingly optimal power saving more significantly (Eq. ) Figure : Switching power scaling. Figure shows the switching power obtained through HSPICE simulation of our model pipeline stage. Optimal logic depth N Λ was and was from 9 to 8% compared to the baseline of N =. The graphs show that lower threshold voltages gives slightly lower optimal logic depth and also slightly greater switching power saving. The variances are quite small since the variance of a a is small.. Pipelining and Leakage Power The rapid reduction in gate length and accompanying downscaling of threshold voltages over the last few process generations has led to an exponential growth in leakage power. Within a few process generations, it is predicted power dissipation from static leakage current could be comparable to dynamic switching energy [, ]. The leakage power of our pipelined circuit can be given by the following equations: P leak =(c + c + V dd N )V dd e T () a c a (N+ a = c a e T ( + )(N + ) e T a ) () c N a where T is a constant representing leakage current slope, is a Drain-Induced-Barrier-Lowering (DIBL) coefficient, and c c is the ratio of leakage power of one FO ierter versus one timing element. As in the switching power model, the leakage power in a stage can be divided into logic gate leakage and timing element leakage, with timing element leakage iersely proportional to N. When N is much greater than a a and c c, P leak becomes proportional to the product of N and the exponential term e N T a : P leak a N ß c a e T Ne T a (N+ a T () a The exponential term, e ) represents the dependence of leakage current on the drain voltage (from DIBL). In modern deep submicron technology, for an appropriate supply voltage range, this term is larger than O() but smaller than O(N ), therefore leakage power is reduced in a super-linear fashion as N decreases, though less than the quadratic reduction for switching power. Also, it is noted that the exponential term scales down faster as N decreases when a is larger. A higher V th process has higher a as shown in Table, and so it is expected that higher V th process will see greater leakage power saving from pipelining, which is the

4 opposite to the switching power case, but higher V th processes have less absolute leakage to begin with. On the other hand, if N becomes much smaller than a a and c c, P leak becomes iersely proportional to N just as in the P switching case: P leak ß c a e T N e T () Figure shows the simulated leakage power while varying the number of logic gates per stage. Optimal logic depth N Λ was around six and was around %. The graphs show that lower threshold voltages gives less leakage power saving and slightly greater optimal logic depth a.. Figure : Leakage power versus logic depth per stage.. Idle Power without Clock-Gating Clock-gating is a popular switching power reduction technique which inactivates the clock signal to timing elements within an inactive block when a circuit block is idle. But clock gating is not always possible due to the increase control complexity or the insufficient setup time of the clock enable signal. This section focuses on the impact of pipelining on an idle pipeline stage without clockgating. The following section discusses the effects of clock-gating. The following equations model idle power with no clock-gating mechanism as simply the sum of the switching power of the timing elements and the total leakage power. Because of the exponential dependency of leakage current on V th as represented in the e T term, P idle approximately follows the switching power of the timing elements when V th is high and follows the total leakage power when V th is low. P idle = b N V dd +(c + c + V dd N )V dde T () P idle = b a a (N + N ) + () a c a e T ( + c a a (N+ a )(N + )e T a () ) c N a When N is much greater than a a and c c, P idle becomes proportional to the product of N and the exponential function of N or just proportional to N, depending on V th : P idle (HighV th ) ß b a N () P idle (LowV th ) ß c a e T Ne a N T (8) When V th is high, P idle shows a linear reduction as N decreases, which is slower than a quadratic reduction as in switching power or a super-linear reduction as in leakage power. Thus, we can expect that idle power savings from pipelining are lower than those of switching and leakage power saving when V th is high. On the other hand, if N is much smaller than a a and c c, P idle becomes iersely proportional to N: P idle (HighV th ) ß b a N (9) P idle (LowV th ) ß c a e T N e T () Figure shows the simulated idle power without clock-gating, varying the ierters per pipeline stage. Optimal logic depth N Λ was 8, which is greater than the optimal logic depths for switching and leakage power. Also, was smaller ( to %) compared to the switching and leakage power cases. For idle stages, the overhead of timing elements is more significant compared to active stages. The graphs show that lower threshold voltages gives more idle power saving and slightly lower optimal logic depth Figure : Idle power scaling. a... RESULTS In this section, we combine the results for the individual power components to calculate optimal logic depths and optimal power savings for different operating regimes including threshold voltage,, and presence of clock-gating. Power-optimal pipelining varies depending on and V th because these change the proportion of switching power and leakage power (or idle power with no clock-gating mechanism), and each impacts pipelining power differently as seen in Section. This section is divided into two parts: the first part details the case when there is a clock-gating mechanism for pipeline stages and the second part considers the case without clock-gating.. Case : Clock-Gating Present Figure shows the simulated total power when a clock-gating mechanism is present for different s. With a low activity factor, total power curves follow leakage power curves and high V th leads to more power saving by pipelining. As the activity factor increases, total power curves follow switching power curves and high V th leads to less power saving by pipelining. Figure shows the simulated optimal total power saving when a clock-gating mechanism is present. With zero, optimal power savings compared to a FO design vary from

5 to % depending on V th. Since switching power savings from pipelining are less dependent upon V th, s reach around 8% regardless of V th as increases. Because both switching power and leakage power are minimized when N is as seen in Section. and Section., optimal logic depth was found to be regardless of or threshold voltage when a clock-gating mechanism is present. However, as seen in Figure and Figure, both switching and leakage power curves are quite flat around the optimum and power saving by pipelining is quite insensitive to modest deviations from the optimum. Therefore, 8 FO delays per stage might be a better choice since it simplifies design complexity with a small loss of power saving = = = =. Figure : Total power scaling with a clock-gating mechanism. 8 8 base base base pipe pipe pipe Figure : Optimal power saving with a clock-gating mechanism.. Case : No Clock-Gating Present Figure 8 shows the simulated total power without clock-gating for different s. With a low, total power curves follow idle power curves and low V th leads to more power saving (Section.). As the increases, total power curves follow switching power curves. Figure 9 shows the simulated optimal total power saving when there is no clock-gating mechanism. With zero, optimal power savings are around to % less than the clock-gating present case because of the timing element switching power overhead which is not present when there is a clock-gating scheme. Optimal power savings reach 8% slowly as increases compared to the clock-gated case. It is noted that low V th gets the most power saving regardless of. Figure shows the optimal logic depths when clock is not gated for different threshold voltages. Because the idle power is minimized when N is 8 (Section.), optimal logic depths remain at 8 until reaches around. (. at high V th )andafter. (. at high V th ), it falls to..8. = = = =. Figure 8: Total power scaling with no clock-gating mechanism. 8 8 base base base pipe pipe pipe Figure 9: Optimal power saving with no clock-gating mechanism.. DISCUSSION Our study has a number of limitations. The number of latches was assumed to grow linearly with the number of pipeline stages, whereas previous authors have used a superlinear latch count scaling formula of the form N, with an exponent ß : [, ]. It is not clear how latch counts scale in highly parallel architectures, but larger values of would increase the optimal logic depth. Depending on the computation being parallelized, additional state in the form of larger memory arrays might be required to track the increased number of operations in flight. A growth in the size of these memory structures would tend to increase energy per operation and hence increase optimal logic depth per stage, though

6 8 low Vt. 8 medium Vt. 8 high Vt. Figure : Optimal logic depth with no clock-gating mechanism. we expect this effect to be minor as memories are generally lower power than processing units. Our study did not include the effects of glitching on power. Others have noted that glitching activity reduces linearly with pipeline depth as it becomes less likely that inputs to a gate would have very different path lengths []. This effect would tend to push the optimum towards shallower pipeline stages. We did not include parasitic wire capacitance. Adding wire load capacitance to our model will increase total switching power, and so will again push the optimum towards shallower pipeline stages. For deeply pipelined circuits, fast path problems are more likely, as there will be an increase in the number of short logic paths between timing elements and an decrease in the relative wire delay. Because clock frequency is not increased, clock skew and jitter problems are not as apparent as in a frequency-scaled design, but clock jitter might increase as power supply to the clock drivers is reduced. One benefit of supply scale-down is that wire delay becomes relatively less significant as gates slow down. This helps reduce some of the design effort of building a highly pipelined circuit compared with pipelining for increased clock frequency. 9. REFERENCES [] A. Chandrakasan, W. J. Bowhill, and F. Fox. Design of High Performance Microprocessor Circuits. IEEE Press,. [] A. Chandrakasan et al. Low-power CMOS digital design. IEEE JSSC, (): 8, Apr. 99. [] V. De and S. Borkar. Technology and design challenges for low power and high performance. In ISLPED, pages 8, 999. [] Device Group at UC Berkeley. Predictive technology model. Technical report, UC Berkeley,. ptm/. [] A. Hartstein and T. Puzak. The optimum pipeline depth for a microprocessor. In ISCA 9, pages, May. [] A. Hartstein and T. Puzak. Optimum power/performance pipeline depth. In MICRO, Dec.. [] S.Heo,R.Krashinsky,andK.Asanović. Activity-sensitive flip-flop and latch selection for reduced energy. In 9th Conference on Advanced Research in VLSI, Salt Lake City,UT USA, March. [8] G. Hinton et al. A.8 μm CMOS IA- processor with a -GHz integer execution unit. IEEE JSSC, ():, Nov.. [9] M. Hrishikesh et al. The optimal logic depth per pipeline stage is to 8 FO ierter delays. In ISCA 9, pages, May. [] S. R. Kunkel and J. E. Smith. Optimal pipelining in supercomputers. In Proceedings th Symposium on Computer Architecture, pages, Tokyo, Japan, June 98. [] E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In ISCA 9, pages, May. [] V. Srinivasan et al. Optimizing pipelines for power and performance. In MICRO, Nov.. 8. CONCLUSIONS Pipelining can be an effective power-reduction tool when used to support voltage scaling in digital systems implementing highly parallel computations. Simulation results show that power-optimal logic depth is to 8 FO and varies from to 8% compared with a FO design depending on threshold voltage,, and the presence of clock-gating. Even though the exact power-optimal pipelining is technologydependent, we can gain some important insights from the simulation results. First, higher s decrease the poweroptimal logic depth and increase the because pipelining is most effective at saving the additional switching power. Second, pipelining is more effective with lower threshold voltages, resulting in lower logic depths and lowest power, except for low s when leakage power is dominant. Third, clock-gating enables deeper pipelining and more power saving because it reduces timing element overhead when is low. Therefore, power-optimal pipelining with clock gating should be an efficient low-power technique for high throughput blocks in systems implementing highly parallel computations.