CS 152 Computer Architecture and Engineering
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1 CS 152 Computer Architecture and Engineering Lecture 7 Pipelining I John Lazzaro ( TAs: David Marquardt and Udam Saini www-inst.eecs.berkeley.edu/~cs152/
2 Office Hours Change David: W 3-4, Th 3-4, 125 Cory Udam: W Cory, Tu Soda John: Mon 9:30-10:30 AM, 315 Soda
3 Last Time: Performance Equation Seconds Program Instructions Program Cycles Instruction Seconds Cycle Goal is to optimize execution time, not individual equation terms. Machines are optimized with respect to program workloads. The CPI of the program. Reflects the program s instruction mix. Clock period. Optimize jointly with machine CPI.
4 Today: Introduction to Pipelining How to apply the performance equation to our single-cycle CPU. Pipelining: an idea from assembly line production applied to CPU design Why pipelining is hard: data hazards, control hazards, structural hazards. Also: Introduction to Lab 3
5 Note: Reading is Fundamental... The book presentation of pipelined processors is sufficient to do Lab 3. These lectures are not. The lectures are a gentle introduction, to prepare you to read the book...
6 + Recall: Our single-cycle processor Challenge: Speed up clock while keeping CPI == 1 Seconds Program Instructions Program Cycles Instruction Seconds Cycle 0x4 CPI == 1 This is good. Slow. This is bad. D PC Q Addr Instr Mem Data RegFile rs1 rs2 rd1 ws rd2 wd WE op A L U Data Memory Addr Dout Din WE MemToReg Ext
7 Recall: An R-format CPU design Decode fields to get : ADD $8 $9 $10 opcode rs rt rd shamt funct Logic op RegFile rs1 rs2 rd1 ws rd2 wd WE A L U
8 Reminder: How data flows after posedge PC Instr Mem + D Q Addr Data 0x4 Logic op RegFile rs1 rs2 rd1 ws rd2 wd WE A L U
9 Next posedge: Update state and repeat PC D Q RegFile rs1 rs2 rd1 ws rd2 wd WE
10 Observation: Logic idle most of cycle For most of cycle, ALU is either waiting for its inputs, or holding its output Ideal: a CPU architecture where each part is always working. 0x4 + D PC Q Addr Instr Mem Data RegFile rs1 rs2 rd1 ws rd2 wd WE op A L U Data Memory Addr Dout Din WE MemToReg Ext
11 Inspiration: Automobile assembly line Assembly line moves on a steady clock. Each station does the same task on each car. The clock Car body shell Merge station Bolting station Car chassis
12 Inspiration: Automobile assembly line Simpler station tasks more cars per hour. Simple tasks take less time, clock is faster.
13 Inspiration: Automobile assembly line Line speed limited by slowest task. Most efficient if all tasks take same time to do
14 Inspiration: Automobile assembly line Simpler tasks, complex car long line! These lines go 24 x 7, and rarely shut down. Why?
15 Lessons from car assembly lines Faster line movement yields more cars per hour off the line. Faster line movement requires more stages, each doing simpler tasks. To maximize efficiency, all stages should take same amount of time (if not, workers in fast stages are idle) Filling, flushing, and stalling assembly line are all bad news.
16 Key Analogy: The instruction is the car Pipeline Stage #1 Stage #2 Stage #3 Stage #4 Stage #5 Instruction Fetch IR IR IR IR + PC 0x4 Instr Mem Controls hardware in stage 2 Controls hardware in stage 3 Controls hardware in stage 4 Controls hardware in stage 5 D Q Addr Data Data-stationary control
17 + Example: Decode & Register Fetch Stage Pipeline Stage #1 Stage #2 Stage #3 Instr Fetch Decode & Reg Fetch SUB R10, R9,R8 IR OR R7,R6,R5 IR ADD R4,R3,R2 IR 0x4 A sample program D PC Q Addr Instr Mem Data RegFile rs1 rs2 rd1 ws rd2 wd WE Ext A M B ADD R4,R3,R2 OR R7,R6,R5 SUB R10,R9,R8 R s chosen so that instructions are independent - like cars on the line.
18 Performance Equation and Pipelining + Seconds Program Instructions Program Cycles Instruction Seconds Cycle D PC Instr Fetch Decode & Reg Fetch Stage #3 Q 0x4 Addr Instr Mem Data IR IR IR CPI == 1 Once pipe is fill, one instruction completes per cycle rs1 rs2 ws wd RegFile WE rd1 rd2 Ext A M B Clock period is shorter Less work to do in each cycle To get shortest clock period, balance the work to do in each pipeline stage.
19 Hazards: An instruction is not a car... + Stage #1 Stage #2 Stage #3 Instr Fetch Decode & Reg Fetch D PC Q 0x4 Addr Instr Mem Data OR R5,R4,R2 IR IR IR... wrong value of R4 fetched from RegFile, contract with programmer broken! Oops! rs1 rs2 ws wd RegFile WE rd1 rd2 Ext A M B ADD R4,R3,R2 R4 not written yet... New sample program ADD R4,R3,R2 OR R5,R4,R2 An example of a hazard -- we must (1) detect and (2) resolve all hazards to make a CPU that matches ISA
20 Performance Equation and Hazards + Seconds Program Instructions Program Cycles Instruction Seconds Cycle D PC Instr Fetch Decode & Reg Fetch Stage #3 Q 0x4 Addr Instr Mem Data IR IR IR Some ways to cope with hazards makes CPI > 1 stalling pipeline rs1 rs2 ws wd RegFile WE rd1 rd2 Ext A M B Added logic to detect and resolve hazards increases clock period Software slows the machine down Seymour Cray
21 + A (simplified) 5-stage pipelined CPU 1 2 IF Stage Instr Fetch ID/RF Stage Decode & Reg Fetch 3 EX Stage Execution 4 MEM Stage Memory 5 WB Write Back IR IR IR IR WE, MemToReg Mux,Logic op D PC Q 0x4 Addr Instr Mem Data RegFile rs1 rs2 rd1 ws rd2 wd WE A M A L U Y M Data Memory Addr Dout Din WE MemToReg R Ext B Welcome to Lab 3!
22 Administrivia: Upcoming deadlines... Friday 9/23: Lab 2 Xilinx Checkoff, in section. For non-150 students, 150 Lab Lecture 4, 2-3 PM, 125 Cory. Monday 9/26: Lab 2 final report due via the submit program, 11:59 PM. Lab 3 now available on the web site Thursday 9/29: At 11:59 PM via Lab 2 peer evaluations, and Lab 3 preliminary design document due.
23 Starting 9/29: Homework, Midterm, Lab HW graded on effort Thursday review session. Will cover format, material, and ground rules for test. Midterm two weeks from today, in evening, no class that day. Lab 3 design doc, checkoffs, later in week...
24 Pipelining Your Processor Lab 3 Introduction
25 Week 1 for Lab 3: Pipelining Processors
26 Week 1 for Lab 3: Pipelining Processors
27 Week 2: Hazard-Free Code on the Board A sample program ADD R4,R3,R2 OR R7,R6,R5 SUB R10,R9,R8 R s chosen so that instructions are independent - like cars on the line.
28 Week 3: Run TA s Hard Tests on Xilinx New sample program ADD R4,R3,R2 OR R5,R4,R2 An example of a hazard -- we must (1) detect and (2) resolve all hazards to make a CPU that matches ISA
29 Next 2 Lectures: Pipelining details... Control, Hazards, Forwarding
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