CS 152 Computer Architecture and Engineering

Transcription

1 CS 152 Computer Architecture and Engineering Lecture 4 Testing Processors John Lazzaro ( TAs: Ted Hong and David Marquardt www-inst.eecs.berkeley.edu/~cs152/

2 Last Time: Single-Cycle Processors Addr Instr Mem Data Equal 32 Combinational Logic (Only Gates, No Flip Flops) Just specify logic functions! RegDest RegWr ExtOp ALUsrc MemWr MemToReg PCSrc RegDest RegFile rs1 rs2 rd1 ws rd2 wd WE Ext ALUctr op A L U 32 Equal 32 Data Memory Addr Dout Din WE 32 RegWr ExtOp ALUsrc MemWr MemToReg

3 Today s Lecture: Testing Processors The four types of Making a test plan Unit techniques

4 Lecture Focus: Functional Design Test Not manufacturing tests... goal The design correctly executes programs written in the supported subset of the MIPS ISA Clock speed? CPI? Upcoming lectures... Intel XScale ARM Pipeline, IEEE Journal of Solid State Circuits, 36:11, November 2001

5 Four Types of Testing

6 Big Bang: Complete Processor Testing Top-down complete (Lab 1) how it works Assemble the complete. Execute test program suite on the. Bottom-up Check results. What makes a good test program suite?

7 Methodical Approach: Unit Testing Top-down complete how it works Remove a block from the design. unit Bottom-up Test it in isolation against specification. What if the specification has a bug? What if team members do not use the exact same specification?

8 Climbing the Hierarchy: Multi-unit Testing Top-down complete multi-unit unit Bottom-up how it works Remove connected blocks from design. Test in isolation against specification. How to choose partition? How to create specification?

9 Processor Testing with Self-Checking Units Top-down complete with self-checks multi-unit unit how it works Add self-checking to units Perform complete Bottom-up Good for Xilinx? ModelSim? Why not use self-checks for all tests?

10 Testing: Verification vs. Diagnostics Top-down complete with self-checks multi-unit unit Bottom-up Verification: A yes/no answer to the question Does the have one more bug? Diagnostics: Clues to help find and fix the bug. Which types are good for verification? For diagnostics?

11 Xilinx: Observability and Controllability Top-down complete with self-checks multi-unit unit Bottom-up For early labs, use ChipScope for observability. For later labs... Observability: Can I sense the state I need to diagnose a bug on the board? Controllability: Can I force a flip-flop into known state to diagnose bugs on the board?

12 Use switches and LEDs on the board... LEDS Switches LEDS

13 Administrivia: Upcoming deadlines... Thursday: Lab 2 preliminary design document due to TAs via , 11:59 PM. Friday: Design Document Review, 12-1, 119 Cory. For 61(c) students, 150 Lab Lecture 2, 1-2 PM, 125 Cory. Monday: Lab 2 final design document due to TAs via , 11:59 PM.

14 Administrivia: Office Hours, Mid-terms Ted: Tu 5-6 PM and Fri AM David: Weds 2-3 PM and Fri 2-3 PM John: Mon 9:30-10:30 AM Mid-term 1: Thursday March 17th, 5:30 to 8:30 PM, Room TBA. Check for schedule conflicts now, let us know. Mid-term 2: Thursday May 5th, 5:30 to 8:30 PM, Room TBA. Check for schedule conflicts now, let us know.

15 Writing a Test Plan

16 The timeline... Top-down complete Plan in advance what tests to do when... Epoch 1 Epoch 2 Epoch 3 Epoch 4 with self-checks multi-unit unit Time Bottom-up assembly complete correctly executes single instructions correctly executes short programs

17 Testing to catch logic design errors... Top-down complete with self-checks multi-unit unit Bottom-up Which types are good for each epoch? Epoch 1 Epoch 2 Epoch 3 Epoch 4 unit early multi unit later assembly complete with self-checks multi-unit unit diagnostics correctly executes single instructions with self-checks multi-unit unit diagnostics correctly executes short programs complete verification with self-checks diagnostics Time New this year -- test benches checked off early

18 Works in ModelSim, not on the board... Top-down complete Result for half of the teams Our recommendations last year... Epoch 1 Epoch 2 Epoch 3 Epoch 4 with self-checks ModelSim 100 % ModelSim 100 % ModelSim 100 % ModelSim 20 % multi-unit Xilinx 0 % Xilinx 0 % Xilinx 0 % Xilinx 80 % unit Time Bottom-up assembly complete correctly executes single instructions correctly executes short programs

19 Possible solution... Top-down complete Idea: get confidence in going to board earlier... Epoch 1 Epoch 2 Epoch 3 Epoch 4 ModelSim ModelSim ModelSim ModelSim with self-checks 80 % Xilinx 80 % Xilinx 80 % Xilinx 20 % Xilinx multi-unit 20 % 20 % 20 % 80 % unit Bottom-up assembly complete correctly executes single instructions correctly executes short programs Time Also: catch Synplicity warnings and errors earlier

20 Unit Testing

21 Combinational Unit Testing: 3-bit Adder Cin Number of input bits? 7 A Sum Total number of possible input values? 2 7 = 128 B 3 Just test them all... Cout Apply test vectors 0,1, to inputs. 100% input space coverage Exhaustive

22 Combinational Unit Testing: 32-bit Adder Cin Number of input bits? 65 A B Cout 32 Sum Total number of possible input values? 2 65 = 3.689e+19 Just test them all? Exhaustive does not scale. Combinatorial explosion!

23 Test Approach 1: Random Vectors Cin how it works A B Sum Apply random A, B, Cin to adder. Check Sum, Cout. Cout When to stop? Bug curve. Bug Rate Bugs found per minute of Time

24 Test Approach 2: Directed Vectors A B Cin + Directed random? 32 Sum how it works Hand-craft test vectors to cover corner cases A == B == Cin == 0 Cout Black-box : Corner cases based on functional properties. Clear-box : Corner cases based on unit internal structure. Examples? Examples?

25 State Machine Testing 152 project examples: Cache control state machines, Branch prediction state machines,...

26 Specification: Traffic Light Controller CLK R (red) Y Change Rst If Change == 1 on positive CLK edge traffic light changes (yellow) G (green) RYG If Rst == 1 on positive CLK edge RYG=

27 State Machine: Traffic Light Controller Rst == 1 RYG 100 Change == 1 Change == 1 RYG 001 Change == 1 RYG 010

28 State Assignment: Traffic Light Controller Rst == 1 Change == 1 R Y G R Y G Change == Change == 1 R Y G One-Hot Encoding D Q R D Q G D Q Y

29 Next State Logic: Traffic Light Controller Rst == 1 Change == 1 Rst R Y G R Y G Change == Change == 1 Next State Combinational Logic R Y G Change D Q R D Q G D Q Y

30 State Machine Testing

31 Testing State Machines: Break Feedback Rst Change Next State Combinational Logic D Q R D Q G D Q Y Isolate Next State logic. Test as a combinational unit. Easier with certain Verilog coding styles?

32 State Verilog: Traffic Light Controller D Q R D Q G D Q Y wire next_r, next_y, next_g; output R, Y, G; ff ff_r(r, next_r, CLK); ff ff_y(y, next_y, CLK); ff ff_g(g, next_g, CLK);

33 Next State Verilog: Traffic Light Controller Rst Change Next State Combinational Logic next_r R G Y next_g next_y wire next_r, next_y, next_g; assign next_r = rst? 1 b1 : (change? Y : R); assign next_y = rst? 1 b0 : (change? G : Y); assign next_g = rst? 1 b0 : (change? R : G);

34 Verilog: Complete Traffic Light Controller wire next_r, next_y, next_g; output R, Y, G; assign next_r = rst? 1 b1 : (change? Y : R); assign next_y = rst? 1 b0 : (change? G : Y); assign next_g = rst? 1 b0 : (change? R : G); ff ff_r(r, next_r, CLK); ff ff_y(y, next_y, CLK); ff ff_g(g, next_g, CLK);

35 State Machine Testing

36 Testing State Machines: Arc Coverage? Rst == 1 Change == 1 R Y G R Y G Change == Change == 1 R Y G Force machine into each state. Test behavior of each arc. Is this technique always practical to use?

37 When bugs escape... (Testing our financial trading system), we found a case where our software would get a bad calculation. Once a week or so. Eventually, the problem turned out to be a failure in a CPU cache line refresh. This was a hardware design fault in the PC. The test suite included running for two weeks at maximum update rate without error, so this bug was found. Eric Ulevik

38 Conclusion -- Testing Processors Bottom-up test for diagnosis, top-down test for verification. Make your plan early! Unit : avoiding combinatorial explosions.

39 Coming up next week... Top-down view of how signals move through your in time. Software for teamwork, group dynamics, etc... Pipelined s...