CS 152 Computer Architecture and Engineering Lecture 3 Metrics

Transcription

1 CS 152 Computer Architecture and Engineering Lecture 3 Metrics John Lazzaro (not a prof - John is always OK) TA: Eric Love www-insteecsberkeleyedu/~cs152/ Play: CS 152 L3: Metrics UC Regents Spring 2014 UCB 1

2 Topics for today s lecture Metrics: Estimating the goodness of a CPU design so that we can redesign the CPU to be better Short Break A case study in microcode control: the Motorola 68000, the CPU that powered the original Macintosh [see Lecture 5 slides for this topic] Administrivia: Will announce office hours soon CS 152 L3: Metrics + Microcode UC Regents Spring 2014 UCB 2

3 On the drawing board Todd Hamilton, iwatch concept 3

4 Gray-scale computer graphics model Todd Hamilton, iwatch concept 4

5 Color computer graphics model Todd Hamilton, iwatch concept 5

6 Animated model Then the baton is passed to us Todd Hamilton, iwatch concept We use models to do stepwise refinement of the silicon that powers the consumer product 6

7 Four metrics: Performance Execution time of a program Energy Joules required to execute a program Today s Focus For a later lecture Cost How many dollars to manufacture Time to Market Will we ship a product before our competitors? For a later lecture For a later lecture 7

8 Performance Measurement (as seen by the customer) CS 152 L6: Performance UC Regents Fall 2006 UCB 8

9 Who (sensibly) upgrades CPUs often? A professional who turns CPU cycles into money, and who is cycle-limited Artist tool: animation, video special effects CS 152 L6: Performance UC Regents Fall 2006 UCB 9

10 How to decide to buy a new machine? Measure After Effects execution time on a representative render workload (still shot from the movie) Night flight City map and clouds computed on the fly with fractals CPU intensive Trivial I/O CS 152 L6: Performance UC Regents Fall 2006 UCB 10

11 Interpreting Execution Time Power Book G4 125 GHz Execution Time: 1265 seconds Performance 1 Execution Time = 285 renders/hour 15 GHz PB (Y) is N times faster than 125 GHz PB (X) N is? N = Performance (Y) Execution Time (X) Performance (X) = = 1 19 Execution Time (Y) PB 15 Ghz : 3 4 renders/hour PB 125 : 285 renders/hour Might make the difference in meeting a deadline CS 152 L6: Performance UC Regents Fall 2006 UCB 11

12 2 CPUs: Execution Time vs Throughput Execution Time: time for one job to complete 2 CPUs vs 1 CPU, otherwise similar 18x faster Implies parallel code on a Mac Throughput: # of independent jobs/hour completed Assume G5 MP execution time faster because AE isn t parallelized on Opteron CPUs However, G5 and Opteron may have same throughput CS 152 L6: Performance UC Regents Fall 2006 UCB 12

13 Performance Measurement (as seen by a CPU designer) Q Why do we care about After Effect s performance? A We want the CPU we are designing to run it well! CS 152 L6: Performance UC Regents Fall 2006 UCB 13

14 Step 1: Analyze the right measurement! Guides CPU design CPU Time: Time the CPU spends running program under measurement Measuring CPU time (Unix): % time <program name> 2577u 072s 0: % Guides system design Response Time: Total time: CPU Time + time spent waiting (for disk, I/O, ) CS 152 L6: Performance UC Regents Fall 2006 UCB 14

15 CPU time: Proportional to Instruction Count Q Once ISA is set, who can influence instruction count? A Compiler writer, application developer Q Static count? (lines of program printout) Or dynamic count? (trace of execution) A Dynamic CPU time Program Machine Instructions Program Rationale: Every additional instruction you execute takes time CS 152 L6: Performance Q How does a architect influence the number of machine instructions needed to run an algorithm? A Create new instructions: instruction set architect UC Regents Fall 2006 UCB 15

16 CPU time: Proportional to Clock Period Q How can architects (not technologists) reduce clock period? Q What ultimately limits an architect s ability to reduce clock period? We will revisit these questions later in lecture Time Program Time One Clock Period Rationale: We measure each instruction s execution time in number of cycles By shortening the period for each cycle, we shorten execution time CS 152 L6: Performance UC Regents Fall 2006 UCB 16

17 Completing the performance equation What factors make different programs have different CPIs? Cache behavior varies Instruction mix varies Branch prediction varies Seconds Program Instructions Program Cycles Instruction Seconds Cycle We need all three terms, and only these terms, to compute CPU Time! Q When is it OK to compare clock rates? A When other RHS terms are equal CS 152 L6: Performance CPI -- The Average Number of Clock Cycles Per Instruction For the Program UC Regents Fall 2006 UCB 17

18 Consider Lecture 2 single-cycle CPU All instructions take 1 cycle to execute every time they run CPI of any program running on machine? 10 average CPI for the program is a more-useful concept for more complicated machines CS L5: Pipelining UC Regents Fall 2008 UCB 18

19 Recall Lecture 2: Multi-flow VLIW CPU Q Which right-hand-side term decreases with N? Seconds Program Instructions Program A This one gets smaller Cycles Instruction Seconds Cycle A We hope this one doesn t grow Syntax: ADD $8 $9 $10 Semantics:$8 = $9 + $10 opcode rs rt rd shamt funct opcode rs rt rd shamt funct Syntax: ADD $7 $8 $9 Semantics:$7 = $8 + $9 N x -bit VLIW yields factor of N speedup! Multiflow: N = 7, 14, or 28 (3 CPUs in product family) CS 152 L3: Metrics + Microcode UC Regents Spring 2014 UCB 19

20 Consider machine with a data cache A program s load instructions stride through every memory address The cache never hits, so every load goes to DRAM (100x slower than loads that go to cache) Thus, the average number of cycles for load instructions is higher for this program Thus, the average number of cycles for all instructions is higher for this program Seconds Program Instructions Program Cycles Instruction Seconds Cycle Thus, program takes longer to run! CS 152 L6: Performance UC Regents Fall 2006 UCB 20

21 CPI as an analytical tool to guide design 5 Multiply 1 Other ALU Machine CPI (throughput, not latency) 2 Load 2 Store 2 Branch Program Instruction Mix Store 10% Branch 20% Load 20% Multiply 30% Other ALU 20% 5 x x x x x = 27 cycles/instruction Now we know how to optimize the design 20/270 7% Load 15% Branch 15% 7% Multiply 56% Where program spends its time CS 152 L6: Performance UC Regents Fall 2006 UCB 21

22 Final thoughts: Performance Equation Seconds Program Instructions Program Cycles Instruction Seconds Cycle Goal is to optimize execution time, not individual equation terms Machines are optimized with respect to program workloads The CPI of the program Reflects the program s instruction mix Clock period Optimize jointly with machine CPI CS 152 L6: Performance UC Regents Fall 2006 UCB 22

23 Invented the one ISA, many implementations business model CS 152 L6: Performance UC Regents Fall 2006 UCB 23

24 Amdahl s Law (of Diminishing Returns) Where program spends its time 8% Load 16% Branch 16% 8% Multiply 52% If enhancement E makes multiply infinitely fast, but other instructions are unchanged, what is the maximum speedup S? S = 1 (post-enhancement %) / 100% = 1 48%/100% = 208 Attributed to Gene Amdahl -- Amdahl s Law What is the lesson of Amdahl s Law? Must enhance computers in a balanced way! CS 152 L6: Performance UC Regents Fall 2006 UCB 24

25 Amdahl s Law in Action Program We Wish To Run On N CPUs Serial 30% Parallel 70% The program spends 30% of its time running code that can not be recoded to run in parallel S( ) S = (30 % + (70% / N) ) / 100 % # CPUs CPUs Speedup CS 152 L6: Performance UC Regents Fall 2006 UCB 25

26 Real-world 2006: 2 CPUs vs 4 CPUs 20 in imac Core Duo 2, 216 GHz $1500 Mac Pro 2 Dual-Core Xeons, 266 GHz $00 w/ 20 inch display CS 152 L6: Performance UC Regents Fall 2006 UCB 26

27 Real-world 2006: 2 CPUs vs 4 CPUs 2 cores on one die Amdahl s Law + Real-World Legacy Code Issues in action Source: MACWORLD 4 cores on two dies Caveat: Mac Pro CPUs are server-class and have architectural advantages (better I/O, ECC DRAM, ETC) CS 152 L6: Performance Simple audio and video tasks: easier to parallelize ZIPing a file: very difficult to parallelize UC Regents Fall 2006 UCB 27

28 Break CS 152 L3: Metrics Play: UC Regents Spring 2014 UCB 28

29 Timing CS 152 L3: Metrics UC Regents Spring 2014 UCB 29

30 CPU time: Proportional to Clock Period Q How can architects (not technologists) reduce clock period? Q What ultimately limits an architect s ability to reduce clock period? In this part of lecture: we answer these questions Time Program Time One Clock Period Rationale: We measure each instruction s execution time in number of cycles By shortening the period for each cycle, we shorten execution time CS 152 L6: Performance UC Regents Fall 2006 UCB 30

31 Goal: Determine minimum clock period + D PC Q Addr Instr Mem Data Equal Combinational Logic 0x4 PCSrc Clk E x t e n d op rs rt immediate 0 Control Lines RegDest RegFile rs1 rs2 rd1 ws rd2 wd WE Ext ALUctr op A L U Equal Data Memory Addr Dout Din WE RegWr ExtOp ALUsrc MemWr MemToReg CS L6: Timing UC Regents Fall 2008 UCB 31

32 A Logic Circuit Primer Models should be as simple as possible, but no simpler Albert Einstein CS 250 L3: Timing UC Regents Fall 2013 UCB

33 Inverters: A simple transistor model In CS 250 L3: Timing Inverter Out Out = In Correctly predicts logic output for simple static CMOS circuits In 0 1 Out Circuit In 1 0 Vdd PMOS Out NMOS Extensions to model subtler circuit families, or to predict timing, have not worked well pfet A switch On if gate is grounded nfet A switch On if gate is at Vdd UC Regents Fall 2013 UCB 33

34 Transistors as water valves (Cartoon physics) If electrons are water molecules, transistor strengths (W/L) are pipe diameters, and capacitors are buckets Vdd 1 A on p-fet fills up the capacitor with charge Open Charge 0 Water level Time A on n-fet empties the bucket CS 250 L3: Timing n Vdd Open Vdd Out Discharge 1 This model is often good enough 0 Water level Time UC Regents Fall 2013 UCB 34

35 What is the bucket? A gate s fan-out Inverter: NAND gate: Fan-out : The number of gate inputs driven by a gate s output Driving other gates slows a gate down Driving wires slows a gate down Driving it s own parasitics slows a gate down CS 250 L3: Timing UC Regents Fall 2013 UCB 35

36 Fanout CS 250 L3: Timing UC Regents Fall 2013 UCB 36

37 A closer look at fan-out Driving more gates adds delay Linear model works for reasonable fan-out 05ns Out: Low -> High Slope = 00021ns / ff FO4: Fanout of four delay CS 250 L3: Timing Delay time of an inverter driving 4 inverters Cout UC Regents Fall 2013 UCB 37

38 Propagation delay graphs Cascaded gates: 1 ->0 1 ->0 0 ->1 0 ->1 inverter transfer function Vout Vin CS 250 L3: Timing UC Regents Fall 2013 UCB 38

39 Worst-case delay through combinational logic T2 might be the worst-case delay path (critical path) 0 ->1 T2 0 ->1 T1 0 ->1 x = g(a, b, c, d, e, f) If d going 0-to-1 switches x 0-to-1, delay is T1 If a going 0-to-1 switches x 0-to-1, delay is T2 It would be surprising if T1 > T2 CS 250 L3: Timing UC Regents Fall 2013 UCB 39

40 1 v2 Why might? Wires have delay too Even in those cases where the transmission line effect is negligible: Wires posses distributed resistance and capacitance v1 v2 v3 v4 Wires posses distributed resistance and capacitance v1 v2 v3 v4 Wire Delay Time constant associated with distributed RC is proportional to the square of the length Time constant associated with distributed RC is proportional to the square of the length v3 v4 For short wires on ICs, v1 v2 v3 v4 resistance is insignificant (relative to effective R of transistors), but C is important Typically around half of C of gate load is in the wires For long wires on ICs: v1 v2 v3 v4 control signal, etc busses, clock lines, global Looks benign, but Resistance is significant, time therefore distributed RC effect dominates signals are typically rebuffered to reduce delay: time CS 250 L3: Timing UC Regents Fall 2013 UCB Spring 2003 EECS150 Lec10-Timing Page 16 40

41 Clocked Logic Circuits CS 250 L3: Timing UC Regents Fall 2013 UCB 41

42 From Delay Models to Timing Analysis clk Timing Analysis What is the smallest T that produces correct operation? f T 1 MHz 1 μs 10 MHz 100 ns 100 MHz 10 ns 1 GHz 1 ns CS 250 L3: Timing UC Regents Fall 2013 UCB 42

43 Timing Analysis and Logic Delay Register: An Array of Flip-Flops Combinational Logic If our clock period T > worst-case delay through CL, does this ensure correct operation? CS 250 L3: Timing UC Regents Fall 2013 UCB 43

44 Flip Flops have internal delays D Q Value of D is sampled on positive clock edge Q outputs sampled value for rest of cycle t_setup CLK D Q t_clk-to-q CS 250 L3: Timing UC Regents Fall 2013 UCB 44

45 Flip-Flop delays eat into time budget Combinational Logic ALU time budget T! # clk"q + # CL + # setup CS 250 L3: Timing UC Regents Fall 2013 UCB 45

46 Clock skew also eats into time budget CLKd CLK CLK CLK CLKd CLK CL As T 0, which circuit fails first? CL CLK CLK CLKd clock skew, delay in distribution T " T CL +T setup +T clk!q + worst case skew ost modern large high-performance chi CS 250 L3: Timing UC Regents Fall 2013 UCB 46

47 Clocks have dedicated wires (low skew) GCLK7 GCLK5 GCLK6 GCLK4 4 4 BUFGMUX 4 DCM 4 4 DCM Clock tree 4 Top Spine 8 Flip flop clock inputs are the leaves of the tree 8 Horizontal Spine Bottom Spine 8 8 DCM BUFGMUX 4 4 DCM From: Xilinx Spartan 3 data sheet Virtex is similar CS 152 L5: Timing GCLK2 GCLK0 GCLK3 GCLK1 UC Regents Fall 2006 UCB 47

48 Die photo: Xilinx Virtex Pro Gold wires form clock tree 48

49 Delay Grid Tuned sector trees Delay Sector buffers x CS 250 L3: Timing Clock Tree Delays, IBM Power CPU y Buffer level 2 Buffer level 1 UC Regents Fall 2013 UCB 49

50 15 10 Delay Volts (V) 20 ps skew Time (ps) Multiplefingered transmissio line x CS 250 L3: Timing Clock Tree Delays, IBM Power y UC Regents Fall 2013 UCB 50

51 Some Flip Flops have hold time t_setup t_inv t_hold CLK D Q D D must stay stable here What is the intended function of this circuit? CLK Does flip-flop hold time affect operation of this circuit? Under what conditions? CS 250 L3: Timing t_clk-to-q + t_inv > t_hold For correct operation UC Regents Fall 2013 UCB 51

52 Searching for processor critical path + D PC Q Addr Instr Mem Data Equal Combinational Logic 0x4 PCSrc Clk E x t e n d op rs rt immediate 0 Control Lines RegDest RegFile rs1 rs2 rd1 ws rd2 wd WE Ext ALUctr op A L U Equal Data Memory Addr Dout Din WE RegWr ExtOp ALUsrc MemWr MemToReg CS L6: Timing UC Regents Fall 2008 UCB 52

53 Searching for processor critical path Timing Analysis What is the smallest T that produces correct operation?? Must consider all connected register pairs Q Why might I suspect this one? A Very long wire on the path CS 250 L3: Timing UC Regents Fall 2013 UCB 53

54 Combinational paths for IBM Power 4 CPU The critical path Most wires have hundreds of picoseconds to spare Late-mode timing checks (thousands) Timing slack (ps) CS 250 L3: Timing From The circuit and physical design of the POWER4 microprocessor, IBM J Res and Dev, 46:1, Jan 2002, JD Warnock et al UC Regents Fall 2013 UCB 54

55 Power 4: Timing Estimation, Closure Timing Estimation Predicting a processor s clock rate early in the project From The circuit and physical design of the POWER4 microprocessor, IBM J Res and Dev, 46:1, Jan 2002, JD Warnock et al CS 250 L3: Timing UC Regents Fall 2013 UCB 55

56 Power 4: Timing Estimation, Closure Timing Closure Meeting (or exceeding!) the timing estimate From The circuit and physical design of the POWER4 microprocessor, IBM J Res and Dev, 46:1, Jan 2002, JD Warnock et al CS 250 L3: Timing UC Regents Fall 2013 UCB 56

57 Floorplaning: Essential to meet timing CS 250 L3: Timing (Intel XScale 80200) UC Regents Fall 2013 UCB 57

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59 CPU time: Proportional to Clock Period Q How can architects (not technologists) reduce clock period? A Shorten the machine s critical path Time Program Q What ultimately limits an architect s ability to reduce clock period? A Clock-to-Q, setup times, 2-D floorplanning geometry Time One Clock Period Rationale: We measure each instruction s execution time in number of cycles By shortening the period for each cycle, we shorten execution time CS 152 L6: Performance UC Regents Fall 2006 UCB 59

60 On Thursday Pipeline design - with enough detail to do a design Have fun in section! 60