Lecture #17: CPU Design II Control
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1 Lecture #7: CPU Design II Control
2 Anatomy: 5 components of any Computer Personal Computer Computer Processor Control ( brain ) This week ( ) path ( brawn ) (where programs, data live when running) Devices Input Output Keyboard, Mouse Disk (where programs, data live when not running) brawn: muscle Display, Printer
3 Review: A Single Cycle path Rs,,, Imed6 connected to datapath We have everything except control signals Instruction<3:> npc_sel Instruction Fetch Unit RegDst RegWr Rs Rs Imm ALUctr Zero busa MemWr MemtoReg Rw Ra Rb busw -bit Registers busb WrEn Adr In imm6 6 ALUSrc Extender ExtOp AL LU <2 :25> <6 :2> < :5> <: 5>
4 An Abstract View of the Critical Path Critical Path (Load Operation) = This affects Delay clock through PC (FFs) + how much you Instruction s Access Time + can overclock your PC! Register File s Access Time, + ALU to Perform a -bit Add + Ideal Access Time + Instruction Instruction Stable Time for Register File Write Instruction Address s Next Addres PC Cl lk 5 Rs 5 5 Rw Ra Rb -bit Registers Imm 6 A B ALU Address Dt In Ideal
5 Recap: Meaning of the Control Signals npc_mux_sel: PC < PC + 4 n =nextn next PC < PC {SignExt(Imm6), } Later in lecture: higher-level connection between mux and branch cond npc_mux_sel 4 Adr Inst Adder PC 6 imm PC Ext Adde er
6 Recap: Meaning of the Control Signals ExtOp: zero, sign MemWr: write memory Zero or sign extended ALUsrc: regb; MemtoReg: ALU; Mem immed RegDst: rt ; rd ALUctr: add, sub, or RegWr: write register RegDst RegWr busw Equal Rs busa Rw Ra Rb -bit Registers busb imm6 6 Extende er ALUctr = ALU MemWr In WrEn Adr MemtoReg ExtOp ALUSrc
7 RTL: The Add Instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt MEM[PC] Fetch the instruction from memory R[rd] = R[rs] + R[rt] The actual operation PC = PC + 4 Calculate the next instruction s s address
8 Instruction Fetch Unit at the Beginning of Add Fetch the instruction ti from Instruction ti memory: Instruction = MEM[PC] same for all instructions npc_mux_sel Inst Instruction<3:> Adr 4 Adder PC imm m6 PC Ext Adde er
9 The Single Cycle path during Add 3 26 R[rd] = R[rs] + R[rt] RegDst = Rs RegWr = busw imm6 2 6 op rs rt rd shamt funct Rw Ra Rb -bit Registers 6 npc_sel= +4 busb Ex xtender busa ExtOp = x Since there is no extension Instruction Fetch Unit ALUctr = Add ALUSrc = AL LU In 6 Instruction<3:> Zero <2:2 25> Rs <6:2 2> <: 5> No memory write should be not x <: 5> Imm6 MemtoReg = MemWr = WrEn Adr
10 Instruction Fetch Unit at the End of Add PC = PC + 4 This is the same for all instructions except: Branch and Jump npc_mux_sel Inst Adr Instruction<3:> imm 6 4 Adder Add der PC
11 Single Cycle path during Or Immediate? op rs rt immediate R[rt] = R[rs] OR ZeroExt[Imm6] RegDst = RegWr = 5 5 Rs 5 busw imm6 Rw Ra Rb -bit Registers 6 npc_sel = busb Ex xtender busa ExtOp = 6 Instruction Fetch Unit ALUctr = ALUSrc = AL LU In Instruction<3:> Zero <2: :25> Rs <6: :2> <: :5> MemWr = WrEn Adr <: 5> Imm6 MemtoReg =
12 Single Cycle path during Or Immediate? op rs rt immediate R[rt] = R[rs] OR ZeroExt[Imm6] RegDst = Rs RegWr = busw imm6 Rw Ra Rb -bit Registers 6 npc_sel= +4 busb Ex xtender ExtOp = busa 6 Instruction Fetch Unit ALUctr = Or ALUSrc = AL LU In Instruction<3:> Zero <2: :25> <6: :2> <: :5> <: 5> Rs Imm6 MemtoReg = MemWr = WrEn Adr
13 The Single Cycle path during Load? op rs rt immediate 6 R[rt] [t] = oy{ {R[rs] [s] + Sg SignExt[imm6]} RegDst = Rs RegWr = busw imm6 Rw Ra Rb -bit Registers 6 ExtOp = npc_sel= busb Ex xtender busa ALUSrc = Instruction Fetch Unit ALUctr = AL LU In Instruction<3:> Zero <2:2 25> Rs <6:2 2> MemWr = WrEn Adr <: 5> <: 5> Imm6 MemtoReg =
14 The Single Cycle path during Load op rs rt immediate 6 R[rt] [t] = oy{ {R[rs] [s] + Sg SignExt[imm6]} RegDst = Rs RegWr = busw imm6 Rw Ra Rb -bit Registers 6 npc_sel= +4 busb Ex xtender ExtOp = busa Instruction Fetch Unit ALUctr = Add ALUSrc = AL LU In Instruction<3:> Zero <2:2 25> <6:2 2> <: 5> <: 5> Rs Imm6 MemtoReg = MemWr = WrEn Adr
15 The Single Cycle path during Store? op rs rt immediate {R[rs] + SignExt[imm6]} = R[rt] RegDst = Rs RegWr = busw imm6 Rw Ra Rb -bit Registers 6 npc_sel = busb Ex xtender busa ExtOp = 6 Instruction Fetch Unit ALUctr = ALUSrc = ALU In Instruction<3:> Zero <2:2 25> Rs <6:2 2> <: 5> MemWr = WrEn Adr <: 5> Imm6 MemtoReg =
16 The Single Cycle path during Store op rs rt immediate {R[rs] + SignExt[imm6]} = R[rt] Since there is no regfile write RegDst = x RegWr = 5 5 Rs 5 busw imm6 Rw Ra Rb -bit Registers 6 6 npc_sel= +4 Instruction Fetch Unit busb Ex xtender ExtOp = busa 이부분은사용안됨 ALUctr = Add AL LU In ALUSrc = Instruction<3:> Zero <2: :25> <6: :2> <: :5> <: 5> Rs Imm6 MemtoReg = x MemWr = WrEn Adr
17 The Single Cycle path during Branch? op rs rt immediate if (R[rs] - R[rt] == ) then Zero = ; else Zero = RegDst = RegWr = 5 5 Rs 5 busw imm6 Rw Ra Rb -bit Registers 6 npc_sel= busb Ex xtender ExtOp = busa 6 ALUctr = ALUSrc = Instruction Fetch Unit AL LU In Instruction<3:> Zero <2: :25> Rs <6: :2> <: :5> MemWr = WrEn Adr <: 5> Imm6 MemtoReg = x
18 The Single Cycle path during Branch op rs rt immediate if (R[rs] - R[rt] == ) then Zero = ; else Zero = RegDst = x RegWr = 5 5 Rs 5 busw imm6 Rw Ra Rb -bit Registers 6 npc_sel= Br busb Ex xtender ExtOp = x busa 6 Instruction Fetch Unit ALUctr =Sub ALUSrc = AL LU In Instruction<3:> Zero <2: :25> <6: :2> <: :5> <: 5> Rs Imm6 MemtoReg = x MemWr = WrEn Adr
19 Instruction Fetch Unit at the End of Branch op rs rt immediate if (Zero == ) then PC = PC SignExt[imm6]*4 ; else PC = PC + 4 npc_sel Zero Inst Adr Instruction<3:> What is encoding of npc_sel? 4 npc_mux_sel Direct MUX select? Branch / not branch Adder Let s pick 2nd option imm6 Ad dder PC npc_mux_sel npc_sel zero? MUX x Q: What logic gate? AND gate
20 Step 4: Given path: RTL -> Control Instruction<3:> Inst Adr <26:3> < :5> Op Fun <2 2:25> < 6:2> < :5> <:5> Rs Imm6 Control npc_sel RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg Zero DATA PATH
21 inst A Summary of the Control Signals (/2) Register Transfer ADD R[rd] < R[rs] + R[rt]; PC < PC + 4 ALUsrc = RegB, ALUctr = add, RegDst = rd, RegWr, npc_sel = +4 SUB R[rd] < R[rs] R[rt]; PC < PC + 4 ALUsrc = RegB, ALUctr = sub, RegDst = rd, RegWr, npc_sel = +4 ORi R[rt] < R[rs] + zero_ext(imm6); PC < PC + 4 ALUsrc = Im, Extop = Z, ALUctr = or, RegDst = rt, RegWr, npc_sel = +4 LOAD R[rt] < MEM[ R[rs] + sign_ext(imm6)]; PC < PC + 4 ALUsrc = Im, Extop = Sn, ALUctr = add, MemtoReg, RegDst = rt, RegWr, npc_sel = +4 STORE MEM[ R[rs] + sign_ext(imm6)] < R[rs]; PC < PC + 4 ALUsrc = Im, Extop = Sn, ALUctr = add, MemWr, npc_sel = +4 BEQ if ( R[rs] == R[rt] ) then PC < PC + sign _ ext(imm6)] else PC < PC + 4 npc_sel = Br, ALUctr = sub
22 A Summary of the Control Signals (2/2) See func We Don t Care :-) Appendix A op add sub ori lw sw beq jump RegDst ALUSrc x x x x MemtoReg RegWrite MemWrite x x x npcsel Jump ExtOp x x x x ALUctr<2:> Add Subtract Or Add Add Subtract xxx Column by column 으로볼것 R-type op rs rt rd shamt funct add, sub I-type op rs rt immediate ori, lw, sw, beq J-type op target address jump
23 Administrivia Project 2 Due Sunday HW 6 out tomorrow Slight shakeup of the schedule starting tomorrow (we re only doing one Control lecture) This allows us to have the second midterm before the drop deadline, if that would be preferable
24 이후 self study J-type The Single Cycle path during Jump op target address New PC = { PC[3..28], target address, } <2: :25> <6: :2> <: :5> jump Jump= Instruction<3:> npc_sel= Instruction Fetch Unit RegDst = RegWr = ALUctr = Rs Rs Imm6 TA MemtoReg = busa Zero MemWr = Rw Ra Rb busw -bit Registers busb WrEn Adr In imm6 6 ALUSrc = Ex xtender ExtOp = AL LU <: 5> <:2 25>
25 The Single Cycle path during Jump J-type op target address New PC = { PC[3..28], target address, } <2: :25> <6: :2> <: :5> jump Jump= Instruction<3:> npc_sel= Instruction Fetch Unit RegDst = x RegWr = ALUctr =x Rs Rs Imm6 TA MemtoReg = x busa Zero MemWr = Rw Ra Rb busw -bit Registers busb WrEn Adr In imm6 6 ALUSrc = x Ex xtender ExtOp = x AL LU <: 5> <:2 25>
26 Instruction Fetch Unit at the End of Jump J-type op target address New PC = { PC[3..28], target address, } jump Jump npc_sel Zero Inst Adr Instruction<3:> npc_mux_sel imm6 4 Adder Add der How do we modify this to account for jumps? PC
27 Instruction Fetch Unit at the End of Jump J-type op target address New PC = { PC[3..28], target address, } jump Jump npc_sel Inst Adr Instruction<3:> Zero imm6 4 npc_mux_sel Add der Adder TA (MSBs) PC Query Can Zero still get asserted? Does npc_sel need to be? If not, what? All depends on designer
28 Build CL to implement Jump on paper now Inst3 Inst3 Inst29 Inst28 Inst27 Inst26 Inst25 Jump Inst Inst
29 Build CL to implement Jump on paper now Inst3 Inst3 Inst29 Inst28 Inst27 Inst26 Inst25 Inst Inst A B 2-input 6-bit-wide XNOR 6-input AND A i B i XNOR Jump
30 Peer Instruction RegDst busw RegWr imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 npc_sel busb Ex xtender busa ExtOp Instruction Fetch Unit ALUctr ALUSrc ALU In Instruction<3:> Zero <2:25> <6:2> Rs MemWr <:5> WrEn Adr <:5> Imm6 MemtoReg A. MemToReg= x & ALUctr= sub. SUB or BEQ? B. ALUctr= add. Which signal is different for all 3 of: ADD, LW, & SW? RegDst or ExtOp? C D t C i l f l b C. Don t Care signals are useful because we can simplify our Boolean equations?
31 And in Conclusion Single cycle control 5 steps to design a processor. Analyze instruction set => datapath requirements 2. Select set of fdatapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. Processor 5. Assemble the control logic Control is the hard part MIPS makes that easier Control path Instructions ti same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Input Output
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