Efficient methods for analog mixed signal verification Interface handling methods, trade-offs and guidelines
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1 Efficient methods for analog mixed signal verification Interface handling methods, trade-offs and guidelines akshmanan Balasubramanian, Bharath Kumar Poluri, Texas Instruments Shoeb Siddiqui, IITM Vijay Kumar Sankaran, Cadence Accellera Systems Initiative 1
2 Acknowledgement Jagdish C Rao, Nikhil Chandrakant Sangani of Texas Instruments (TI) for their support and motivation Badrinarayanan Zanwar, Bhanuprakash R and Michael Womac of Cadence Design Systems (CDS) for their specific technical contributions and support of towards the studies of several flavours of CMs for AMS co-simulation Abhijeet Kolpekwar, Chong Chi, Ron Vogelsong, Dan Cline, Michael Dolan, Andre Baguenier and Vishwajeet Betai of CDS for their untiring support on AMS co-simulation methodology, technical discussions, brainstorming and formal tool support Kalyan Ram Hampapuram, Aswani Kumar Golla, and Penchalkumar Gajula of TI for their support on several aspects of backend physical design flow and tools Accellera Systems Initiative 2
3 Objective Context: AMS co-simulation Explain connect modules / interface elements Power managed designs Introduce different types of CMs Compare Implementation intricacies Automation requirements True supply sensitivity Recommendations Accellera Systems Initiative 3
4 Motivation: Analog mixed signal Increasing analog integration Increasing system complexity, flexibility and richness of functionalities Time-to-market pressures & first pass silicon success Finding issues later in the product or design cycle is expensive Quality product on time in the hands of end user Accellera Systems Initiative 4
5 AMS co-simulation: Significance Digital (Event driven) and analog (SPICE) simulation engines running simultaneously, in coherence To simulate systems having digital and analog contents A misnomer! Not necessarily digital Vs analog Mix of (Digital, Behavioural abstraction) & (analog, transistor level or device level abstraction) Necessary though limited scope Synopsys: VCS-Nanosim, VCS-HSIM Cadence: NC-Ultrasim, NC-Spectre/APS Performed at various levels of accuracy and abstraction To realistically trade-off simulation run time Vs accuracy AMS co-simulation with only focused functions in T Other functions (including analog) as ABMOD Accellera Systems Initiative 5
6 Abstraction levels: Cost Vs Accuracy Digital DMS Register Transfer evel (RT) Gate evel (G) with timing annotation Transistor evel (T) Accuracy Method Event driven Faster SPICE based analog simulator Slower Simulation run time (Speed ) & Cost Analog Behavioural models (BMOD) Digital equivalent models (VHD/Verilog) Analog models using digital tools VHD RN (Real Number), Verilog wreal Analog macro models Verilog A Verilog or VHD AMS SPICE macro models Transistor evel (T) Device level models with detailed characterisation Most accurate Accellera Systems Initiative 6
7 Abstraction levels: Cost Vs Accuracy Digital Register Transfer evel (RT) Gate evel (G) with timing annotation Conventional AMS Transistor evel (T) Accuracy Method Event driven Faster SPICE based analog simulator Slower Simulation run time (Speed ) & Cost Analog Behavioural models (BMOD) Digital equivalent models (VHD/Verilog) Analog models using digital tools VHD RN (Real Number), Verilog wreal Analog macro models Verilog A Verilog or VHD AMS SPICE macro models Transistor evel (T) Device level models with detailed characterisation Most accurate Accellera Systems Initiative 7
8 AMS co-simulation setup Testbench C 1 R 1 Digital Toplevel IOs Mixed Signal SoC Connect Module A2D Connect Module D2A Connect Module A2D Connect Module BiDi On-chip Oscillators ADC Comparator Power Management Selected Analog simulated in transistor level Analog BUS Functional Models Digital BUS Functional Models Analog modules simulated in transistor level always Accellera Systems Initiative 8
9 Connect modules for A(D)MS CM (IE): To handle signals crossing inconsistent data types Multiple disciplines Co-simulation boundary ogical and real domains E Continuous, real valued Variable VDD E2-CM Discrete, binary valued Variable 1 t r t f 0 0 0V Accellera Systems Initiative 9
10 Connect modules: Basic function evel (Voltage) conversion w.r.t a threshold Pre-defined constant Pre-defined derived function ogic Output X 0 X 1 Electrical Voltage Input VHI VO Vsupmin Pre-defined Voltage Thresholds Time Accellera Systems Initiative 10
11 Connect module flavours Voltage & Current handling Impedance handling Strength based CM Supply awareness Static CM Dynamic CM Inherited CM Inherited CM with CPF (Power aware CM) Supply sensitive CM Accellera Systems Initiative 11
12 Static connect modules evel (Voltage) conversion w.r.t a pre-defined constant threshold ogic Output X 0 X 1 Electrical Voltage Input VHI VO Pre-defined Voltage Thresholds Time Accellera Systems Initiative 12
13 Static CM Implementation connectmodule E2 (Ain, Dout); input Ain; electrical Ain; // electrical input output Dout; \logic Dout; // logic output // INSTANCE PARAMETERS: parameter real vsup=3.6 from (0:inf); // nominal supply voltage parameter real vthi=vsup/1.5 from (-inf:vsup); // upper input threshold parameter real vtlo=vthi/2 from (-inf:vthi); // lower threshold parameter real vtol=vsup/100 from (0:(vthi-vtlo)/4]; // voltage tolerance // OCA VARIABES: reg Dreg; // output register initial begin end endmodule Accellera Systems Initiative 13
14 Static CM Multiple voltage & power domain 2E E2 Digital RT / G + SDF E 2E E2 E BD 2R R2 R BD 2R R2 R BD Analog (Electrical / T) Analog (Real Numbered BMOD) Accellera Systems Initiative 14
15 PM handling with Static CM Identify all the CM instances after compilation and elaboration Classify CM instances among the different voltage domains Assign the variable vsup for each CM instance to constant value defparam testbench.duv.a_3v_e2.vsup=3.0; defparam testbench.duv.b_1p8v_e2.vsup=1.8; Pursue with simulation; now the setup can comprehend the difference between different voltage domains even though in a static manner. Accellera Systems Initiative 15
16 Static CM: Summary No power domain handling Manual voltage domain handling No dynamism Fixed supply voltage levels per simulation run Digital RT / G + SDF 2E E2 E 2E E2 E BD 2R R2 R BD 2R Analog (Electrical / T) Analog (Real Numbered BMOD) R2 R BD Accellera Systems Initiative 16
17 Dynamic CM Very critical with multiple voltage supplies & levels Supply 1.3 V 0 V D2A input D2A output Static CM D2A output Dynamic CM V 0 V 1.3 V 0 V t0 t1 t2 t D2A output doesn t track supply dynamics D2A output tracks supply dynamics Accellera Systems Initiative 17
18 Supply inherited connect modules Inherits the top-level power net Uses the voltage value for conversion (in real time) Definition (Global!) in CM overrides physical supply connectivity VDD E E2 - Inh Accellera Systems Initiative 18
19 Supply inh. CM Implementation connectmodule E2_inhconn (Ain, Dout); input Ain; electrical Ain; // electrical input output Dout; \logic Dout; // logic output // Inherited vdd! and vss! electrical (* integer inh_conn_prop_name="vdd"; integer inh_conn_def_value="cds_globals.\\vdd! "; *) \vdd! ; electrical (* integer inh_conn_prop_name="vss"; integer inh_conn_def_value="cds_globals.\\vss! "; *) \vss! ; // INSTANCE PARAMETERS: parameter real vsup_min=0.5 from (0:inf); // min supply for normal operation // scaled input/output levels/thresholds (0 maps to Vref, 1 maps to vdd-vss): // OCA VARIABES: real Vds; // supply voltage real Vas; // input voltage initial begin end... analog begin Vds = V(\vdd!,\vss! ); Vas = V(Ain,\vss! ); end endmodule Accellera Systems Initiative 19
20 Supply inherited connect modules Multiple voltage & power domain Accellera Systems Initiative 20
21 PM handling with supply inh. CM Identify all voltage domains Create unique CM definition per domain Supply node reference for different domains Defining a unique logic discipline (Ex. logicavdd & logicdvdd) electrical (* integer inh_conn_prop_name="vdd"; integer inh_conn_def_value= testbench.avdd"; *) \avdd! ; electrical (* integer inh_conn_prop_name="vss"; integer inh_conn_def_value= testbench.avss"; *) \avss! ; electrical (* integer inh_conn_prop_name="vdd"; integer inh_conn_def_value= testbench.dvdd"; *) \vdd! ; electrical (* integer inh_conn_prop_name="vss"; integer inh_conn_def_value= testbench.dvss"; *) \vss! ; Classify the different cells, cell instances, instance terminals and nets into logic domains Use the backend physical design tool Pursue with compilation, elaboration and simulation Accellera Systems Initiative 21
22 Supply inherited CM: Summary No power domain handling Semi-automated voltage domain handling Discipline definitions ogical: Multiple supply domains Superficial (not through physical supply connectivity) supply dependence definition Dynamism supported Power-up/down (ramp) & mode transitions Accellera Systems Initiative 22
23 Supply inherited CM with C/UPF Voltage conversion based upon whether that particular power domain is active or not Definition (Global!) in C/UPF overrides physical supply connectivity VDD1 Inactive VDD2 E E2 - Inh E2 - Inh x Accellera Systems Initiative 23
24 Supply Inherited CM with C/UPF Summary Power domain handling CPF / UPF Semi-automated voltage domain handling Discipline definitions ogical: Multiple supply domains Superficial (not through physical supply connectivity) supply dependence definition Dynamism supported Power-up/down (ramp) & mode transitions Accellera Systems Initiative 24
25 True supply sensitive CM References the ogic Ordinary Module (OM) of the port it is connected to Uses the SS info of the port VDD (*VDD*) E E2 - SS Accellera Systems Initiative 25
26 SS CM implementation connectmodule E2_ss (Ain, Dout); input Ain; electrical Ain; // electrical input output Dout; \logic Dout; // logic output // Supply Sensitivity attributes electrical (* integer supplysensitivity = "cds_globals.\\vdd! " ; *) \vdd! ; electrical (* integer groundsensitivity = "cds_globals.\\vss! " ; *) \vss! ; // INSTANCE PARAMETERS: initial begin end... analog begin end endmodule Accellera Systems Initiative 26
27 Requirements on design elements SS information in all design elements Definitions of Standard cells, IOs and ABMODs input VCC; input VDD; input (* integer supplysensitivity = "VCC" ; integer groundsensitivity = "VSS" ; *) a_3p0v; input (* integer supplysensitivity = "VDD" ; integer groundsensitivity = "VSS" ; *) a_3p0v; Accellera Systems Initiative 27
28 True supply sensitive CM Multiple voltage & power domain Power domain handling CPF / UPF Fully automated voltage domain handling SS constructs in models & RT Dynamism supported Power-up/down (ramp) & mode transitions Digital RT + CPF / G + SDF + SS constr ucts 2E E2 E 2E E2 E BD 2R R2 R BD 2R R2 R BD Analog (Electrical / T) Analog (Real Numbered BMOD) + CPF (not supported) + SDF (not supported) + SS constructs Accellera Systems Initiative 28
29 SS CM: DMS Vs AMS compatibility Homogeneous SS Electrical ABMODs (VAMS) No DMS & always need co-simulation over head VDD (E) VDD (E) E E SS: E Works: No VDD (E) Accellera Systems Initiative 29
30 SS CM: DMS Vs AMS compatibility RN ABMODs with supply as real VDD (R) (BMOD) R R VDD (R) Accellera Systems Initiative 30 VDD (R)
31 SS CM: DMS Vs AMS compatibility Heterogeneous SS CM insertion on the supply path Can also be handled through discipline resolution algorithm & CM optimisation VDD (E) VDD (R) R E SS: E Works: No R VDD (R) Accellera Systems Initiative 31 SS: E Works: No
32 SS CM: imitations 1. ogical power awareness PA GS Requires logical operation on supply Supply path CM insertion Sensitive on itself! Difficult to handle Especially on real supply Hypothesis: If supported Number of CM blows-up Performance / Run time impact Is it really needed? SS on WE/BODY & PA on supply, vice-versa No PA in AMS SS CM handles 1 st stage PA RT/GS/DMS regressions to be PA for coverage Accellera Systems Initiative 32
33 SS CM: imitations 2. Out of module references OOMR Assertions for metric driven verification (MDV) Avoid waveform analysis Improves efficiency CM insertion What is the sensitivity? Use access functions / built-in tasks CDS_GET_ANAOG_VAUE $SNPS_GET_VOT, $SNPS_GET_PORT_CURRENT Avoids CM insertion for OOMR and hence handling SS Accellera Systems Initiative 33
34 SS CM: imitations 3. Performance impact Heterogeneity Number of CMs can blow-up Algorithmic or SS type handling G-AMS Number of CMs can blow-up due to fan-out nodes Algorithmic improvement CM optimisation on signal path Merge supply at least for E2 Accellera Systems Initiative 34
35 SS CM: Superiority No verification side bottleneck in setup Power and SS intent Available at design Accellera Systems Initiative 35
36 Comparison & Recommendations S. No Requirements Static CM Supply inherited CM 1 Power awareness Inherently not supported. Dynamic with global. 2 Multiple voltage and power domains 3 Setup effort G concerns simulation Migration of legacy designs Recommended design flavours & stage Sandwitch configuration Improvements needed AMS Static support using custom setup requiring high effort. Negligible for designs with single supply. High for power managed (PM) designs. None. ow effort. Same as new design. Non-PM designs. No additional effort. String parameter support for vsup. Dynamic, not connectivity aware. High in defining disciplines. Custom automation possible. None. Moderate effort. Same as new design. PM designs at mature stage. Designs not having SS information. Additional discipline handling required. None. Supply sensitive CM Dynamic with actual. Dynamic & connectivity aware. ow. Initial effort spread across each design element. Performance issue due to CM blow-up. High effort. Custom automation possible. PM design at early stage. Designs having SS information. No additional effort. Heterogeneity & Hierarchical CM optimisation. Power aware (CPF/UPF) Dynamic with global. Dynamic, not connectivity aware. None. Reuses existing PA RT simulation flow setup. CPF may be stripped which has SS information. Very high effort, if no CPF/UPF available. PM designs with CPF/UPF, with no G AMS requirement. Not evaluated. G-AMS simulation support. Accellera Systems Initiative 36
37 Conclusions AMS co-simulation is in-escapable for AMS SoC CM (IE) is inherent to any co-simulation for discipline/domain crossings Flavours of CM evolved Static, Supply inherited, SI with C/UPF & Supply sensitive Practical tips, and automation needs identified Power managed designs are common SS CM is superior on intent transfer & reducing verification setup bottleneck imitations exist: Collaboration underway for solutions Comparison and recommendations provided Accellera Systems Initiative 37
38 Questions Thanks for your interest, attention, and time Accellera Systems Initiative 38
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