Intro to: Ultra-low power, ultra-high bandwidth density SiP interconnects

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1 <Insert Picture Here> This work was supported in part by DARPA under contract HR The views, opinions, and/or findings contained in this article/presentation are those of the author/presenter and should not be interpreted as representing the official views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense Intro to: Ultra-low power, ultra-high bandwidth density SiP interconnects Ashok V. Krishnamoorthy, Ron Ho, John Cunningham, Xuezhe Fafa Zheng, Jon Lexau Oracle Labs

2 Optical link penetration Data Rate (Gb/s) Gb/s * m Distance (m) MMF SMF Copper Backplanes Coax (1970s) 100Gb/s.m 10Gb/s.m 1000Gb/s.m Krishnamoorthy et al., IEEE JSTQE, Vol. 17 (2),p , March/April 2011 Companies leading the way QDR/FDR/EDR: Tyco, Finisar, Emcore, FCI (Merge), Avago, Molex, Luxtera

3 Better Interconnects, Better Systems Compute density (& functionality) improvements > Want higher performance/area (volume) at manageable thermal density Power improvements > Want higher BW/Watt to achieve breakthrough performance on key benchmarks Productivity (programming) improvements > Want better bisection bandwidth & random memory access for improvements in development & execution time productivity Memory latency improvements > Want reductions in memory-access latency over all-electrical systems

4 Processor I/O scaling Total Off-chip I/O Bandwidth [Tbps] Intel AMD Sun/Oracle IBM Virtex IBM P7 IO Scaling Oracle T Number of pins off package Year of Revenue Release (Aprox.) Data after D. Huang., IEEE HSD Workshop 2011, Santa Fe Consistent I/O bandwidth growth: ~2x every 2 years Need >20Tbps I/O soon Packaging falling behind historically Limited high speed pin count pushes for higher data rates 1000

5 Lots of work trying to solve this problem Integrate vertically with TSVs (build up) Complex packaging and assembly, but it will be here soon Thermal issues limit the architectural use cases (memory) Integrate horizontally with fine pitch IO (build out) Complex package, assembly, and test with MCMs Known-good die issues Source: IBM Source: Samsung

6 An ideal (?) solution Enable systems with chips that build both up and out Aggregate TSV ed chip stacks with a fine pitch IO But without conductive (soldered) attachments, to help yield Needs a chip-to-chip IO with enormous BW and low energy 6

7 Improving link energy efficiency Link Energy Efficiency (pj/bit/m) System Target: <<1 mw per Gigabit/s per meter Krishnamoorthy et al., IEEE JSTQE, Vol. 17 (2),p , March/April 2011 Electrical links today VCSEL links today Si Target 100fJ/bit (Core) 500fJ/bit (Core - L3 cache & MM) 2pJ/bit (Core Distant Memory) Link Distance (m)

8 One possibility: optically-enabled silicon Create enormously dense IO channels over fast optical media Optical channels are an interesting solution Multiple λs in a single waveguide more data BW & WDM routing Better energy/distance, bandwidth/area and bandwidth-distance We need an electrical-to-optical interface Use a bridge chip face-bonded to a CPU or mem controller Optical devices & waveguides on bridge chips can point down Optical proximity communication w/ face-to-face couplers Cunningham et al., IEEE Group IV Photonics, 2008 Krishnamoorthy et al., Proceedings of the IEEE,

9 The macrochip a server-on-a-chip vision Aggregate the hybrid chips onto a substrate with embedded waveguides Silicon lattice carrying CPUs and DRAMs With a very rich waveguide network connecting the sites Bridges perform OE/EO and couple optically to lattice Silicon lattice w/ waveguides Ho et al., IEEE Design and Test, 2010 Krishnamoorthy et al., Proc. IEEE, 2009 CPUs or DRAM stacks Optical bridges 9

10 And the most important part: the link The goal is to hit 0.3 pj/b (on-chip) link energy consumption Commercial electronic links today around pj/b Including laser conversion efficiency, we want to hit <1pJ/bit We have demonstrated Tx+Rx< 0.35 pj/b thus far (2011) Zheng et al., OFC Postdeadline 2011 (JSTQE 2012 accepted) Good start but miles to go before we sleep 10