ELCT 501: Digital System Design

Transcription

1 ELCT 501: Digital System Lecture 8: Pipelining Dr. Mohamed Abd El Ghany,

2 Pipelining: Its Natural! Laundry Example Ann, brian, cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes Dryer takes 40 minutes folder takes 20 minutes How long to do laundry? 2

3 Sequential Laundry Sequential laundry takes 6 hours for 4 loads If they learned pipelining, how long would laundry take? 3

4 Pipelining Laundry: Start Work ASAP Pipelining laundry takes 3.5 hours for loads 4

5 Pipelining Lessons Pipelining doesn t help latency of single task, it helps throughput of entire workload Pipeline rate limited by slowest pipeline stage Multiple tasks operating simultaneously Potential speedup= number pipe stages Unbalanced lengths of pipe stages reduces speedup Time to fill pipeline and time to drain it reduces speedup 5

6 Pipeline Throughput and Latency IF ID EX MEM WB 5 ns 4 ns 5 ns 10 ns 4 ns Consider the pipeline above with the indicated delays. We want to know what is the pipeline throughput and the pipeline latency. Pipeline throughput: instructions completed per second. Pipeline latency: how long does it take to execute a single instruction in the pipeline. COMM 704:Communication Systems Department of Electronics and Electrical Engineering 6

7 Pipeline Throughput and Latency IF ID EX MEM WB 5 ns 4 ns 5 ns 10 ns 4 ns Pipeline throughput: how often an instruction is completed. 1instr 1instr 1instr / max / max lat( IF ), lat( ID), lat( EX ), lat( MEM 5ns,4ns,5ns,10ns,4ns /10ns ( ignoring pipeline register overhead) ), lat( WB) Pipeline latency: how long does it take to execute an instruction in the pipeline. L lat( IF ) lat( ID) lat( EX ) lat( MEM COMM 704:Communication Systems 5ns 4ns 5ns 10ns 4ns 28ns Department of Electronics and Electrical Engineering ) lat( WB) Is this right? 7

8 Pipeline Throughput and Latency IF ID EX MEM WB 5 ns 4 ns 5 ns 10 ns 4 ns Simply adding the latencies to compute the pipeline latency, only would work for an isolated instruction I1 IF I2 ID IF I3 EX ID IF I4 MEM EX ID EX IF ID WB L(I1) = 28ns MEM WB L(I2) = 33ns MEM WB L(I3) = 38ns EX MEM WB L(I5) = 43ns We are in trouble! The latency is not constant. This happens because this is an unbalanced pipeline. The solution is to make every state the same length as the longest one. COMM 704:Communication Systems Department of Electronics and Electrical Engineering 8

9 Definitions Latency The delay from when an input is establish until the output associated with that input becomes valid Sequential laundry = = 90 mins Pipelining laundry = = 120 mins (at steady state) Throughput The rate of which inputs or outputs are processed Sequential laundry = 1/90 outputs/mins Pipelining laundry = 1/40 outputs/mins (at steady state) Sequential laundry Pipelining laundry 9

10 Pipelining Combinational Logic Non-Pipelined Latency = 500ps Throughput = 2GHz Pipelined A and B process input X(T2) while C process the intermediate results for input X(T1) Latency = 600ps Throughput = 3.3GHz 10

11 Pipe stages Multiple- Clock Cycle Pipeline Diagram Clock cycles T i T i+1 T i+2 T i+3 Input X(T i ) X(T i+1 ) X(T i+2 ) X(T i+3 ) A reg B reg A(X(T i )) B(X(T i )) A(X(T i+1 )) B(X(T i+1 )) C reg C[A(X(T i )), B(X(T i ))] A(X(T i+2 )) B(X(T i+2 )) C[A(X(T i+1 )), B(X(T i+1 ))] C[A(X(T i+2 )), B(X(T i+2 ))] 11

12 Stage 2 Stage 1 Pipeline Example x y z w x y z w clk + s + + Longest path is 2+2 =4ns 2ns clk + R1 + s R2 + Pipeline register Longest path is only 2ns S= x + y + z+ w 12

13 Pipeline Example So minimum clock period is 4ns So minimum clock period is 2ns clk clk S S(0) S(1) S S(0) S(1) 13

14 Pipeline Example Datapath on left has critical path of 4ns, so fasted clock period is 4ns Can read new data, add and write data to S every 4ns Datapath on right has critical path of only 2ns So can read new data every 2ns- sort of doubled performance So pipelining the above system Doubling the throughput, from 1 item/4ns, to 1 item/2ns Latency stayed the same: 4ns (sometimes it may increase) 14