ECE331: Hardware Organization and Design

Transcription

1 ECE331: Hadwae Oganization and Design Lectue 16: Pipelining Adapted fom Compute Oganization and Design, Patteson & Hennessy, UCB

2 Last time: single cycle data path op System clock affects pimaily the Pogam Counte ECE331: Pipelining 2

3 Oveview Single-cycle MIPs datapath pesented so fa Not ovely efficient. Components of the datapath can be used moe efficiently Idea! Put egistes between stages of the datapath Clock used to update egiste values All stages pefom an opeation on evey clock cycle Pipelined datapath: the basis fo almost all moden micopocessos! ECE331: Pipelining 3

4 Speeding up though pipelining Ann, Bian, Cathy, Dave each have one load of clothes to wash, dy, and fold Washe takes 30 minutes Dye takes 30 minutes Folde takes 30 minutes Stashe takes 30 minutes to put clothes into dawes A B C D ECE331: Pipelining 4

5 T a s k O d e Sequential Laundy A B C D 6 PM AM Sequential laundy takes 8 hous fo 4 loads If they leaned pipelining, how long would laundy take? ECE331: Pipelining Time

6 Pipelined Laundy: Stat wok ASAP T a s k O d e 12 2 AM 6 PM A B C D Time Pipelined laundy takes 3.5 hous fo 4 loads! ECE331: Pipelining 6

7 Pipelining Lessons T a s k O d e A B C D 6 PM Time Pipelining doesn t help latency of single task, it helps thoughput of entie wokload Multiple tasks opeating simultaneously using diffeent esouces Potential speedup = Numbe pipe stages Pipeline ate limited by slowest pipeline stage Unbalanced lengths of pipe stages educes speedup Time to fill pipeline and time to dain it educes speedup ECE331: Pipelining 7

8 MIPs Datapath Datapath contains 5 stages Instuction fetch (IF), Decode (ID), Execute (EX), Memoy (Mem), Witeback (W) PC Instuction Memoy Registes A L U Data Memoy Stage 1 (IF) Stage 2 (ID) Stage 3 (EX) Stage 4 (Mem) Stage 5 (W) Can I pipeline the MIPs stages? ECE331: Pipelining 8

9 Pipelining Instuctions Time (in cycles) Instuction IF ID EX M W IF ID EX M W IF ID EX M W IF ID EX M W Fetch = 200 ps Decode = 100 ps Execute = 200 ps Memoy = 200 ps Wite back = 100 ps IF ID EX M W IF ID EX M W What is the latency fo this pipeline? ECE331: Pipelining 9

10 Pipeline Pefomance Single-cycle (T c = 800ps) Pipelined (T c = 200ps) ECE331: Pipelining 10

11 Why Pipeline? Because the esouces ae thee! Time (clock cycles) I n s t. O d e Inst 1 Inst 2 Inst 3 Inst 4 Inst 5 Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg ECE331: Pipelining 11

12 MIPS Pipelined Datapath State egistes between pipeline stages to isolate them IF:IFetch ID:Dec EX:Execute MEM: MemAccess WB: WiteBack Inst 5 Inst 4 Inst 3 Inst 2 Inst 1 Add PC 4 Instuction Memoy Read Addess IFetch/Dec Read Add 1 Registe Read Read Add Data 2 1 File Wite Add Wite Data Read Data 2 Dec/Exec Shift left 2 Add Exec/Mem Addess Wite Data Data Memoy Read Data Mem/WB Sign 16 Extend 32 System Clock ECE331: Pipelining 12

13 Pipeline Hazads Data hazads: an instuction uses the esult of a pevious instuction (RAW) ADD R1, R2, R3 o SW R1, 4(R2) SUB R4, R1, R5 LW R3, 4(R2) Contol hazads: the addess of the next instuction to be executed depends on a pevious instuction BEQ R1,R2,CONT SUB R6,R7,R8 CONT: ADD R3,R4,R5 Stuctual hazads: two instuctions need access to the same esouce e.g., single memoy shaed fo instuction fetch and load/stoe ECE331: Pipelining 13

14 Stuctual Hazad Time (clock cycles) I n s t. lw Inst 1 Mem Reg Mem Reg Mem Reg Mem Reg Reading data fom memoy O d e Inst 2 Inst 3 Mem Reg Mem Reg Mem Reg Mem Reg Inst 4 Reading instuction fom memoy Mem Reg Mem Reg Fix with sepaate instuction and data memoies (I$ and D$) ECE331: Pipelining 14

15 Data Hazads Time (in cycles) IF ID EX M W Instuction IF ID EX M W Get data fom R1 Hee Wite Data to R1 Hee ADD R1, R2, R3 SUB R4, R1, R5 ECE331: Pipelining 15

16 One Way to handle a Data Hazad I n s t. add $1, stall By waiting intoducing stalls but impacts pefomace O d e stall stall sub $4,$1,$5 ECE331: Pipelining 16

17 I n s t. Additional Way to Fix a Data Hazad Time add $1, sub $4,$1,$5 by fowading O d e and $6,$1,$7 o $8,$1,$9 xo $4,$1,$5 ECE331: Pipelining 17

18 I n s t. Intenal data fowading Time add $1, sub $4,$1,$5 Fix data hazads by fowading esults to whee they ae needed O d e and $6,$1,$7 o $8,$1,$9 xo $4,$1,$5 ECE331: Pipelining 18 -to- fowading vs. full fowading

19 Fowading with Load-use Data Hazads Time I n s t. lw $1,4($2) sub $4,$1,$5 O d e and $6,$1,$7 o $8,$1,$9 xo $4,$1,$5 sub needs to stall Will still need one stall cycle even with fowading ECE331: Pipelining 19

20 Contol Hazad Time (in cycles) IF ID EX M W Instuction Destination Available Hee IF ID EX M W Need Destination Hee JR R25... XX: ADD... Simple solution: Flush Instuction fetch until banch esolved ECE331: Pipelining 20

21 Summay Pipelined pocessos ae fundamental. Spend the time to undestand why pipelining is impotant The use of pipelining geatly impoves micopocesso pefomance The clock fo micopocessos is about 3 GHz today Hazads can be a difficult concept Convince youself with examples Next-Next time: Contol hazads! ECE331: Pipelining 21