Chapter 3 & Appendix C Pipelining Part A: Basic and Intermediate Concepts

Transcription

1 CS359: Computer Architecture Chapter 3 & Appendix C Pipelining Part A: Basic and Intermediate Concepts Yanyan Shen Department of Computer Science and Engineering Shanghai Jiao Tong University

2 Parallel Processing 2

3 Outline C. Introduction to Pipelining How Pipeline is Implemented Pipeline Hazards Exceptions Handling ulticycle Operations 3

4 Processor Performance Performance of single-cycle processor is limited by the long critical path delay The critical path limits the operating clock frequency Can we do better? New semiconductor technology will reduce the critical path delay by manufacturing smallsized transistors Core 2 Duo is manufactured with 65nm technology Core i7 is manufactured with 5nm technology Next semiconductor technology is nm technology Can we increase the processor performance with a different microarchitecture? Yes! Pipelining

5 Revisiting Performance Laundry Example Ann, Brian, Cathy, Dave each has one load of clothes to wash, dry, and fold Washer takes 3 minutes Dryer takes minutes Folder takes 2 minutes A B C D 5

6 Sequential Laundry 6 P idnight Time T a s k O r d e r A B C D Response time: 9 mins Throughput:.67 tasks / hr (= 9mins/task, 6 hours for loads) 6

7 Pipelined Laundry T a s k O r d e r A B C D 6 P idnight Time 3 2 Notes Pipelining doesn t help latency (response time) of a single task Pipelining helps throughput of entire workload ultiple tasks operating simultaneously Potential speedup = # of pipeline stages Unbalanced lengths of pipeline stages reduce speedup Response time: 9 mins Throughput:. tasks / hr (= 52.5 mins/task, 3.5 hours for loads) 7

8 Pipelining Improve performance by increasing instruction throughput Fetch ister File Access () Operation Access ister Access () 2ns ns 2ns 2ns ns Sequential Execution Pipelined Execution Program execution order Time (in instructions) lw $, ($) lw $2, 2($) lw $3, 3($) Program execution Time order (in instructions) lw $, ($) lw $2, 2($) lw $3, 3($) fetch fetch 2 ns ns access fetch 8 ns fetch 2 ns fetch access access access 2 ns 2 ns 2 ns 2 ns 2 ns access fetch 8 ns... 8

9 Pipelining (Cont.) ultiple instructions are being executed simultaneously Program execution Time order (in instructions) lw $, ($) fetch access lw $2, 2($) 2 ns fetch access lw $3, 3($) 2 ns fetch access fetch access fetch access fetch access fetch access fetch access fetch access 9

10 Pipelining (Cont.) Pipeline Speedup Time to execute an instruction pipeline = Time to execute an instruction sequential Number of stages If not balanced, speedup is less Speedup comes from increased throughput the latency of instruction does not decrease

11 Outline Introduction to Pipelining C.2 How Pipeline is Implemented Pipeline Hazards Exceptions Handling ulticycle Operations

12 Basic Idea IF: fetch u x ID: decode/ file read EX: Execute/ address calculation E: emory access : back ress isters 2 u x ress u x 6 What do we have to add to actually split the path into stages? 2

13 Basic Idea IF: fetch u x ID: decode/ file read EX: Execute/ address calculation E: emory access : back ress isters 2 u x ress u x 6 clock D Q F/F Q D Q F/F Q D Q F/F Q D Q F/F Q 3

14 Graphically Representing Pipelines Time lw IF ID EX E add IF ID EX E Shading indicates the unit is being used by the instruction Shading on the right half of the file (ID or ) or means the element is being read in that stage Shading on the left half means the element is being written in that stage

15 Pipelined path u x IF/ID ID/EX EX/E E/ ress isters 2 u x ress u x 6 5

16 lw: Fetch (IF) fetch IF/ID ID/EX EX/E E/ ress isters 2 ress 6 6

17 lw: Decode (ID) decode IF/ID ID/EX EX/E E/ ress isters 2 ress 6 7

18 lw: Execution (EX) Execution IF/ID ID/EX EX/E E/ ress isters 2 ress 6 8

19 lw: emory (E) emory IF/ID ID/EX EX/E E/ ress isters 2 ress 6 9

20 lw: back () back IF/ID ID/EX EX/E E/ ress isters 2 ress 6 2

21 sw: emory (E) emory IF/ID ID/EX EX/E E/ ress isters 2 ress 6 2

22 sw: back (): do nothing back IF/ID ID/EX EX/E E/ ress isters 2 ress 6 22

23 Corrected path (for lw) IF/ID ID/EX EX/E E/ ress isters 2 ress 6 23

24 Pipelining Example add $, $5, $6 lw $3, 2($) add $2, $3, $ sub $, $2, $3 lw $, 2($) IF/ID ID/EX EX/E E/ ress isters 2 ress 6 2

25 Pipeline Control u x Src Note that in this implementation, the branch is resolved in the E stage IF/ID ID/EX EX/E E/ Branch ress isters 2 [5 ] 6 Src u x 6 control ress em em emto u x [2 6] [5 ] u x Op Dst 25

26 Pipeline Control What needs to be controlled in each stage (IF, ID, EX, E, )? IF: fetch and increment ID: decode and operand fetch from file and/or immediate EX: Execution stage Dst op[:] Src A: emory stage Branch em em : back emto (note that this signal is in ID stage) 26

27 Pipeline Control Extend pipeline s to include control information created in ID stage Pass control signals along just like the Execution/ress Calculation stage control lines emory access stage control lines -back stage control lines Dst Op Op Src Branch em em write em to R-format lw sw X X beq X X Control EX IF/ID ID/EX EX/E E/ 27

28 path with Control Src u x Control ID/EX EX/E E/ IF/ID EX ress isters 2 u x Src Branch em ress emto u x 6 [5 ] 6 control em [2 6] [5 ] u x Dst Op 28

29 path with Control IF: lw $, 9($) Src Control ID/EX EX/E E/ IF/ID EX ress isters 2 Src Branch em ress emto [5 ] 6 6 control em [2 6] [5 ] Op Dst 29

30 path with Control IF: sub $, $2, $3 ID: lw $, 9($) Src lw Control ID/EX EX/E E/ IF/ID E X ress isters 2 Src Branch em ress emto [5 ] 6 6 control em [2 6] [5 ] Op Dst 3

31 path with Control IF: and $2, $, $5 ID: sub $, $2, $3 EX: lw $, 9($) Src IF/ID sub Control ID/EX EX EX/E E/ ress isters 2 Src Branch em ress emto [5 ] 6 6 control em [2 6] [5 ] Op Dst 3

32 path with Control IF: or $3, $6, $7 ID: and $2, $, $5 EX: sub $, $2, $3 E: lw $, 9($) Src IF/ID and Control ID/EX EX EX/E E/ ress isters 2 Src Branch em ress emto [5 ] 6 6 control em [2 6] [5 ] Op Dst

33 path with Control IF: add $, $8, $9 Src ID: or $3, $6, $7 EX: and $2, $, $5 E: sub $,.. : lw $, 9($) IF/ID or Control ID/EX EX EX/E E/ ress isters 2 Src Branch em ress emto [5 ] 6 6 control em [2 6] [5 ] Op Dst 33

34 path with Control IF: xxxx ID: add $, $8, $9 EX: or $3, $6, $7 E: and $2 Src : sub $,.. IF/ID add Control ID/EX EX EX/E E/ ress isters 2 Src Branch em ress emto [5 ] 6 6 control em [2 6] [5 ] Op Dst 3

35 path with Control IF: xxxx ID: xxxx EX: add $, $8, $9 E: or $3,.. Src : and $2 IF/ID Control ID/EX EX EX/E E/ ress isters 2 Src Branch em ress emto [5 ] 6 6 control em [2 6] [5 ] Op Dst 35

36 path with Control IF: xxxx ID: xxxx EX: xxxx E: add $,.. Src : or $3 IF/ID Control ID/EX EX EX/E E/ ress isters 2 Src Branch em ress emto [5 ] 6 6 control em [2 6] [5 ] Op Dst 36

37 path with Control IF: xxxx ID: xxxx EX: xxxx E: xxxx Src : add $.. Control ID/EX EX/E E/ IF/ID EX ress isters 2 Src Branch em ress emto [5 ] 6 6 control em [2 6] [5 ] Op Dst 37