PROGRAMMABLE PERIPHERAL INTERFACE (PPI) -8255

Transcription

1 PROGRAMMABLE PERIPHERAL INTERFACE (PPI) is a general purpose programmable device used for data transfer between processor and I/O devices. It has 3 programmable I/O ports (PA,PB &PC) and port operation (IN/OUT Port) is defined by control word in the control word register. Ports are operated in two modes: i) I/O modes: Mode 0, Mode 1,& Mode 2 Ii) BSR (Bit set/reset) mode

2 About 8255 PPI has 40 pins and it has three distinct modes of operation. Port A (PA7-PA0) :8 pins Port B (PB7-PB0) :8 pins Port C (Pc: Upper: PC7-PC4) : 4 pins Port C (Pc: Lower: PC3-PC)) : 4 pins Data Bus (D7-D0) : 8 pins Control signals : 6 pins VCC and Gnd : 2 pins

3 Pin Diagram

4 Pin name Pin names and function No.of pins I/O functions PA0-PA7 8 i/o Tristate PB0-PB7 8 i/o Tristate PC0-PC7 8 i/o Tristate D0-D7 8 i/o Tristate Port can be configured either input or output by software Port has output latch buffer and input buffer PA can be programmed by mode 0, mode 1, mode 2. PB can be programmed by mode 0 and mode 1. PC can be programmed by bit set/reset operation. Port C can be divided into two 4 bit ports namely PC7-PC4 & PC3-PCO and used for control signals to PA and PB Used for data transfer with MPU Transfer of control words to PPI Read status information from PPI

5

6 8255 Block Diagram

7

8 Group A and Group B control: Group A and B get the Control Signal from CPU and send the command to the individual control blocks. Group A send the control signal to port A and Port C (Upper) PC7-PC4. Group B send the control signal to port B and Port C (Lower) PC3-PC0.

9 FOR I/O MODE: The control word mode format for I/O as shown in figure D7 D6 D5 D4 D3 D2 D1 D0 Mode set 1: i/o MODE 0: BSR mode Group A Port C Upper 1=Input 0=Output Port A 1=Input 0=Output Mode selection 00=mode 0 01=mode 1 1x=mode 2 Group B Port C Lower 1=Input 0=Output Port B 1=Input 0=Output Mode selection 0=mode 0 1=mode 1

10 operation modes: i) I/O modes (M0,M1,&M2) ii) BSR (Bit set/reset) mode BIT SET/RESET MODE: The PORT C can be Set or Reset by sending OUT instruction to the CONTROL registers.

11 Mode 1:Handshake interrupt i/p port When i/p device has data to send it checks if IBF (input buffer full) signal is 0. If 0, it sends data on PA/PB7-0 and activates STB* (Strobe) signal. (STB* is active low. ) When STB* goes high, the data enters the port and IBF gets activated. If the Port interrupt is enabled, INT is activated. This interrupts the processor. Processor reads the port during the ISS. Then IBF and INT get deactivated. 11

12 82C55: Mode 1 Strobed Input INTE A Controlled by bit set / reset of PC4. INTE B Controlled by bit set / reset of PC2.

13 Handshake interrupt o/p port When o/p device wants to receive data it checks if OBF* (output buffer full) signal is 0. If 0, it receives data on PB7-0 and activates ACK* (Acknowledge) signal. ACK* is active low. When ACK* goes high, the data goes out of the port and OBF* is set to 1. If the Port interrupt is enabled, INT is activated. This interrupts the processor. Processor sends another byte to the port during the ISS. Then OBF* and INT are reset to 0. 13

14 Mode 1 o/p mode INTE A Controlled by bit set/reset of PC6. INTE B Controlled by bit set/reset of PC2.

15 82C55: Mode 2 Bi-directional Operation:

16

17

18 82C55: Mode 2 Bi-directional Operation INTR : Interrupt request is an output that requests an interrupt. ~OBF : Output Buffer Full is an output indicating that that output buffer contains data for the bi-directional bus. ~ACK : Acknowledge is an input that enables tri-state buffers which are otherwise in their high-impedance state. ~STB : The strobe input loads data into the port A latch.

19 82C55: Mode 2 Bi-directional Operation IBF : Input buffer full is an output indicating that the input latch contains information for the external bidirectional bus. INTE : Interrupt enable are internal bits that enable the INTR pin. BIT PC6(INTE1) and PC4(INTE2). PC2,PC1,PC0 : These port C pins are general-purpose I/O pins that are available for any purpose.

20 FOR BIT SET/RESET MODE (Port C only) This is bit set/reset control word format. D7 D6 D5 D4 D3 D2 D1 D0 X X X Don t care BIT SET/RESET 1=SET 0=RESET Bit select for Port C (Pc0-Pc7) B B B2 BIT SET/RESET FLAG =0 Active

21 The control word for both mode is same. Bit D7 is used for specifying whether word loaded in to Bit set/reset mode or Mode definition word. D7=1=Mode definition mode. D7=0=Bit set/reset mode. PC0-PC7 is set or reset as per the status of D0. A BSR word is written for each bit Example: PC3 is Set then control register will be 0XXX0111. PC4 is Reset then control register will be 0XXX X is a don t care.

22

23 8259A PROGRAMMABLE INTERRUPT CONTROLLER

24

25 8259A PIC FEATURES Manage 8 interrupts according to the instructions written into the control registers Vector location can be assigned anywhere in the memory map. However all the 8 interrupts are spaced at an interval of four to eight locations. Resolve 8 levels of interrupt priorities in variety of modes. Be expanded to 64 priority levels by cascading additional 8259As. Compatible with 8-bit as well as 16-bit processors.

26 8259A PIC- PIN DIGRAM

27 8259A PIC- BLOCK DIAGRAM

28

29

30

31

32

33

34

35

36

37

38 8259A PIC- CASCADE BUFFER/ COMPARATOR Slave Program/ Enable Buffer: Used to specify whether 8259 is to act as a master or a slave High Master Low Slave In Non-Buffered Mode, this pin is used to specify whether 8259 is to act as a master or a slave. In Buffered mode this pin is used as an output to enable the data bus buffer of the system.

39 8259A- Priority Modes FULLY NESTED MODE: General purpose mode. All IRs are arranged from highest to lowest. IR0 Highest IR7 Lowest In addition any IR can be assigned the HP in this mode; the priority sequence will then begin at that IR IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR (LP) 0 (HP) 1 2 3

40 AUTOMATIC ROTATION MODE: In this mode, a device after being serviced, receives the lowest priority. Assuming that the IR2 has just been serviced, it will receive the 7 th priority IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR SPECIFIC ROTATION MODE: Similar to automatic rotation mode, except that the user can select any IR for the lowest priority, thus fixing all other priorities.

41 End of Interrupt (EOI) After the completion of interrupt service, the corresponding ISR bit needs to be reset to update the information in the ISR. This is called EOI command. It can be issued in three formats. Non Specific EOI: When this command send to the 8259 PIC, it resets the highest priority ISR bit. Specific EOI: This command specifies which ISR bit to reset Automatic EOI: In this mode no command is necessary. During the third INTA* the ISR bit is reset.

42 Programming of 8259A can be initialized with four ICW and two OCW. ICW1 & ICW2 are Compulsory command Words in the initialization sequence. ICW3 & ICW4 are Optional. ICW3 is read only when more than one 8259 used in the system ( SNGL bit in ICW1 is 0).

43 ADI=1 for 8086 based system For 8086 Don t Care p

44

45

46

47

48 8253/8254 Programmable counter / timer The Intel 8253 and 8254 are Programmable Interval Timers (PITs), which perform timing and counting functions using three 16-bit counters. Compatible with 8085/86 processor. The Intel 82c54 variant handles up to 10 MHz clock signals. The timer interrupt is usually assigned to IRQ-0 (highest priority hardware interrupt) because of the critical function it performs and because so many devices depend on it.

49

50

51 Intel 8253/54 : Programmable counter / timer chip

52 3 counters ;Counter #0, #1, #2 Each counter is identical, and each consists of a 16-bit, pre-settable, down counter. Each is fully independent and can be easily read by the CPU. Each counter is operated simultaneously but in different mode condition (M0,M1,M2,M3,M4, & M5) When the counter is read, the data within the counter will not be disturbed. This allows the system or your own program to monitor the counter's value at any time, without disrupting the overall function of the 8253.

53 Data Bus: This tri-state, bi-directional, 8-bit buffer is used to interface the 8253/54 to the system data bus. The Data bus buffer has three basic functions. 1. Programming the modes of 8253/ Loading the count registers. 3. Reading the count values A1 A0 Operation 0 0 Counter Counter Counter Control word register

54 Counter operation To operate a counter, a desired 16-bit count is loaded in its register and, on command, it begins to decrement the count until it reaches 0. At the end of the count, it generates a pulse that can be used to interrupt the CPU. Control Word Register (CWR) This internal register is used to write information to, prior to using the device. This register is addressed when A0 and A1 inputs are logical 1's. The data in the register controls the operation mode and the selection of either binary or BCD ( binary coded decimal ) counting format. The register can only be written to. You can't read information from the register.

55 Programming of 8253 (CWR)

56 Read operation (performed by CPU) In event counters, it is necessary to read the value of the count in process. This is done by three methods Simple read operation (Rw1: Rw2) Counter Latch Command (RW1/Rw2:0/0; Read Back command ( Available in 8254)

57 CWR for read back command

58 Counter status format

59 Modes of opertaion Mode 0 Interrupt on terminal count Mode 1 H/W retriggerable one shot Mode 2 Rate generator Mode 3 Square wave generator Mode 4 S/W triggered strobe Mode 5 H/W triggered strobe

60 `The OUT pin is set low after the Control Word is written, and counting starts one clock cycle after the COUNT programmed. OUT remains low until the counter reaches 0, at which point OUT will be set high until the counter is reloaded or the Control Word is written. The Gate signal should remain active high for normal counting. If Gate goes low counting gets terminated and current count is latched till Gate pulse goes high again.

61 In this mode 8253 can be used as Monostable Multivibrator. GATE input is used as trigger input. OUT will be initially high. OUT will go low on the Clock pulse following a trigger to begin the one-shot pulse, and will remain low until the Counter reaches zero. OUT will then go high and remain high until the CLK pulse after the next trigger.

62 In this mode, the device acts as a divide-by-n counter, which is commonly used to generate a real-time clock interrupt. Like other modes, counting process will start the next clock cycle after COUNT is sent. OUT will then remain high until the counter reaches 1, and will go low for one clock pulse. OUT will then go high again, and the whole process repeats itself.

63

64

65

66

67 8237DMA CONTROLLER

68 Introduction: Direct memory access (DMA) is a method that allows an input/output (I/O) device to send or receive data directly to or from the main memory, bypassing the CPU to speed up memory operations. The process is managed by a chip known as a DMA controller(dmac).

69 Basic DMA Operation: Two control signals are used to request and acknowledge a direct memory access (DMA) transfer in the microprocessorbased system. The HOLD signal as an input(to the processor) is used to request a DMA action. The HLDA signal as an output that acknowledges the DMA action. When the processor recognizes the hold, it stops its execution and enters hold cycles. HLDA becomes active to indicate that the processor has placed its buses at high-impedance state.

70 Basic DMA Definitions: Direct memory accesses normally occur between an I/O device and memory without the use of the microprocessor. A DMA read transfers data from the memory to the I/O device. A DMA write transfers data from an I/O device to memory. The system contains separate memory and I/O control signals. Hence the Memory & the I/O are controlled simultaneously The DMA controller provides memory with its address, and the controller signal selects the I/O device during the transfer. Data transfer speed is determined by speed of the memory device or a DMA controller.

71 The 8237 DMA Controller 8237 is a four-channel device compatible with 8086/8088, adequate for small systems. Each channel is capable of addressing a full 64K-byte section of memory. Expandable to any number of DMA channel inputs 8237 is capable of DMA transfers at rates up to 1.6MB per second.

72 CPU having the control over the bus: When DMA operates:

73 Programmable DMA controller. (a) Block diagram and (b) pin-out. 7

74

75

76 8237 Internal Registers CAR The current address register holds a 16-bit memory address used for the DMA transfer. Each channel has its own current address register for this purpose. When a byte of data is transferred during a DMA operation, CAR is either incremented or decremented depending on how it is programmed.

77 CWCR The current word count register programs a channel for the number of bytes to transferred during a DMA action. CR The command register programs the operation of the 8237 DMA controller. The register uses bit position 0 to select the memory-tomemory DMA transfer mode. Memory-to-memory DMA transfers use DMA channel 0 to hold the source address DMA channel 1 holds the destination address

78 command register. 12

79 BA and BWC The base address (BA) and base word count (BWC) registers are used when auto-initialization is selected for a channel. In auto-initialization mode, these registers are used to reload the CAR and CWCR after the DMA action is completed.

80 MR The mode register programs the mode of operation for a channel. Each channel has its own mode register as selected by bit positions 1 and 0. Remaining bits of the mode register select operation, auto-initialization, increment/decrement, and mode for the channel 14

81 BR The bus request register is used to request a DMA transfer via software. very useful in memory-to-memory transfers, where an external signal is not available to begin the DMA transfer 15

82 MRSR The mask register set/reset sets or clears the channel mask. if the mask is set, the channel is disabled the RESET signal sets all channel masks to disable them 16

83 MSR The mask register clears or sets all of the masks with one command instead of individual channels, as with the MRSR. 17

84 SR The status register shows status of each DMA channel. The TC bits indicate if the channel has reached its terminal count (transferred all its bytes). When the terminal count is reached, the DMA transfer is terminated for most modes of operation. The request bits indicate whether the DREQ input for a given channel is active. 18

85 Master clear Acts exactly the same as the RESET signal to the As with the RESET signal, this command disables all channels Clear mask register Enables all four DMA channels. Clear the first/last flip-flop Clears the first/last (F/L) flip-flop within The F/L flip-flop selects which byte (low or high order) is read/written in the current address and current count registers. if F/L = 0, the low-order byte is selected if F/L = 1, the high-order byte is selected Any read or write to the address or count register automatically toggles the F/L flip-flop.

86 Memory-to-memory transfer is much more powerful than the automatically repeated MOVSB instruction. most modern chip sets do not support the memory-tomemory feature 8237 requires only 2.0 µs per byte, which is over twice as fast the existing data transfer. 20

87 8251 USART (Universal Synchronous Asynchronous Receiver Transmitter) The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data communication. As a peripheral device of a microcomputer system, the 8251 receives parallel data from the CPU and transmits serial data after conversion. This device also receives serial data from the outside and transmits parallel data to the CPU after conversion.

88 Serial data transmission is classified as Simplex: the data are transmitted in only one direction. Ex. Transmission from computer to printer Half Duplex: Data are transmitted in both direction but not simultaneously. Ex. Walky talky Full Duplex: Data are transmitted in both direction simultaneously. ex. Telephone

89 Syn and asycn transmission a) Synch format b) asynch format

90 Serial bit format Baud: number of signal changes per second; bits/second. Baud Rate: Bits transmitted per second ASCII character I (49H) to be transmitted at 1200 baud; 11 bits includes 1 start, 8 data and 2 stop bits. start bit +7 bits for ASCII + parity bit + 2 stop bits Transmission time for one bit = 1/1200 = 0.83 ms Time for transmitting one ASCII = 9.13 ms

91 H/W controlled serial I/O SW control has following requirements: An input port and an output port are required for interfacing. In transmission, MPU converts parallel data into serial bits. In reception, MPU converts bits from serial to parallel. Trans and receiver must match the time delay. In HW control has serial IO, all these features are incorporated in one chip, like 8251A (USART).

92

93 8251 BLOCK DIAGRAM

94 The transmitter section The transmitter section accepts parallel data from CPU and converts them into serial data. The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits. When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register. If buffer register is empty, then TxRDY is goes to high. If output register is empty then TxEMPTY goes to high. The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART. The clock frequency can be 1,16 or 64 times the baud rate.

95

96 Receiver section The receiver section accepts serial data and convert them into parallel data The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data. The CPU reads the parallel data from the buffer register. RxD: bits are received serially on this line RxC: controls the rate at which bits are received by USART. In asych mode, it can be 1, 16 or 64 times the baud. RxRDY : When the input register loads a parallel data to buffer register, the RxRDY line goes high. RxRDY Can be used either to indicate the status or to interrupt MPU. During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission. During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character.

97 Control logic and registers CS C/D RD WR Function MPU writes in the control register MPU reads status register MPU outputs data to data buffer MPU reads data from data buffer 1 X X X USART is not selected

98 Data comm over telephone: MODEM control The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines. This unit takes care of handshake signals for MODEM interface.

99 MODEM signals DSR (Data Set Ready : i/p) This is an input port for MODEM interface. The input status of the terminal can be recognized by the CPU reading status words. DTR (Data Terminal : o/p) This is an output port for MODEM interface. It is possible to set the status of DTR by a command. CTS (clear to send : i/p) This is an input terminal for MODEM interface which is used for controlling a transmit circuit. RTS (Request to send: o/p) This is an output port for MODEM interface. It is possible to set the status RTS by a command. Data Carrier Detect (DCD)

100 Serial I/O standards Standard is used to interface between host system (DTE: Data terminal equipment) and peripherals system(dce:data Communication Equipment) RS 232 (Recommended standard) is serial I/O cable

101 RS 232C Speed 20Kbaud. Distance 50 ft. data signal; Logic zero: +3v to +15V Logic one: -3v to -15V Other signals are TTL.(timing and control signals and ground signal) 25 pins

102 Interfacing RS232 terminal using 8251A

103 Minimum interface with RS232C The null modem cable is frequently called a crossover cable. It is used to allow two serial Data Terminal Equipment (DTE) devices to communicate with each other without using a modem or a Data Communications Equipment (DCE) device in between.

104 Other standard Specs RS232C RS422A RS423A Speed 20kbd 10Mbd 100kbd Distance 50ft 4000ft 4000ft Logic 0 3 to 15 B>A 4 to 6V Logic 1-3 to -15 B<A -4 to -6 Rcvr input volt ±15V ±7 ±12

105 RS 232C

106 Initializing 8251A Mode, baud, stop bits, parity, etc. Control word: a) mode word b) command word After a reset operation, a mode word must be written in the control register (16 bit register) followed by a command word. Command word can be changed at any time during operation, but mode can only be changed only after a reset operation. It can be reset using internal reset bit (D 6 ) in the command word.

107 Control Words There are two types of control word. 1. Mode instruction (setting of function) 2. Command (setting of operation) 1) Mode Instruction Mode instruction is used for setting the function of the Items set by mode instruction are as follows: Synchronous/asynchronous mode Stop bit length (asynchronous mode) Character length Parity bit Baud rate factor (asynchronous mode) Internal/external synchronization (synchronous mode) Number of synchronous characters (Synchronous mode) The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of synchronous mode, it is necessary to write one-or two byte sync characters. If sync characters were written, a function will be set because the writing of sync characters constitutes part of mode instruction.

108

109

110 2) Command Command is used for setting the operation of the It is possible to write a command whenever necessary after writing a mode instruction and sync characters. Items to be set by command are as follows: Transmit Enable/Disable Receive Enable/Disable DTR, RTS Output of data. Resetting of error flag. Sending to break characters Internal resetting Hunt mode (synchronous mode)

111

112

113

114 Pin description of 8251 D 0 to D 7 (l/o terminal) This is bidirectional data bus which receive control words and transmits data from the CPU and sends status words and received data to CPU. RESET (Input terminal) A "High" on this input forces the 8251 into "reset status." The device waits for the writing of "mode instruction." The min. reset width is six clock inputs during the operating status of CLK. CLK (Input terminal) CLK signal is used to generate internal device timing. CLK signal is independent of RXC or TXC. However, the frequency of CLK must be greater than 30 times the RXC and TXC at Synchronous mode and Asynchronous "x1" mode, and must be greater than 5 times at Asynchronous "x16" and "x64" mode. WR (Input terminal) This is the "active low" input terminal which receives a signal for writing transmit data and control words from the CPU into the RD (Input terminal) This is the "active low" input terminal which receives a signal for reading receive data and status words from the 8251.

115 C/D (Input terminal) This is an input terminal which receives a signal for selecting data or command words and status words when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high, command word or status word will be accessed. CS (Input terminal) This is the "active low" input terminal which selects the 8251 at low level when the CPU accesses. Note: The device won t be in "standby status"; only setting CS = High. TXD (output terminal) This is an output terminal for transmitting data from which serial-converted data is sent out. The device is in "mark status" (high level) after resetting or during a status when transmit is disabled. It is also possible to set the device in "break status" (low level) by a command. TXRDY (output terminal) This is an output terminal which indicates that the 8251is ready to accept a transmitted data character. But the terminal is always at low level if CTS = high or the device was set in "TX disable status" by a command. Note: TXRDY status word indicates that transmit data character is receivable, regardless of CTS or command. If the CPU writes a data character, TXRDY will be reset by the leading edge or WR signal.

116 TXEMPTY (Output terminal) This is an output terminal which indicates that the 8251 has transmitted all the characters and had no data character. In "synchronous mode," the terminal is at high level, if transmit data characters are no longer remaining and sync characters are automatically transmitted. If the CPU writes a data character, TXEMPTY will be reset by the leading edge of WR signal. Note : As the transmitter is disabled by setting CTS "High" or command, data written before disable will be sent out. Then TXD and TXEMPTY will be "High". Even if a data is written after disable, that data is not sent out and TXE will be "High". After the transmitter is enabled, it sent out. (Refer to Timing Chart of Transmitter Control and Flag Timing) TXC (Input terminal) This is a clock input signal which determines the transfer speed of transmitted data. In "synchronous mode," the baud rate will be the same as the frequency of TXC. In "asynchronous mode", it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16 or 1/64 the TXC. The falling edge of TXC sifts the serial data out of the RXD (input terminal) This is a terminal which receives serial data.

117 RXRDY (Output terminal) This is a terminal which indicates that the 8251 contains a character that is ready to READ. If the CPU reads a data character, RXRDY will be reset by the leading edge of RD signal. Unless the CPU reads a data character before the next one is received completely, the preceding data will be lost. In such a case, an overrun error flag status word will be set. RXC (Input terminal) This is a clock input signal which determines the transfer speed of received data. In "synchronous mode," the baud rate is the same as the frequency of RXC. In "asynchronous mode," it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the RXC. SYNDET/BD (Input or output terminal) This is a terminal whose function changes according to mode. In "internal synchronous mode." this terminal is at high level, if sync characters are received and synchronized. If a status word is read, the terminal will be reset. In "external synchronous mode, "this is an input terminal. A "High" on this input forces the 8251 to start receiving data characters. In "asynchronous mode," this is an output terminal which generates "high level output upon the detection of a "break" character if receiver data contains a "lowlevel" space between the stop bits of two continuous characters. The terminal will be reset, if RXD is at high level. After Reset is active, the terminal will be output at low level.

118 Transmitter section TxD: serial bits are transmitted on this line. TxC: controls bit trans rate. Clk freq can be 1,16,64 times the baud. TxRDY: o/p signal,high indicates the trans buffer is empty and USRT ready to accept a byte. Signal is reset when data is loaded in the buffer. TxE: o/p signal High indicates that the O/P register is empty. Reset when a byte is transferred from buffer to o/p register.

119 Read/Write control logic: The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register. It monitors the data flow. This section has three registers and they are control register, status register and data buffer. The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers. When C/D(low) is high, the control register is selected for writing control word or reading status word. When C/D(low) is low, the data buffer is selected for read/write operation. When the reset is high, it forces 8251A into the idle mode. The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

120 Interfacing RS232 terminal using 8251A TxC is khz. Asycn mode with 9600 baud Character length = 7 bits, two stop bits No parity chck. Port add Data register: FEh Control/status register: FFh

121 Mode word: D 7 D 6 D 5 D 4 D 3 D 2 D 1 D =CAh Stop bits No parity 7 bits chr Baud= TxC/16=153.6k/16 = 9600 Command word (asynch mode): D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 X 0 X 1 X 0 X 1 =11h Prvnts Intrnal reset Err Rst Rcv Disbl Tr Enbl Status word: D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 X X X X X X X 1 =01h Tr rdy

122 Initialization intruction: SETUP: MVI A, CAh ; load mode word OUT FFh MVI A, 11h OUT FFh ; write mode word to control rgstr ; load command word ; enable trnsmitter STATUS: IN FFh ; read stats word ANI 01h ; mask all bits except D 0 JZ STATUS ; if D 0 = 0, Tr buffer is full, go back and wait

123 transmit Init bit cntr Snd strt bit Wait bit time Get chr into A o/p bit using D 0 Wait bit time Rotate nxt bit to D 0. Dcr bit cntr N Last bit? Add parity Snd stop bits return N rcv Rd o/p port N Strt bit? Y Wait ½ bit time Bit still low? Y Set bit cntr Clr data rgstr Wait bit time Rd i/p Save bit Redy to rcv nxt bit Dcr bit cntr N Last bit? Y Chk parity Wait for stop bits return

124 IIE - SAP

125 The keyboard display controller chip 8279 provides A set of four scan lines and eight return lines for interfacing keyboard IIE - SAP A set of eight output lines for interfacing display. Scan line are used to drive multiplexed 7 segment display

126 WHY 8279??? 8255 can be used in interfacing keyboards and displays. The disadvantages of this method of interfacing keyboard and display is that the processor has to refresh the display and check the status of the keyboard periodically using polling technique. Thus a considerable amount of CPU time is wasted, reducing the system operating speed. Intel s 8279 is a general purpose keyboard display controller that simultaneously drives the display of a system and interfaces a keyboard with the CPU, leaving it free for its IIE - SAP routine task.

127 IIE - SAP

128 IIE - SAP

129 IIE - SAP

130 IIE - SAP

131 IIE - SAP

132 IIE - SAP

133 IIE - SAP

134 IIE - SAP

135 Keyboard segment i)scans the keyboard detects key if any key is pressed ii) Key code is stored in 8x8 FIFO RAM data in FIFO RAM sends Interrupt signal to CPU CPU reads the key code stored in FIFO RAM 8279 Display segment vii) Then CPU writes the key code in 16x8 display RAM viii)display devices display the data in the display RAM IIE - SAP

136 KEYBOARD i) Scanned Keyboard ( 2 Key lock out /N key roll over) ii)strobed input mode iii)scanned sensor matrix mode MPU INTERFACE BLOCK DIA 8279 SCAN i) Encoded ii) Decoded MUX. DISPLAY (8 digit or 16 digit) i)left Entry ii) Right Entry IIE - SAP

137 2 Key lock out/n key roll over KEY DEBOUNCE When a key is pressed, a debounce logic comes into operation. Return Buffers and Keyboard De-bounce and Control section scans for a key closure row wise. If a key closer is detected, the keyboard debounce unit debounces the key entry (i.e. wait for 10 ms). When a key is pressed, a debounce logic comes into operation. After the debounce period (i.e. wait for 10 ms)., if the key continues to be detected, The code of key is directly transferred to the sensor RAM along with SHIFT and CONTROL key status. 2 key lock out: If two keys are pressed simultaneously within a debounce cycle, no key is recognized and no key code is stored in FIFO RAM till one of them remains closed and the other is released. N key roll over Any number of keys can be pressed simultaneously and recognized in the order, the keyboard scan recorded them. All the codes of such keys are entered into FIFO. IIE - SAP In this mode, the first pressed key need not be released before the second is

138 CNTL/STB i/p mode:, control lines that enters data in FIFO RAM. Shift: The status of shift is stored along with key code in FIFO RAM. In Scanned Sensor Matrix mode, a sensor array can be interfaced with 8279 using either encoded or decoded scans to scan the key matrix and refresh the display. IIE - SAP

139 Output (Display) Modes : 8279 provides two output modes for selecting the display options. Display Entry ( right entry or left entry mode ) 8279 allows options for data entry on the displays. The display data is entered for display either from the right side or from the left side. Display Scan : In this mode 8279 provides 8 or 16 character multiplexed displays those can be organized as dual 4- bit or single 8-bit display units. IIE - SAP

140 Control and Timing Register and Timing Control These registers store the keyboard and display modes and other operating conditions programmed by CPU. The registers are written with A0=1 and WR=0. The Timing and control unit controls the basic timings for the operation of the circuit. IIE - SAP

141 All the command words or status words are written or read with A0 = 1 and CS = 0 to or from a) Keyboard Display Mode Set : The format of the command word to select different modes of operation of 8279 is given below with its bit definitions. D7 D6 D5 D4 D3 D2 D1 D D D K K K IIE - SAP

142 SENSOR MATRIX SENSOR MATRIX IIE - SAP

143 B) Programmable clock : The clock for operation of 8279 is obtained by dividing the external clock input signal by a programmable constant called pre scaler. PPPPP is a 5-bit binary constant. The input frequency is divided by a decimal constant ranging from 2 to 31, decided by the bits of an internal prescaler, PPPPP. D7 D6 D5 D4 D3 D2 D1 D P P P P P IIE - SAP

144 c) Read FIFO / Sensor RAM : The format of this command is given below. D7 D6 D5 D4 D3 D2 D1 D AI X A A A AI Auto Increment Flag AAA Address pointer to 8 bit FIFO RAM X- Don t care This word is written to set up 8279 for reading FIFO/ sensor RAM. In scanned keyboard mode, AI and AAA bits are of no use. The 8279 will automatically drive data bus for each subsequent read, in the same sequence, in which the data was entered. In sensor matrix mode, the bits AAA select one of the 8 rows of RAM. If AI flag is set, each successive read will be from the subsequent RAM location. IIE - SAP

145 d) Read Display RAM : This command enables a programmer to read the display RAM data. D7 D6 D5 D4 D3 D2 D1 D AI A A A A The CPU writes this command word to 8279 to prepare it for display RAM read operation. AI is auto increment flag and AAAA, the 4-bit address points to the 16-byte display RAM that is to be read. If AI=1, the address will be automatically, incremented after each read or write to the Display RAM. The same address counter is used for reading and writing. IIE - SAP

146 d) Write Display RAM : This command enables a programmer to write the display RAM data. D7 D6 D5 D4 D3 D2 D1 D AI A A A A AI Auto increment Flag. AAAA 4 bit address for 16-bit display RAM to be written. e) Display Write Inhibit/Blanking : D7 D6 D5 D4 D3 D2 D1 D X IW IW BL BL IW - inhibit write flag (Masking) BL - blank display bit flags (Blanking) IIE - SAP

147 g) Clear Display RAM : D7 D6 D5 D4 D3 D2 D1 D CD2 CD1 CD0 CF CA CD: CLEAR DISPLAY ; CF: CLEAR FIFO RAM STATUS; CA: CLEAR ALL (both CD&CF) IIE - SAP

148 h) End Interrupt / Error mode Set : D7 D6 D5 D4 D3 D2 D1 D E X X X 1 E- Error mode X- don t care For the sensor matrix mode, this command lowers the IRQ line and enables further writing into the RAM. Otherwise, if a change in sensor value is detected, IRQ goes high that inhibits writing in the sensor RAM. For N-Key roll over mode, if the E bit is programmed to be 1, the 8279 operates in special Error mode IIE - SAP

149 I/O Interface FIFO status register Code given in text for reading keyboard. Data returned from 8279 contains raw data that need to be translated to ASCII: IIE - SAP

150 IIE - SAP

151 ADC 0809

152 ADC 0809 The ADC0809 is an 8-bit successive approximation type ADC with inbuilt 8-channel multiplexer. The ADC0809 is suitable for interface with 8086 microprocessor. The ADC0809 is available as a 28 pin IC in DIP (Dual Inline Package). The ADC0809 has a total unadjusted error of ±1 LSD (Least Significant Digit).

153 PIN DESCRIPTION OF ADC0809

154

155 SAR

156 Interfacing ADC with 8085 thro 8255

157 ADC interfacing with 8051

158 DAC To convert the digital signal to analog signal a Digital-to-Analog Converter (DAC) has to be employed. ( binary weighted and R/2R ladder. ) The DAC will accept a digital (binary) input and convert to analog voltage or current. Every DAC will have "n" input lines and an analog output. The DAC require a reference analog voltage (Vref) or current (Iref) source. The smallest possible analog value that can be represented by the n-bit binary code is called resolution. The resolution of DAC with n-bit binary input is 1/2nof reference analog value.

159 DAC 0800 The DAC0800 is an 8-bit, high speed, current output DAC with a typical settling time (conversion time) of 100 ns. It produces complementary current output, which can be converted to voltage by using simple resistor load. The DAC0800 require a positive and a negative supply voltage in the range of ± 5V to ±18V. It can be directly interfaced with TTL, CMOS, PMOS and other logic families. For TTL input, the threshold pin should be tied to ground (VLC = 0V).

160 R-2R Ladder

161 pin configuration of DAC0800

162 DAC interfacing with 8085 thro 8255

163 DAC interfacing with 8051