Radiation Tolerant FPGAs and Space System Managers

Transcription

1 Radiation Tolerant FPGAs and Space System Managers Ken O Neill Director of Marketing, Space and Aviation Microsemi SOC Group

2 Agenda RTG4 TM Next Generation Radiation Tolerant FPGAs RTSX-SU, RTAX TM and RT ProASIC 3 Update Radiation Hardened by Design Flash Memory Space System Managers Questions and Answers 2

3 TM Next Generation Radiation Tolerant FPGAs

4 RT FPGAs Migrating to High Speed Processing Logic Density 150 KLE TM 20 KLE RTAX-S / DSP Command and Control Medium Speed Processing High Speed Processing 150 KLE 5 Mbit SRAM 126 GMults / second 75 Gbit / second SERDES bandwidth 9 KLE RT ProASIC3 2 KLE RTSX-SU Frequency of Operation 4

5 Next Generation Space FPGAs Designed for high-bandwidth data processing in payload applications Abundant high-performance programmable logic fabric Embedded high speed multiply-accumulate blocks Ample on-board memory with fast access time, two block sizes High performance I/Os SERDES, LVDS, DDR2, Based on 65nm Flash low power process Naturally resistant to configuration upsets Non-volatile configuration live at power-up, no external boot memory needed Low static power Radiation enhanced for GEO and deep space Total ionizing dose, single event effects hardening by design Intrinsic latch-up immunity and absence of configuration upsets RTG4 TM high-speed signal processing from your high-reliability partner 5

6 RTG4 Family Resources RT4G075 RT4G150 RT4G200 LUT4 + TMR/SET FF 77, , ,400 User IO (non-serdes) RAM24K Blocks uram1.5k Blocks RAM Mbits UPROM Kbits x18 Multiply-Accumulate Blocks SERDES lanes DDR2/3 SDRAM Controller (with ECC) 2x32 2x32 2x32 Globals PLLs (Rad Tolerant) Spacewire Clock & Data Recovery Circuits PCI Express Endpoints Packages CG1432 CG1657 CG2092 6

7 Radiation Specifications Total Dose > 100 KRad TID Single Event Effects No configuration failures (to be tested to > 110 MeV-cm 2 /mg) No single event latch-up (to be tested to > 110 MeV-cm 2 /mg) Mitigation for single event upsets Flip-flops with TMR and asynchronous self-correction (LET TH > 37 MeV-cm 2 /mg) Flip-flops in the logic fabric Flip-flops in embedded features Mathblocks etc On-chip SRAM (RAM18K and uram1k) Built-in EDAC 1E-10 errors/bit-day, GEO solar min Mitigation of single event transients Logic cells hardened with SET filter SET filter can be individually enabled / disabled for higher performance Target 1E-8 errors/bit-day, GEO solar min 7

8 RT4G150 Chip Architecture SERDES + Hardened IP (PCI-Express) PLL and CCC Mathblocks SERDES + Hardened IP (PCS) Logic Cells SDRAM DDRx Controller Block RAM (18Kb) uprom μram (1Kb) 8

9 RTG4 Logic Module TMR Protected Simplified Diagram Dedicated Flip-flop to enable efficient TMR hardening With enable, global asynchronous set/reset, and local synchronous set/reset Fast carry chain to complement Mathblock performance Arithmetic functions (add/subtract) Target 300 MHz for 32-bit functions (no SET filter) Target 250 MHz for 32-bit function (SET filter deployed) Industry standard LUT4 for efficient synthesis High utilization LUT4 and flip-flop in same module can be used independently Hierarchical routing architecture enables >95% module utilization 9

10 RTG4 Mathblock A[17:0] D ADD_SUB EN B[17:0] D + X D OVFL / CO S N [43:0] EN D[43:0] EN C[43:0] D SHIFT17 D >> 17 EN EN SEL_CASC S N-1 [43:0] 18 x 18 multiplier with advanced accumulate New 3-input adder function: (C + D) +/- (A * B) High performance for signal processing throughput 250 MHz with SET mitigation 300 MHz without SET mitigation Optional SEU-protected registers on inputs and outputs (including C input) 10

11 RTG4 Memory Blocks Radiation Tolerant Resistant to multi-bit upset Built-in optional EDAC (SECDED) LSRAM up to 24 KBit Dual-port and two-port options High performance synchronous operation Example usage Large FFT memory uram up to 1.5 KBit Three Port Memory Synchronous Write Port Two Asynchronous or Synchronous Read Ports Example usage Folded FIR filters and FFT twiddle factors Mixed port sizes Write and read port sizes can be different 300 MHz performance CLKA ADDRA[ ] WDATAA[17:0] WENA CLKB ADDRB[ ] WDATAB[17:0] WENB WCLK WADDR[ ] WDATA[17:0] WEN RCLKA RADDRA[ ] RENA RCLKB RADDRB[ ] RENB RAM24K uram1.5k RDATAA[17:0] ECC_STATA RDATAB[17:0] ECC_STATB RDATAA[17:0] ECC_STATA RDATAB[17:0] ECC_STATB 11

12 General Purpose IO Single ended standards LVCMOS from 1.2V to 3.3V LVTTL PCI Voltage reference standards (600+ Mbps) Includes on-chip termination SSTL2, SSTL18 and SSTL15 For DDR2/DDR3 SDRAM memories HSTL18 and HSTL15 For SRAM memories Differential I/O standards Includes on-chip termination True LVDS (600+ Mbps) Mini-LVDS, M-LVDS, RSDS, LVPECL 12

13 3.125Gbps SERDES PMA Based on PCIe Gen 1 PHY RT Performance = Gbps Up to eight x4 units PCI Express Protocol x1, x2, x4 64-bit AXI /AHB PCI Express Interface 4 X16 PIPE 8B/10B Encoding / Decoding PCS Programmable Logic TXDn RXDn 1 PMA 4 x 20-bit EPCS SRIO Or Custom Protocol Serializer / Deserializer Clock Recovery XAUI Bridge XGMII Or Custom Protocol <= 3.125GHz <= 156MHz 13

14 Processor IP Benchmarking 1: Aeroflex Gaisler Leon3 on Igloo2 Initial benchmarking uses Igloo2 FPGA Igloo2 is 65nm Flash FPGA commercial equivalent of RTG4 No optimization of IP yet for Igloo2 or RTG4 architecture Benchmarking of Leon3 on RTG4 will follow RTG4 has built-in SEU protection of gates and SRAM so non-ft Leon3 ok Resource utilization and performance Includes peripherals UARTs, Timer, Interrupt Controllers, etc Occupies 7% to 24% of M2GL150 (will be same for RT4G150) Main clock at 80MHz, commercial temperature range Expect ~ 110DMIPs, using 1.4 DMIPs/MHz Results courtesy of Aeroflex Gaisler 14

15 Processor IP Benchmarking 2: ARM Cortex M1 on RTG4 ARM Cortex M1 32-bit RISC microcontroller Supported by ecosystem from ARM and third-party vendors Results presented here for information only not officially supported on RTG4 Benchmarking uses RTG4 first customer access software Software is evolving and improving as we move toward production Targeting RT4G150, Dash-1 speed grade Basic processor core without peripherals was tested Main clock at 96 MHz, military temperature range Feature Logic Resources 2% Memory Resources 4% Globals 4% I/O 17% Utilization 15

16 Performance Summary General purpose logic 250 MHz system performance with SET mitigation deployed 300 MHz system performance without SET mitigation 300 MHz DSP support performance (adders, delays, etc.) Mathblock 250 MHz pipelined performance with SET mitigation deployed 300 MHz pipelined performance without SET mitigation RAM18K and uram1k > 300 MHz IO > 600 Mbps LVDS and 667 Mbps DDRx SDRAM data SERDES to Gbps Overall 250 MHz general system performance with SET mitigation deployed 300 MHz signal processing performance without SET mitigation 16

17 RTG4 Packaging Summary Flip chip assembly Hermetically-sealed cavity Internally-mounted BME decoupling capacitors Expect that this is qualifiable as Class V Pending any spec changes in Mil Prf rev K Thermal adhesive between die and seal lid (passed RGA <5,000ppm, passed outgas to NASA spec) BME decoupling capacitors placed inside Kovar Lid RTG4 Die Under fill (passed RGA <5,000ppm, passed outgas to NASA spec) 17

18 RTG4 Product Availability RT devices for space flight applications Initial device: RT4G150 Early SW access: NOW Sample RT4G150 silicon: Early CY 2015 RT4G150 development kit: Early CY 2015 Mil Std 883 class B flight units: Early CY 2016 QML class Q qualification: Late CY 2016 Non-RT Igloo2 and SmartFusion2 for emulation and development Software general availability: NOW Commercial device availability: NOW M2S150T advanced development kit: NOW 18

19 RTG4 Lead Customer Program (LCP) Program outline Early access to the first RTG4 software and documentation Start new design activity or port existing designs to RTG4 Evaluate product performance, features, documentation Provide feedback LCP has multiple phases, in which updated RTG4 software and documentations will be provided: LCP Phase 1 software available now Basic place and route with timing analysis for GPIO, logic fabric, SRAM and Mathblocks, TID timing derating, power estimator spreadsheet LCP Phase 2 software available now Adds SET filtering LCP Phase 3 software scheduled for November 2014 Adds SERDES, package pin assignments, DDR controllers, UPROM Program is currently open to new participants

20 RTSX-SU, RTAX and RT ProASIC3 Update 20

21 RTSX-SU, RTAX and RT ProASIC3 Update RT FPGAs removed from US Munitions List All Microsemi RT FPGAs now under EAR control Currently using the following Export Control Classification Numbers RTSX-SU 9A515.e2 RTAX-S/SL/DSP 9A515.e2 RT ProASIC3 3A001.a.2.c RT ProASIC3 QML qualification Currently under review with DLA, SMC, NASA Expect to finalize by end of

22 RTAX-S Space Flight Heritage Advanced EHF First Launch August 2010 CHIRP Launched Sept 2011 Mars Science Lab Curiosity Launched November 2011 MUOS First Launch February 2012 RTAX2000S-CQ352 RTAX4000S-CQ352 RTAX2000S-CG1152 RTAX1000S-CQ352 RTAX250S-CQ208 RTAX2000S-CG624 (6Σ) RTAX2000S-CG624 (BAE) IRNSS-1A/1B Launched July 2013/May 2014 Gaia Launched December 2013 Sentinel-1A Launched April 2014 ANGELS Launched July 2014 RTAX2000S-CQ256 RTAX2000S-CG624 (6Σ) RTAX2000S-CG1152 (6Σ) RTAX2000S-CG624 (6Σ) RTAX4000S-CG1272 (6Σ)

23 Preparing to Fly RTAX-S Sentinel 2 KompSat 3 ExoMars GOES-R Radarsat Constellation Mission Magnetospheric MultiScale CG624 CG624 CQ208 CQ256 CQ208 CQ352 CG624 - BAE CQ352 CQ208 CQ352 CG624-6Σ Galileo Bepi Colombo MTG James Webb Space Telescope GPS-III Iridium Next CQ352 CQ208 CQ256 CQ352 CQ352 CQ352 CQ208 CQ256 CQ352 CG624-6Σ CQ208 CQ352

24 RT ProASIC3 Flight Heritage In Flight Preparing For Flight ISS LADEE Mars InSight Deimos 2 IRIS Orbcomm G2 Iridium Next (Hosted Payload) DubaiSat 2

25 Rad Hard By Design Flash Memory 25

26 RHBD Non-Volatile Memory for Space 128 Mbit Flash memory NOR-flash architecture Parallel user interface address bus, data bus JTAG user interface for read and write 30 nsec read / write access time Radiation hardened by design TID hard to 300Krad SEL immune SEU protected to LET TH > 37 MeV-cm 2 /mg Orbital error rate <1E-10 errors/bit-day, GEO solar min This is NOT upscreened commercial product Space-grade manufacturing and packaging Mil Std 883 Class B, QML class Q, QML class V Hermetic packaging, planning for 100-pin CQFP Availability of flight-qualified parts expected

27 Space System Managers 27

28 Space System Managers Standard off-the-shelf solutions for telemetry and motor control in space Microsemi mixed-signal standard parts LX7720 current sense, rotary position sense and MOSFET drivers LX7730 voltage, current and temperature telemetry 100 Krad TID, 50 Krad ELDRS, SEE immune Microsemi RT FPGAs implement digital interface with satellite control bus LX7720 Motor Control and Current Drive RTAX2000S or RT3PE3000L FPGA Spacecraft Motors, Actuators, and Pyrotechnics Level Control PCB Power Rails and Temperature Sensors Current Sense Position Sense MOSFET Drivers Mux LX7730 Telemetry DAC ADC ΔΣ Modulator ΔΣ Modulator SPI Interface to RT FPGA GPIO SPI Interface to LX7730 User-Defined Custom Logic Leon3-FT Processor (optional) Mil Std 1553 Interface CANBus Interface Spacewire Interface PCI Interface To Spacecraft Telemetry, Tracking & Control (TT&C) system 28

29 Space System Manager Advantage The Space System Manager offers: 50% to 75% board space reduction Increased reliability Decreased weight FPGA A/D Analog Multiplexer Driver MOSFET Comparators Amplifier Discrete Solution Microsemi Space System Manager

30 LX7730: 64 Analog Input Telemetry Controller Features: 64 Universal sensor interfaces: SSA 64 single ended or 32 differential CLKA MOSI_A MISO_A ADC range scaling Level monitoring of 8 SE channels SSB CLKB MOSI_B Break before Make switching MISO_B 25ksps 12 bit ADC Optional 2 pole anti-aliasing filter 8 fixed bi-level logic interfaces 10 bit current DAC 1% voltage & 2% current references Parallel or Dual SPI interface Built in test and calibration -55 C to 125 C ambient 100krad TID, 50krad ELDRS, SEE immune 132 pin ceramic CQFP Applications: Spacecraft environment monitoring Attitude Control VDD SPI_A SPI_B CLK CE OE WE A0 A1 A2 A3 A4 D0 D1 D2 D3 D4 D5 D6 D7 PTY /ACK RESET BLO# EXT_REF VCC EXT_VEE Dual Serial or Parallel Interface and Registers Bit ADC Current Programming Range Scaling/Offset Cor Hi-Z 8 Bit DAC 2 Pole AAF IREF IREF IREF1/IREF2 + - IA Bit DAC 15V 1 of 8 bi-level input blocks + - IREF MUX 5.00V Precision REF 1 of 65 CH Current MUX 1 of 9 MUX 1 of 9 MUX 1 of 8 MUX 1 of 8 threshold blocks Threshold MUX Pos 1 Pos 2 Pos 8 1 of 8 switch banks 2.5V IREF1 IREF2 ITEST Ch1 to 8 Ch9 to 16 Ch57 to 64 SE_RTN IA_OUT ADC_IN P_DAC N_DAC BLI# BL_TH IREF1 IREF2 VREF +5V regulator +5V Charge Pump Controller PCP NCP VEE 30

31 LX7730 Satellite Telemetry Example Telemetry Management using FPGA and LX Microsemi Corporation 31

32 LX7720 Power Driver w Position Feedback Provides MOSFET motor drivers: 3 phase motors Unipolar or bipolar steppers 4 high and low side relay drivers. Up to 4 current sensors Phase currents or RTN currents Average current control loops Sensing for resolver or LVDT Detecting pulse sensors and limit switches 2013 Microsemi Corporation. 32

33 LX7720: Power Driver with Rotation and Position Sensing Four Half-Bridge Nch MOSFET drivers Four floating differential current sensors with ΣΔmodulated processed outputs Pulse density modulated resolver exciter Three differential resolver sensors with ΣΔmodulated processed outputs to FPGA Six bi-level logic inputs 10V isolation Signal-to-Motor Gnd 132 pin ceramic CQFP -55 C to 125 C ambient 100krad TID, 50krad ELDRS, SEE immune 132 pin ceramic CQFP Applications: Motor or actuator servo driver Stepper, BLDC, PMSM driver FPGA CP_CLK UD_IN_A UD_IN_A LD_IN_A OC_FAULT SNS_OUT_A PLL_CAP MOD_CLK DEMOD_IN ADC1 ADC2 ADC3 Fault CLK COND 1 of 4 driver with current sense CP_CLK Over Current Detect ΣΔ Mod Level Shift Level Shift Charge Pump VGS Level Shift MOSFET Driver +15V Level Shift MOSFET Driver Level Shift SW Pin Current Sense ΣΔ Mod ΣΔ Mod ΣΔ Mod + gm - VDMOD + - CPN_A CPP_A VFLT_A UD_A SW_A LD_A DMODP DMODN ADC1_P ADC1_N + - ADC2_P ADC2_N + - ADC3_P ADC3_N BLO1 BLO BLI1 BLI2 BLO3 + BLI3 - BLO4 + BLI4 - BLO5 + BLI5 - BLO6 BLI6 + - VDD BL_TH VPS CSPS_A VFLT_A RTN_A CS_A Encoders or hall sensors 33

34 LX7720: Attitude and Orbit Control Example Closed loop motor control using FPGA and LX Microsemi Corporation. 34

35 LX7720 Performance Highlights Parameter Comment Min Typ Max Units Motor Power Supply De-rated by 20% V MOSFET driver impedance Source or sink 1 Ω PWM frequency DC 200 khz Current sense differential range mv Current sense accuracy 7 bits Current sense latency 1.5 us Resolver carrier frequency khz Resolver accuracy 16 bits Bi-level threshold range V Bi-level propagation delay 1 us 2013 Microsemi Corporation. 35

36 Space System Manager Schedule Part Description First Customer Samples Flight-worthy (Pre-QML) (1) Production Equiv K (EK) (2) LX7730 Telemetry Controller Dec-14 May-15 Aug-15 LX7720 Position/Motor Controller CQ CQ CQ (1) - product built per QML-K assembly flow, but prior to completion of Life test and ELDRS test. (2) - Equivalent K follows QML-K flow, but is prior to official QML-K listing with the DLA. Product is qualified to 1000 hrs steady state life test. ELDRS test complete.

37 Questions and Answers 37