RETI LOGICHE. Sito del corso:
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1 RETI LOGICHE Sito del corso:
2 Design of Integrated Digital Systems System Level Register Transfer Level Gate Level Transistor Level Layout Level Mask Level 2
3 System Level Abstract algorithmic description of high-level behavior e.g. C-Programming language Port* compute_optimal_route_for_packet(packet_t *packet, {static Queue_t *packet_queue; Channel_t *channel) packet_queue = add_packet(packet_queue, packet);...} abstract because it does not contain any implementation details for timing or data efficient to get a compact execution model as first design draft difficult to maintain throughout project because no link to implementation 3
4 RTL Level Cycle accurate model close to the hardware implementation bit-vector data types and operations as abstraction from bit-level implementation sequential constructs (e.g. if - then - else, while loops) to support modeling of complex control flow module mark1; reg [31:0] m[0:8192]; reg [12:0] pc; reg [31:0] acc; reg[15:0] ir; always begin end ir = m[pc]; if(ir[15:13] == 3b 000) pc = m[ir[12:0]]; else if (ir[15:13] == 3 b010)... endmodule acc = -m[ir[12:0]]; 4
5 Gate Level Model on FINITE-STATE MACHINE LEVEL models function in Boolean logic using registers and gates various delay models for gates and wires 1ns 3ns 4ns 5ns in this course we will deal with gate level 5
6 Transistor Level Model on CMOS transistor level depending on application function modeled as resistive switches used in functional checking or full differential equations for circuit simulation used in detailed timing analysis 6
7 Layout Level Transistors and wires are laid out as polygons in different technology layers such as diffusion, poly-silicon, metal, etc. 7
8 Relative Effort Design of Integrated Systems Design phases overlap to large degrees Parallel changes on multiple levels, multiple teams Tight scheduling constraints for product Logic RTL Transistor System Project Time 8
9 Processor Growth: Moore s Law
10 Storage Capacity At present SDK expects its first 2.5 platters for HAMR drives to feature 1.2TB 1.5TB capacity (areal density of 1.5Tb/in² 1.95Tb/in²). By the end of the decade, capacity of 2.5 disks for HDDs is projected to increase to 2TB Dr. Arjan Durresi CS Conference 2015
11 Global Internet Traffic by Device Type Tablets are the fastest-growing device category with 29 percent CAGR (3.6-fold growth) over the forecast period, followed by machine-to-machine (M2M) connections with 26 percent CAGR (threefold growth).
12 M2M Traffic Growth While the number of connections is growing threefold, global M2M IP traffic will grow 11-fold over this same period
13 Design Challenges Systems are becoming huge, design schedules are getting tighter > 100 M gates becoming common for ASICs > 0.4 M lines of C-code to describe system behavior > 5 M lines of RLT code Design teams are getting very large for big projects several hundred people differences in skills concurrent work on multiple levels management of design complexity and communication very difficult Design tools are becoming more complex but still inadequate typical designer has to run ~50 tools on each component tools have lots of bugs, interfaces do not line up etc. 13
14 Design Challenges Decision about design point very difficult compromise between performance / costs / time-to-market decision has to be made 2-3 years before design finished design points are difficult to predict without actually doing the design scheduling of product cycles Functional verification simulation still main vehicle for functional verification but inadequate because of size of design space results in bugs in released hardware that is very expensive to recover from (different in software) 14
15 Gartner Hype Cycle
16 Gartner Hype Cycle 2016
17 Gartner Hype Cycle 2017
18 Binary Values: Other Physical Quantities What are other physical quantities represent 0 and 1? CPU Disk CD Dynamic RAM Voltage Magnetic Field Direction Surface Pits/Light Electrical Charge
19 Signal Examples Over Time Time Analog Digital Asynchronous Synchronous Continuous in value & time Discrete in value & continuous in time Discrete in value & time
20 Signal Example Physical Quantity: Voltage Threshold Region
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