MSP430 Teaching Materials

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Beira Interior (PT) Pedro Dinis Gaspar, António Espírito Santo, Bruno

1 MSP430 Teaching Materials Lecture 8 Direct Memory Access (DMA) & Communications Introduction Texas Instruments t Incorporated University of Beira Interior (PT) Pedro Dinis Gaspar, António Espírito Santo, Bruno Ribeiro, Humberto Santos University of Beira Interior, Electromechanical Engineering g Department

2 Contents (1/2) Direct Memory Access (DMA) capability DMA configuration and operation: Block diagram Features System and DMA interrupts DMA transfers DMA Registers 2

3 Contents (2/2) Communication Introduction Communications system model Transmission mode Serial communications Synchronous and asynchronous serial communications Peripheral Interface Serial (SPI) protocol I 2 C (Inter-Integrated Circuit) protocol MSP430 communications interfaces 3

4 DMA capability (1/3) The MSP430 has been designed for applications requiring low power; When the application requires data-handling, the direct memory access (DMA) capability included in some devicesisuseful: 5xxx; FG4xx(x); F261x; F16x(x) and F15x; Among these: MSP430FG4618 (Experimenter s board). DMA automatically handles data; DMA does not require CPU intervention; DMA helps reduce the power consumption (CPU remains sleeping). 4

5 DMA capability (2/3) Concept of DMA: move functionality to peripherals: Peripherals use less current than the CPU; Delegating control to peripherals allows the CPU to shut down (saves power); Intelligent peripherals are more capable, providing a better opportunity for CPU shutoff; DMA can be enabled for repetitive e data handling, increasing the throughput of peripheral modules; Minimal software requirements and CPU cycles. 5

6 DMA capability (3/3) The following TI Application Reports cover the use of the DMA controller for different applications, with the aim of lowering power consumption: Streamlining the mixed-signal path with the signal-chainon-chip MSP430F169 <slyt078.pdf> Interfacing the MSP430 with MMC/SD Flash Memory Cards <slaa281b.pdf> Digital FIR Filter Design Using the MSP430F16x <slaa228.pdf> Using the USCI I2C Master <slaa382.pdf> 6

7 DMA configuration and operation (1/9) Block diagram: 7

8 DMA configuration and operation (2/9) DMA controller features: Three independent transfer channels; Configurable (ROUNDROBIN bit) DMA channel priorities: Default: DMA0 DMA1 DMA2; DMA Transfer cycle time: Requires only two MCLK clock cycles per transfer; Each byte/word transfer requires: 2 MCLK cycles after synchronization; 1 MCKL cycle of wait time after transfer. 8

9 DMA configuration and operation (3/9) DMA controller features: Block sizes up to bytes or words; Configurable edge/level-triggered gg transfer (DMALEVEL bit). Byte or word and mixed byte/word transfer capability: Byte-to-byte; t t Word-to-word; Byte-to-word (upper byte of the destination word is cleared); Word-to-byte (lower byte of the source word is transferred). 9

10 DMA configuration and operation (4/9) DMA controller features: Four addressing modes for each DMA channel are independently configurable (DMASRCINCRx and DMADSTINCRx control bits): Fixed address to fixed address; Fixed address to block of addresses; Block of addresses to fixed address; Block of addresses to block of addresses. 10

11 DMA configuration and operation (5/9) DMA controller features: Six transfer modes (each channel is individually configurable by the DMADTx bits): DMADTx Transfer mode Description DMAEN after transfer 000 Single transfer Each transfer requires a trigger Block transfer 010, 011 Burst-block transfer , 111 Repeated single transfer Repeated block transfer Repeated burst-block transfer A complete block is transferred with one trigger CPU activity is interleaved with a block transfer Each transfer requires a trigger 1 A complete block is transferred with one trigger CPU activity is interleaved with a block transfer

12 DMA configuration and operation (6/9) System interrupts: DMA transfers are not interruptible by system interrupts, but system ISRs can be interrupted by DMA transfers; Only NMI interrupts can be given priority it over the DMA controller (ENNMI bit is set). If the ENNMI bit is not set, system interrupts remain pending until the completion of the transfer. DMA controller interrupts: Each DMA channel has its own DMAIFG flag that is set when the corresponding DMAxSZ register counts to zero (all modes); If the corresponding DMAIE and GIE bits are set, an interrupt request is generated. 12

13 DMA configuration and operation (7/9) DMA controller interrupts: The MSP430FG4618 implements the interrupt vector register DMAIV; All DMAIFG flags are prioritized iti and combined to source a single interrupt vector; DMAIV is used to determine which flag requested an interrupt. 13

14 DMA configuration and operation (8/9) DMA transfers: USCI_B I2C module with DMA: Two trigger sources for the DMA controller; Triggers a transfer when new I2C data is received and when data is required for transmit. ADC12 with DMA: Automatically moves data from any ADC12MEMx register to another location. DAC12 with DMA: Automatically moves data to the DAC12_xDAT register. 14

15 DMA configuration and operation (9/9) DMA transfers: DMA with flash memory: Automatically moves data to the Flash memory; Performs the data move data word/byte to the Flash; The write timing control is done by the Flash controller; Write transfers to the Flash memory succeed if the Flash controller set-up is done before the DMA transfer and if the Flash is not busy. All DMA transfers: Occur without CPU intervention; Operate independently of any low-power modes; Increase throughput of modules. 15

16 DMA Registers (1/11) DMACTL0, DMA Control Register 0 (FG4618) Reserved DMA2TSELx DMA1TSELx DMA0TSELx All DMAxTSELx registers are the same. DMAxTSELx Transfer triggered 0000 when DMAREQ = 1 (DMAREQ = 0 automatically when the transfer starts) <Timer_A> when TACCR2 CCIFG = (CCIFG = 0 automatically when the transfer starts) If CCIE = 1, CCIFG won t trigger a transfer <Timer_B> when TBCCR2 CCIFG = (CCIFG = 0 automatically when the transfer starts) If CCIE = 1, CCIFG won t trigger a transfer 16

17 DMA Registers (2/11) DMACTL0, DMA Control Register 0 (FG4618) (continued) DMAxTSELx Transfer triggered <USART0>: when URXIFG0 = 1 (URXIFG0 = 0 automatically when the transfer starts) If URXIE0 = 1, URXIFG0 flag won t trigger a transfer 0011 <USCI_A0>: when UCA0RXIFG = 1 (UCA0RXIFG = 0 automatically when the transfer starts) If UCA0RXIE = 1, UCA0RXIFG flag won t trigger a transfer <USART0>: when UTXIFG0 =1 (UTXIFG0 = 0 automatically when the transfer starts) If UTXIE0 = 1, UTXIFG0 flag won t trigger a transfer 0100 <USCI_A0>: when UCA0TXIFG = 1 (UCA0TXIFG = 0 automatically when the transfer starts) UCA0TXIE = 1, UCA0TXIFG flag won t trigger a transfer <DAC12> when DAC12_0CTL DAC12IFG = (DAC12IFG = 0 automatically when the transfer starts) If DAC12IE = 1, DAC12IFG won t trigger a transfer 17

18 DMA Registers (3/11) DMACTL0, DMA Control Register 0 (FG4618) (continued) DMAxTSELx Transfer triggered <ADC12> when ADC12IFGx = 1 (corresponding ADC12IFGx flag for single-channel conversions, and the ADC12IFGx for the last conversion for 0110 sequence conversions) (All ADC12IFGx = 0 automatically when the associated ADC12MEMx register is accessed by the DMA controller) <Timer_A> when TACCR0 CCIFG = 1: 0111 CCIFG = 0 automatically when the transfer starts If CCIE = 1, CCIFG flag won t trigger a transfer <Timer_B> when TBCCR0 CCIFG = (CCIFG = 0 automatically when the transfer starts) If CCIE = 1, CCIFG won t trigger a transfer <USART1>: 1001 when URXIFG1 = 1 (URXIFG1 = 0 automatically when the transfer starts) If URXIE1 = 1, URXIFG0 flag won t trigger a transfer 18

19 DMA Registers (4/11) DMACTL0, DMA Control Register 0 (FG4618) (continued) DMAxTSELx Transfer triggered <USART1>: when UTXIFG1 =1 (UTXIFG1 = 0 automatically when the transfer starts) If UTXIE1 = 1, UTXIFG0 flag won t trigger a transfer <Hardware Multiplier> when the hardware multiplier is ready for a new operand <USCI_B0>: when UCB0RXIFG = 1 (UCB0RXIFG = 0 automatically when the transfer starts) If UCB0RXIE = 1, UCB0RXIFG flag won t trigger a transfer <USCI_B0>: when UCB0TXIFG = 1 (UCB0TXIFG = 0 automatically when the transfer starts) UCB0TXIE = 1, UCB0TXIFG flag won t trigger a transfer when the DMAxIFG = 1: DMA0IFG triggers channel 1 DMA1IFG triggers channel 2 DMA2IFG triggers channel 0 (None of the DMAxIFG = 0 automatically when the transfer starts) 1111 When an external trigger DMAE0 = 1 19

20 DMA Registers (5/11) DMACTL1, DMA Control Register 1 (FG4618) DMAONFETCH ROUNDROBIN ENNMI Bit Description 2 DMAONFETCH DMA on fetch: DMAONFETCH = 0 DMA transfer occurs immediately DMAONFETCH = 1 DMA transfer occurs on next instruction ti fetch after the trigger 1 ROUNDROBIN Round robin: ROUNDROBIN = 0 DMA channel priority is DMA0 DMA1 DMA2 ROUNDROBIN = 1 DMA channel priority changes with each transfer 0 ENNMI Enable NMI when ENNMI = 1, allowing NMI interrupt to interrupt a DMA transfer 20

21 DMA Registers (6/11) DMAxCTL, DMA Channel x Control Register (FG4618) Reserved DMADTx DMADSTINCRx DMASRCINCRx DMADSTBYTE DMASRCBYTE DMALEVEL DMAEN DMAIFG DMAIE DMAABORT DMAREQ Bit Description DMADTx DMA transfer mode: DMADT2 DMADT1 DMADT0 = 000 Single transfer DMADT2 DMADT1 DMADT0 = 001 Block transfer DMADT2 DMADT1 DMADT0 = 010 Burst-block transfer DMADT2 DMADT1 DMADT0 = 011 Burst-block transfer DMADT2 DMADT1 DMADT0 = 100 Repeated single transfer DMADT2 DMADT1 DMADT0 = 101 Repeated block transfer DMADT2 DMADT1 DMADT0 = 110 Repeated burst-block transfer DMADT2 DMADT1 DMADT0 = 111 Repeated burst-block transfer 21

22 DMA Registers (7/11) DMAxCTL, DMA Channel x Control Register (FG4618) (continued) Reserved DMADTx DMADSTINCRx DMASRCINCRx DMADSTBYTE DMASRCBYTE DMALEVEL DMAEN DMAIFG DMAIE DMAABORT DMAREQ Bit Description DMADSTINCRx DMA destination address increment/decrement after each byte or word transfer: When DMADSTBYTE = 1, the destination address increments / decrements by one When DMADSTBYTE = 0, the destination address increments/ decrements by two. DMADSTINCR1 DMADSTINCR0 = 00 Address unchanged DMADSTINCR1 DMADSTINCR0 = 01 Address unchanged DMADSTINCR1 DMADSTINCR0 = 10 Address decremented DMADSTINCR1 DMADSTINCR0 = 11 Address increment 22

23 DMA Registers (8/11) DMAxCTL, DMA Channel x Control Register (FG4618) (continued) Reserved DMADTx DMADSTINCRx DMASRCINCRx DMADSTBYTE DMASRCBYTE DMALEVEL DMAEN DMAIFG DMAIE DMAABORT DMAREQ Bit Description 9-8 DMASRCINCRx DMA source address increment/decrement after each byte or word transfer: When DMASRCBYTE = 1, the source address increments/decrements by one When DMASRCBYTE = 0, the source address increments/decrements t by two. DMASRCINCR1 DMASRCINCR0 = 00 Address unchanged DMASRCINCR1 DMASRCINCR0 = 01 Address unchanged DMASRCINCR1 DMASRCINCR0 = 10 Address decremented DMASRCINCR1 DMASRCINCR0 = 11 Address increment 23

24 DMA Registers (9/11) DMAxCTL, DMA Channel x Control Register (FG4618) (continued) Reserved DMADTx DMADSTINCRx DMASRCINCRx DMADSTBYTE DMASRCBYTE DMALEVEL DMAEN DMAIFG DMAIE DMAABORT DMAREQ Bit Description 7 DMADSTBYTE DMA destination length (byte or word): DMADSTBYTE = 0 Word DMADSTBYTE = 1 Byte 6 DMASRCBYTE DMA source length (byte or word): DMASRCBYTE = 0 Word DMASRCBYTE = 1 Byte 5 DMALEVEL DMA level: DMALEVEL = 0 Edge sensitive trigger (rising edge) DMALEVEL = 1 Level sensitive trigger (high level) 4 DMAEN DMA enable when DMAEN = 1 3 DMAIFG DMA interrupt flag DMAIFG = 1 when interrupt pending 2 DMAIE DMA interrupt enable when DMAIE = 1 1 DMAABORT DMA Abort DMAABORT = 1 when a DMA transfer is interrupted by NMI 0 DMAREQ DMA request DMAREQ = 1 starts DMA 24

25 DMA Registers (10/11) DMAxSA, DMA Source Address Register (FG4618) 32-bit register points to the DMA source address for single transfers or the first source address for block transfers. DMAxDA, DA DMA Destination i Address Register (FG4618) 32-bit register points to the DMA destination address for single transfers or the first source address for block transfers. For both registers (DMAxSA and DMAxDA): DA) Bits are reserved and always read as zero; Reading or writing to bits requires the use of extended instructions; When writing to DMAxSA or DMAxDA with word instructions, ti bits are cleared. 25

26 DMA Registers (11/11) DMAxSZ, DMA Size Address Register (FG4618) The 16-bit DMA size address register defines the number of bytes/words of data per block transfer: DMAxSZ decrements with each word or byte transfer; When DMAxSZ = 0, it is immediately and automatically reloaded with its previously initialized value. DMAIV, DMA Interrupt Vector Register (FG4618) 16 bit DMAIV value only uses bits 3 to 1 (other bits = 0); DMAIV content provides the interrupt source priority: DMAIV = 02h: DMA channel 0 (highest priority); DMAIV = 04h: DMA channel 1; DMAIV = 06h: DMA channel 2; DMAIV = 0Eh: Reserved (lowest priority). 26

27 Introduction An important feature of modern microprocessor based systems is their communication capability, that is, their ability to exchange information with other systems in the surrounding environment; At the low level, communications interfaces are used to download a firmware update or to set up local configurations (e.g. turn features on or off), amongst other tasks; At a higher level, communication interfaces are used to exchange information in distributed applications. 27

28 Communications system model (1/2) Digital communication devices: Transmitter: Has the task of putting the information into the appropriate p format for subsequent transmission; Receiver: Is responsible for collecting the message that has been sent and extracting the original information; Communication medium: The physical medium through which the information flows and is commonly implemented as: Twisted pair wire; Fibre optic cable; Radio frequency transmission. 28

29 Communications system model (2/2) Devices participating in a digital communication system: DTE: Data Terminal Equipment; DCE: Data Communications Equipment. Transmitter Receiver DTE DCE Transmission medium DCE DTE Receiver Transmitter 29

30 Transmission mode (1/5) Communications between digital devices can be divided into two types : Parallel communications; Serial communications. Parallel communications: The physical transmission medium has independent signal lines in numbers equal to the transmitted digital word bits; The information transmitted at any given instant is the data word formed by the logical levels on the various signal lines. 30

31 Transmission mode (2/5) Parallel communications: Example: Character ASCII W parallel l transmission. i Information flow 31

32 Transmission mode (3/5) Serial communications: Physical transmission medium needs only one signal line; The information transmitted is provided by the transmitter as a sequence of bits, sent at the rate established between the transmitter and the receiver; Additional information is needed to enable the synchronization between the receiver and transmitter: Start bit: Added to the beginning of the information transmitted, so that the receiver can identify the beginning of a new transmission; Stop bit(s): Added to the end of the information transmitted to indicate that the data value is complete. 32

33 Transmission mode (4/5) Serial communications: Example: Character ASCII W serial transmission: i 33

34 Transmission mode (5/5) Advantages and disadvantages of parallel and serial communication: Characteristic Parallel Serial Bus line One line per bit One line Sequence Transmission rate All bits of one word simultaneously High Sequence of bits Low Bus length Short distances Short and long distances Cost High Low Asynchronous transmission Synchronisation between needs start and stop bits Critical the different bits is Synchronous transmission characteristics demanding needs some other synchronisation 34

35 Serial communications (1/3) The start bit identifies the beginning of a data transfer and is generated by a high-to-low transition on the bus; Following the start bit are the data bits. In this example, the ASCII code for the text transfer uses seven data bits; The error-checking bit (parity bit) is sent after the data bits; To terminate the transmission, one or two stop bits are issued; Using seven data bits, the complete message can use one or two stop bits. Using eight data bits, only one stop bit is available for transmission. 35

36 Serial communications (2/3) Parity bit: Used to verify the integrity it of information transmitted; The bit is added by the transmitter and indicates whether the total sum of the numbers "1" in the message data is odd or even; The transmissions can be configured for odd or even parity. 36

37 Serial communications (3/3) Baud rate example: The transmission i of W : Character uses seven data bits; Four bits are used for control, making a total of 11 bits. This corresponds to 11 baud; If the characters are transmitted at a rate of 10 characters per second, the baud rate will be: 10x11 = 1100 baud/s. 37

38 Synchronous and asynchronous serial communications (1/2) Serial communications may be: Asynchronous: where the transmission rate (baud rate) is fixed by the transmitter and the receiver works at the same baud rate, using the transmitted start bit to synchronize the start of a new message; Synchronous: where there is a separate synchronization clock signal connected between the receiver and the transmitter. Synchronous communications: Normally one unit assumes the role of master and one or more of the other units take the role of slaves; The clock signal generated by the master is used by the slave units to transfer data in/out of the TX and RX registers; It is possible for a device to transmit and receive simultaneously. 38

39 Synchronous and asynchronous serial communications (2/2) Asynchronous communications: Characterised by the absence of any synchronization clock signal between the units; The transmission in this mode does not allow simultaneous transmission and reception, that is, when one device transmits the other devices just listen. 39

40 Serial Peripheral Interface (SPI) protocol (1/2) The Serial Peripheral Interface ( SPI) bus is a standard form of synchronous serial communication; Developed by Motorola; Operates in full duplex mode; Master/Slave relationship; Communications are always initiated by the master. Low cost. 40

41 Peripheral Interface Serial (SPI) protocol (2/2) Supports only one master; Can support more than a slave; Short distance between devices, e.g. on a printed circuit boards (PCBs); Special attention needs to be observed to the polarity and phase of the clock signal; The master sends data on one edge of clock and reads data on the other edge. Therefore, itcansend/receive at the same time. 41

42 I 2 C (Inter-Integrated Circuit) protocol (1/3) Multi-master synchronous serial computer bus; Invented by Philips Semiconductors; Developed with the main objective of establishing links between integrated circuits and to connect low-speed peripherals; Based on a two bi-directional open-drain lines pulled up with resistors: SDA: Serial Data; SCL: Serial clock. Typical voltages used are +5.0 V or +3.3 V, although systems with other voltages are possible. 42

43 I 2 C (Inter-Integrated Circuit) protocol (2/3) Communications is always initiated and completed by the master, which is responsible for generating the clock signal; In more complex applications, I 2 C can operate in multimaster mode; The slave selection by the master is made using the seven-bit address of the target slave; The master (in transmit mode) sends: Start bit; 7-bit address of the slave it wishes to communicate with; A single bit representing whether it wishes to write (0) to or read (1) from the slave; The target slave will acknowledge its address. 43

44 I 2 C (Inter-Integrated Circuit) protocol (3/3) Example of an I 2 C communication system: 44

45 MSP430 communications interfaces (1/2) Equipped with three serial communication interfaces: USART (Universal Synchronous/Asynchronous Receiver/Transmitter): UART mode; SPI mode; I 2 C (on F15x/ F16x only). USCI (Universal Serial Communication Interface): UART with Lin/IrDA support; SPI (Master/Slave, 3 and 4 wire modes); I 2 C (Master/Slave, up to 400 khz). USI (Universal Serial Interface): SPI (Master/Slave, 3 & 4 wire mode); I 2 C (Master/Slave, up to 400 khz). 45

46 MSP430 communications interfaces (2/2) Comparison between the communication modules: USART USCI USI UART: UART: - Two modulators support - Only one modulator -n/a -n/a - n/a n/16 timings - Auto baud rate detection - IrDA encoder & decoder - Simultaneous USCI_A and USCI_B (2 channels) SPI: - Only one SPI available - Master and Slave Modes - 3 and 4 Wire Modes I 2 C: (on 15x/ 16x only) - Master and Slave Modes - up to 400kbps SPI: - Two SPI (one on each SPI: USCI_A and USCI_B) - Only one SPI available - Master and Slave Modes - Master and Slave Modes - 3 and 4 Wire Modes I 2 C: - Simplified interrupt usage - Master and Slave Modes -up to 400kbps I 2 C: - SW state machine needed - Master and Slave Modes 46

CPE/EE 323 Introduction to Embedded Computer Systems Homework V

CPE/EE 323 Introduction to Embedded Computer Systems Homework V 1(15) 2(15) 3(25) 4(25) 5(20) Total Problem #1 (15 points) Power, Low power systems A sensor platform features a microcontroller, a sensor,