MSP430 ez430-rf2500. Guillaume Salagnac. November 29, 2011

Size: px

Start display at page:

Download "MSP430 ez430-rf2500. Guillaume Salagnac. November 29, 2011"

Basil Reynolds
6 years ago
Views:

1 1 MSP430 ez430-rf2500 Guillaume Salagnac November 29, 2011

2 2 Embedded Systems Wikipedia An embedded system is a computer system designed for specific control functions within a larger system, often with real-time computing constraints. It is embedded as part of a complete device often including hardware and mechanical parts.

3 Consumer Electronics 3

2 Two general-purpose digital I/O pins connected to green and red LEDs for visual feedback

4 Highly integrated, ultra-low-power MSP430 MCU with 16-MHz ez430-rf2500 performance SLAU227A.pdf p.2 Two general-purpose digital I/O pins connected to green and red LEDs for visual feedback Interruptible push button for user feedback Spy Bi-Wire & MSP430 Appliation UART Pushbutton 2x LEDs CC2500 Chip Antenna USB Powered MSP430F Accessible Pins Figure 1. ez430-rf

5 ez430-rf2500 SLAU227A.pdf p.3 Figure 2. ez430-rf2500 Battery Board 2. Kit Contents, ez430-rf2500 The hardware includes: Two ez430-rf2500t target boards One ez430-rf USB debugging interface 5

6 6 Low-power Operation Power 1mW 0.1µW Time

7 7 Outline 1 Introduction 2 Schematics and Pinout 3 Internal structure 4 Digital Input/Output 5 Interrupts 6 Managing time 7 Serial Communication 8 Analog Input/Output 9 Conclusion

8 Target board schematics SLAU227A.pdf p.16 8

9 9 Target board PCB layout SLAU227A.pdf p.17 Top Layer Bottom Layer Figure 12. ez430-rf, USB Debugger, PCB Layout Figure 13. ez430-rf2500t, Target Board, PCB Layout 17

10 10 Figure 8. ez430-rf, USB Debugging Interface, Schematic Debugger board schematics SLAU227A.pdf p ez430-rf2500 Schematics

11 11 Debugger board schematics SLAU227A.pdf p.15 Figure 9. ez430-rf, USB Debugging Interface, Schematic

12 12 SLAS504B JULY 2006 REVISED JULY 2007 MSP430F2274 device pinout SLAS504B.pdf p.5 MSP430x22x4 device pinout, RHA package P2.5/Rosc DVCC DVCC TEST/SBWTCK P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 DVSS XOUT /P2.7 XIN /P2.6 DVSS RST/NMI/SBWTDIO P2.0/ACLK /A0/OA 0I0 P2.1/TAINCLK /SMCLK /A1/OA0O P2.2/TA 0/A2/OA0I1 P3.0/UCB 0STE /UCA 0CLK /A5 P3.1/UCB 0SIMO /UCB 0SDA P1.1/TA 0 P1.0/TACLK /ADC 10CLK P2.4/TA 2/A4/VREF+/VeREF+/OA1I0 P2.3/TA 1/A3/VREF /VeREF /OA1I1/OA1O P3.7/A7/OA 1I2 P3.6/A6/OA 0I2 P3.5/UCA 0RXD /UCA 0SOMI P3.4/UCA 0TXD /UCA 0SIMO P4.7/TBCLK P4.6/TBOUTH/A15/OA 1I3 P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE AVSS AVCC P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB0/A12/OA0O P4.4/TB1/A13/OA1O P4.5/TB2/A14/OA0I3

13 Spy Bi Wire Reg SPI, I2C 13 MSP430F2274 Functional Block Diagram SLAS504B.pdf p.6 RST/NMI NOTE: See port schematics section for detailed I/O information. MSP430x22x4 functional block diagram VCC VSS P1.x/P2.x P3.x/P4.x 2x8 2x8 XIN XOUT ACLK Basic Clock System+ SMCLK MCLK Flash 32kB 16kB 8kB RAM 1kB 512B 512B ADC10 10 Bit 12 Channels, Autoscan, DTC OA0, OA1 2 Op Amps Ports P1/P2 Ports P3/P4 2x8 I/O Interrupt 2x8 I/O capability, pull up/down pull up/down resistors resistors 16MHz CPU incl. 16 Registers MAB MDB Emulation (2BP) JTAG Interface Spy Bi Wire Brownout Protection Watchdog WDT+ 15/16 Bit Timer_A3 3 CC Registers Timer_B3 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C RST/NMI NOTE: See port schematics section for detailed I/O information.

14 14 MSP bit Memory Map SLAU144D.pdf p.1-4

15 15 Outline 1 Introduction 16MHz CPU incl. 16 Registers Emulation (2BP) JTAG Interface Spy Bi Wire MAB MDB Brownout Protection Watchdog WDT+ 15/16 Bit Timer_A3 3 CC Registers Timer_B3 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C 2 Schematics and Pinout RST/NMI NOTE: See port schematics section for detailed I/O information. MSP430x22x4 functional block diagram 3 Internal structure 4 Digital Input/Output 5 Interrupts 6 Managing time VCC XIN XOUT ACLK Basic Clock Flash System+ SMCLK 32kB 16kB MCLK 8kB 16MHz MAB CPU incl. 16 Registers MDB Emulation (2BP) JTAG Brownout Interface Protection Spy Bi Wire VSS RAM 1kB 512B 512B ADC10 10 Bit 12 Channels, Autoscan, DTC Watchdog WDT+ 15/16 Bit OA0, OA1 2 Op Amps Timer_A3 3 CC Registers P1.x/P2.x 2x8 Ports P1/P2 2x8 I/O Interrupt capability, pull up/down resistors Timer_B3 3 CC Registers, Shadow Reg P3.x/P4.x 2x8 Ports P3/P4 2x8 I/O pull up/down resistors USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C 7 Serial Communication RST/NMI NOTE: See port schematics section for detailed I/O information. 8 Analog Input/Output 9 Conclusion 6 POST OFFICE BOX DALLAS, TEXAS POST OFFICE BOX 1443 HOUSTON, TEXAS

16 GPIO Port Registers Figure 10. ez430-rf2500t, Target Board and Battery Bo P1DIR: direction, 0=in, 1=out P1OUT: set output P1IN: read input 16

17 17 Example char *P5OUT = (char*) 0x0042; *P5OUT = 0x13; volatile unsigned char P5OUT = asm("0x0042"); P5OUT = 0x13; #include <io.h> P5OUT = 0x13;

18 18 GPIO Port Schematics Example (from another MSP430) input/output schematic (continued) port P3, P3.1, input/output with Schmitt trigger SYNC MM STC STE P3SEL.1 P3DIR.1 DCM_SIMO P3OUT1 (SI)MO0 From USART : Input 1: Output Pad Logic P3.1/SIMO0 P3IN.1 SI(MO)0 To USART0 EN D P3SEL: 0=GPIO, 1=another peripheral

19 MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER Pin Sharing SLAS504B.pdf p.9 SLAS504B JULY 2006 REVISED JULY 2007 P1.0/TACLK/ ADC10CLK NAME TERMINAL DA NO. Terminal Functions, MSP430x22x4 RHA NO. I/O I/O General-purpose digital I/O pin Timer_A, clock signal TACLK input ADC10, conversion clock DESCRIPTION P1.1/TA I/O General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: OUT0 output/bsl transmit P1.2/TA I/O General-purpose digital I/O pin Timer_A, capture: CCI1A input, compare: OUT1 output P1.3/TA I/O General-purpose digital I/O pin Timer_A, capture: CCI2A input, compare: OUT2 output P1.4/SMCLK/ TCK P1.5/TA0/ TMS P1.6/TA1/ TDI/TCLK I/O General-purpose digital I/O pin / SMCLK signal output Test Clock input for device programming and test I/O General-purpose digital I/O pin / Timer_A, compare: OUT0 output Test Mode Select input for device programming and test I/O General-purpose digital I/O pin / Timer_A, compare: OUT1 output Test Data Input or Test Clock Input for programming and test P1.7/TA2/ I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output TDO/TDI Test Data Output or Test Data Input for programming and test P2.0/ACLK/A0/OA0I0 8 6 I/O General-purpose digital I/O pin / ACLK output ADC10, analog input A0 / OA0, analog input I0 P2.1/TAINCLK/SMCLK/ A1/OA0O P2.2/TA0/ A2/OA0I1 P2.3/TA1/ A3/V REF /V eref /OA1I1/OA1O 9 7 I/O General-purpose digital I/O pin / Timer_A, clock signal at INCLK SMCLK signal output ADC10, analog input A1 / OA0, analog output 10 8 I/O General-purpose digital I/O pin Timer_A, capture: CCI0B input/bsl receive, compare: OUT0 output ADC10, analog input A2 / OA0, analog input I I/O General-purpose digital I/O pin Timer_A, capture CCI1B input, compare: OUT1 output ADC10, analog input A3 / negative reference voltage output/input OA1, analog input I1 / OA1, analog output P2.4/TA2/ A4/V REF+/V eref+ /OA1I I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output ADC10, analog input A4 / positive reference voltage output/input OA1, analog input I0 P2.5/ 3 40 I/O General-purpose digital I/O pin 19

20 20 " Ports 1 et 2 avec interruptions GPIO " Registres Port Schematics PxIFG (flag) et Example PxIE (interrupt enable) (from another MSP430) input/output schematic port P1, P1.0 to P1.7, input/output with Schmitt trigger P1SEL.x P1DIR.x Direction Control From Module P1OUT.x Module X OUT Pad Logic P1.0/TACLK.. P1.7/TA2 P1IN.x Module X IN P1IRQ.x EN D P1IE.x Q P1IFG.x Interrupt Flag EN Set Interrupt Edge Select P1IES.x P1SEL.x

21 21 GPIO Example #include <io.h> #define BIT_GREEN (1 << 1) #define BIT_RED (1 << 0) void wait(unsigned int n) { int i; for(i=0;i<n;i++) { asm(" nop;"); asm(" nop;"); } } int main(void) { unsigned char b; P1DIR = (BIT_GREEN BIT_RED); P1SEL &= ~(BIT_GREEN BIT_RED); P1OUT &= ~(BIT_GREEN BIT_RED); b = 0x01; while (1) { wait(50000); wait(50000); wait(50000); wait(50000); P1OUT = b; b <<= 1; if (b == 0x4) b = 0x01; } return 0; }

22 22 Bitwise Operators in C...illustrated with non-c syntax A = 0b ~A = 0b A<<2 = 0b A<<2 = 0b A = 0b => A=0b A&=~0b => A=0b A^= 0b => A=0b

23 23 Outline 1 Introduction 16MHz CPU incl. 16 Registers Emulation (2BP) JTAG Interface Spy Bi Wire MAB MDB Brownout Protection Watchdog WDT+ 15/16 Bit Timer_A3 3 CC Registers Timer_B3 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C 2 Schematics and Pinout RST/NMI NOTE: See port schematics section for detailed I/O information. MSP430x22x4 functional block diagram 3 Internal structure 4 Digital Input/Output 5 Interrupts 6 Managing time VCC XIN XOUT ACLK Basic Clock Flash System+ SMCLK 32kB 16kB MCLK 8kB 16MHz MAB CPU incl. 16 Registers MDB Emulation (2BP) JTAG Brownout Interface Protection Spy Bi Wire VSS RAM 1kB 512B 512B ADC10 10 Bit 12 Channels, Autoscan, DTC Watchdog WDT+ 15/16 Bit OA0, OA1 2 Op Amps Timer_A3 3 CC Registers P1.x/P2.x 2x8 Ports P1/P2 2x8 I/O Interrupt capability, pull up/down resistors Timer_B3 3 CC Registers, Shadow Reg P3.x/P4.x 2x8 Ports P3/P4 2x8 I/O pull up/down resistors USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C 7 Serial Communication RST/NMI NOTE: See port schematics section for detailed I/O information. 8 Analog Input/Output 9 Conclusion 6 POST OFFICE BOX DALLAS, TEXAS POST OFFICE BOX 1443 HOUSTON, TEXAS

24 24 Interrupts An interrupt can only occur when both bit General Interrupt Enable (GIE) set in status register Interrupt Enable bit set in specific peripheral register e.g. PxIE in ports 1 and 2 Acknowledgement is implicit for single-source interrupts necessary for multiple-source interrupts e.g. PxIFG in port 1 and 2 Interrupt nesting is disabled by default GIE is cleared upon entering ISR

25 25 ISR Example using GCC intrisincs interrupt (PORT1_VECTOR) PORT1_ISR(void) { if (P1IFG & (P1IE & (1<<2) )) { SWITCH_RED_LED(); } } P1IFG=0;

26 26 MSP bit Memory Map SLAU144D.pdf p.1-4

27 MIXED SIGNAL MICROCONTROLLER MSP430F2274 SLAS504B JULY 2006 REVISED Peripherals JULY 2007 mapping SLAS504B.pdf p PERIPHERALS WITH BYTE ACCESS (continued) Basic Clock System+ Basic clock system control 3 Basic clock system control 2 Basic clock system control 1 DCO clock frequency control Port P4 Port P3 Port P2 Port P1 Port P4 resistor enable Port P4 selection Port P4 direction Port P4 output Port P4 input Port P3 resistor enable Port P3 selection Port P3 direction Port P3 output Port P3 input Port P2 resistor enable Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input Port P1 resistor enable Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input Special Function SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 BCSCTL3 BCSCTL2 BCSCTL1 DCOCTL P4REN P4SEL P4DIR P4OUT P4IN P3REN P3SEL P3DIR P3OUT P3IN P2REN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN P1REN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN IFG2 IFG1 IE2 IE1 053h 058h 057h 056h 011h 01Fh 01Eh 01Dh 01Ch 010h 01Bh 01Ah 019h 018h 02Fh 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h 027h 026h 025h 024h 023h 022h 021h 020h 003h 002h 001h 000h

28 28 Outline 1 Introduction 16MHz CPU incl. 16 Registers Emulation (2BP) JTAG Interface Spy Bi Wire MAB MDB Brownout Protection Watchdog WDT+ 15/16 Bit Timer_A3 3 CC Registers Timer_B3 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C 2 Schematics and Pinout RST/NMI NOTE: See port schematics section for detailed I/O information. MSP430x22x4 functional block diagram 3 Internal structure 4 Digital Input/Output 5 Interrupts 6 Managing time VCC XIN XOUT ACLK Basic Clock Flash System+ SMCLK 32kB 16kB MCLK 8kB 16MHz MAB CPU incl. 16 Registers MDB Emulation (2BP) JTAG Brownout Interface Protection Spy Bi Wire VSS RAM 1kB 512B 512B ADC10 10 Bit 12 Channels, Autoscan, DTC Watchdog WDT+ 15/16 Bit OA0, OA1 2 Op Amps Timer_A3 3 CC Registers P1.x/P2.x 2x8 Ports P1/P2 2x8 I/O Interrupt capability, pull up/down resistors Timer_B3 3 CC Registers, Shadow Reg P3.x/P4.x 2x8 Ports P3/P4 2x8 I/O pull up/down resistors USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C 7 Serial Communication RST/NMI NOTE: See port schematics section for detailed I/O information. 8 Analog Input/Output 9 Conclusion 6 POST OFFICE BOX DALLAS, TEXAS POST OFFICE BOX 1443 HOUSTON, TEXAS

29 Oscillators and clocks 29

30 Basic Clock Module 3$4, !"#$% &'(%) *(+,'-.!'(%) 9$"42": 08638; 84*87 U!"#$% &'(%) *(+,'-. /012(+,%1$(0 $/012 SLAU144D.pdf p.5-3 =%AQ 4JFC( 879:+38; 7%FD() +L (FC( $%&%'() *+*,*-*. &"#$ 6> :+>2 3FGHI 9:> 9/< L0 87 9: U 876OO 9:+6OO 965: L :+ 6CH%FF@DG) >N8=2 LL $/0= :,677 9:,> =%AQ 4JFC( 7%FD() L+ +L ++ $%&%'() *+*,*-*. L +!"#$ 9:,/< 9: 3GAA(HD(' GAFB RS(A 9:, AGD T)(C(AD GA""HS%T =@%A >BCD(E 3FGHI 9:,65: 9:, 6CH%FF@DG) U =6$2 033 =G'JF@DG) $36M >3?L M>N82 $362 >N8> $/0>2 >3?+ MGCH U L + GOO $3?(A()@DG) A $36 AP+ L + =%AQ 4JFC 7%FD() $3638; L + $%&%'() *+*,*-*. L + %!"#$ >JK >BCD(E 3FGHI ' ()*+, -+./0+1%2+0/3/0 "4)05 678/7*/)9: 30

31 31! L>' %<O' F762 J<&?-?;<&C> J'&;''4 &>' %('AB'4CD?'9'C&'5 JD &>' 6,72 J<&? )45 &>' 4'2& ><=>'( %('AB'4CD?'& JD 6,72TQE U>'4 6,72 3 R#>- &>' F762 J<&? >)O' 4: '%%'C& J'C)B?' &>' 6,7 <? )9(')5D SLAU144D.pdf )& &>' ><=>'?& p.5-7?'&&<4= %:( &>'?'9'C&'5./012 ()4='E Digitally-Controlled Oscillator, :0$%"' ;&/< ="35- "3+ =>?@< >2-0# % 6,7 KRRRR XYZ./01 3 Q! QRRR XYZ./01 3 #./013R QRR XYZ 6,73R 6,73Q 6,73K 6,738 6,73V 6,73! 6,73W 6,73#

32 %&' 17;"<7;'8 /74'3, :7 $.8' = '4 ;0:& :&' L* 32 "';%< Sleep =4$$#(& modes =+(-40"&'+( +> A#B';#- B- SLAU144D.pdf!"#$%&'() p.2-14 *+, +#G +,, O LL P H.:#(QD!I,!!G #F, #+G?, $G!,, K LL M+K K LL M!@!K GG +! #I ##,@?,@I,@#,@#, H( J*(, J*(! J*(+ J*($ N<'8.:065 (74'3

33 33 Timers A timer is a 16-bit counter which counts cycles from a selectable clock source in a certain way (up, down, continuous) Can be used in two ways : memorize its value on certain events (capture mode) or trigger an interrupt when reaching a given value (compare mode) Each timer has two interrupt lines: implicit acknowledgement: TxCCR0 vector ack. must be done by software: TxIV vector

34 34 Timer A /"0-%$ !"#$%&' "90%9#!"#$%&' ()*%+,-.*"+) SLAU144D.pdf p ?'7* %=&;Q 3F//AN0,50 4%0!-. %&'() *+,-. 3F%NO F%NO /4%NO,E%NO...!!.!! 5?H?87*!I"IJIK %=7)* 3F%NB!L##M?+ 3?'7* 3FB B% %&6:+ 4&87 A@2. /7+ 3F,PD!!"$!!"#!!"/ %%,/0 %40 =&>?; %1< /%/ %%,"F %%,"G DE5 <%%...!!.!! %)(+6*7 4&87 3?'7* %=&;Q /9:;.!!-. 3F%%B" %%, %&'()*)+&* " A@2" %FS /%%, R F AE.! /7+ 3F%%B" %%,PD A@ (6+ 2:?+" 5 3?'7* %=&;Q B7C7+ 123" /?>:)= S1B

35 35 Timer B /"0-%$ !"#$%&' '5+.6 7"80%8#!"#$%&' ()*%+,-.*"+) SLAU144D.pdf p K88AN4,34 1?&6) $=%;O!-. 2$4 *+,-. /0123 1K$NU S$NU 82$NU...!!.!! 3?E?76)!FGFHFI 1K$NMBD4 M)%5' N%(7 N%>?; $=6() 1K$NB!+##J?* 1?&6) 1KB B$ I!.!G!+ $%5:* 2%76 $R1N4...!!.!! A@0. 86* 1K,LM!!"$!!"%!!"&!!"'!!"(!!") $$,84 $24 =%>?; $/<!!"# $$,+S.. $('*5)6 $$,+K.! 2%76 MR3!. 1?&6) $=%;O <$$!! $NN34 $$, <$$.. 1KBP..! A@0.!. 0DF3/QR!! 8$8. 89:;! M)%5' N%(7 N%>?; $$B- $$BH $$B!!-. 1K$$B+ N%(7 $%&'()6 N(*;T 1K$N+ $%&'()(*%) + A@0+ $SD.! 86* 1K$$B+ $$,LM A@0. /01 /5*'5* 0:?*+ 3 1?&6) $=%;O B6C6* /01+ 8?>:(= /012/34 D/B

36 C&'3 6&83<-3< %=>>?4 A&-9' 0&' 0-*'1 -. -/ 0&' 3'A )'1-+, -. <1'80'1 36 Timers: Up mode."/0%$ ) 6,7$ 4& %=>>?4 0-*'1 1' (30-3< /1+* E'1+7 F/ () *+,' -..'9'60', A&'3 0&' 0-*'1 ;89(' -. <1'80'1 0&83 0&' 0-*'1 -**',-80'9: 1' (30-3< /1+* E'1+7 SLAU144D.pdf p & %=>>?4."/0%$ 12 3:4 5) 6,7$.;*/ <$++"-/ 4& %-*'1 >9+6I %&' %=>>?4 >>F5G -30'11()0 /98< -..'0 A&'3 0&' 0-*'1 8, &' %=>>?4 ;89('7 %&' %=F5G -30'11()0 /98< -..'0 A&'3 0&' 0-*'1 8,0-+9 /1+* %=>>?4 0+ E'1+7 5-<(1'!"##H.&+A. 0&' /98<.'0 6:69'7 %&' %=>>?4 >>F5G -30'11()0 /98< -..'0 A&'3 0&' 0-*'1 8, &' %=>>?4 ;89('7 %&' %=F5G -30'11()0 /98< -..'0 A&'3 0&' 0-*'1 8,0-+9 /1+* %=>>?4 0+ E'1+7 5-<(1'!"##H.&+A. 0&' /98<.'0 6:69'7."/0%$ 12 3:4 5) %-*'1 6,7$.;*/ >>?4##! <$++"-/ >>?4 4&!& >>?4##! >>?4 4& J'0 %=F5G %-*'1 >9+6I J'0 %=>>?4 >>F5G %-*'1 >>?4##! >>?4 4&!& >>?4##! >>?4 4& J'0 %=F5G J'0 %=>>?4 >>F5G!"#$%&$% '"( )(*&+, -(%&.'(* /0!!-1

37 Timers: Continuous mode 5 6,-+"-0,07 8,9$!"#$ :-+$%;*<7 SLAU144D.pdf p.12-8 %>??@!2 %>??@!( DAAAA& %>??@D2 %>??@D( %>??@D0 %>??@!1 %>??@!0 %>??@D1 + D + D + D +! +! +! %,/',*+'4617. (1* 2' 54)0-('0 C,+& )+&'4 /)0'. 1. C'77< C&'4' %>??@D,. -.'0 1. +&' 5'4,)0 4'3,.+'4: %&',4 &1*07,*3,. /)4' ()/57'=.,*(' +&'.-/ )8 37

38 !"#$%&' 38 Timers: Up-down mode (.+).+ /-"+ "- /)78,9- :,;$ SLAU144D.pdf p $JJJJ& -.//0$ -.//0! -.//0" $& W'*9 -,4' Q73@73 R:9' SN -:++2'FH'3 Q73@73 R:9' "N -:++2'F0'6'3 TUV! TUV! TUV! TUV! -.LJP -.LJP TUV$ TUV$ TUV" TUV" TUV" TUV" L(3'557@3 T='(36

39 39 Outline 1 Introduction 16MHz CPU incl. 16 Registers Emulation (2BP) JTAG Interface Spy Bi Wire MAB MDB Brownout Protection Watchdog WDT+ 15/16 Bit Timer_A3 3 CC Registers Timer_B3 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C 2 Schematics and Pinout RST/NMI NOTE: See port schematics section for detailed I/O information. MSP430x22x4 functional block diagram 3 Internal structure 4 Digital Input/Output 5 Interrupts 6 Managing time VCC XIN XOUT ACLK Basic Clock Flash System+ SMCLK 32kB 16kB MCLK 8kB 16MHz MAB CPU incl. 16 Registers MDB Emulation (2BP) JTAG Brownout Interface Protection Spy Bi Wire VSS RAM 1kB 512B 512B ADC10 10 Bit 12 Channels, Autoscan, DTC Watchdog WDT+ 15/16 Bit OA0, OA1 2 Op Amps Timer_A3 3 CC Registers P1.x/P2.x 2x8 Ports P1/P2 2x8 I/O Interrupt capability, pull up/down resistors Timer_B3 3 CC Registers, Shadow Reg P3.x/P4.x 2x8 Ports P3/P4 2x8 I/O pull up/down resistors USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C 7 Serial Communication RST/NMI NOTE: See port schematics section for detailed I/O information. 8 Analog Input/Output 9 Conclusion 6 POST OFFICE BOX DALLAS, TEXAS POST OFFICE BOX 1443 HOUSTON, TEXAS

40 40 Serial Communication Examples of serial protocols: Morse code, USB, Firewire, USB, Ethernet, RS232, I 2 C, SPI... The MSP430F2274 has two UARTs (both interrupt-capable): USCI_A0: UART, I 2 C, SPI, IrDA USCI_B0: SPI, I 2 C Asynchronous communication (UART) : Both ends have to agree on the communication protocol: encoding, frame length, reference frequency,...

41 41!"#$#A C0,D-. Asynchronous Serial Protocol <+=8(' #C)()9*'( <,(7)* )0- &'() /-3 >+3*4/. 50+S% 6% H6=;3-!"##R. 7+%565/5 +> 4 5/43/ 96/. 5-8-% +3-6=0/,4/4 96/5. 4% -8-%N+,,N%+ D436/: 96/. 4% 4,, / Q4,,3-55#96/ *+,-P. 4%, +%- +3 /S+ 5/+D 96/5< )0- &2X1J 96/ 7+%/3+?5 /0-,63-7/6+% +> /0- /34%5>-3 4%, 5-?-7/5 U1J +3 X1J >635/< U1J#>635/ 65 /:D674??: 3-@;63-, >+3 &'() 7+**;%674/6+%< SLAU144D.pdf p ) \] \^ \_ '\ A' 1A 1A X43C 1D47- YLD/6+%4? J6/. 2+%,6/6+%[ YR%, 1/+D J6/. &21AJ T![ YA436/: J6/. &2AGZ T![ Y',,3-55 J6/. &2XL\GE T!][ Y`/0 \4/4 J6/. &2_J$) T ][!-+4'(5)6 "'(+)6 #,778-+9)*+,- $-*'(:)9';!/01 2,3'!"#"

42 42!"#$ $%&'()*+&,(%-!./0 1()2 USCI Block Diagram: UART Mode :,;*'2 <= B6(+C D,5;'57-!./0 1()2 E!#"FG# H IJ SLAU144D.pdf p >F4K4 4,,&, C)*G8 3.>F4>> 3.%E; ? 3.;E>% 3.>F?>0K N 3.C4 17+ C)*G8 3.E4 >797<=7 1+*+7 %*9I<A7 17+ >FKC@ >FKC@ ?> ;;>:3.K;/4 3.K>>F6/ 3.K>>FC/5 3.K>>FC4 >797<=7?(JJ7, 3.2>F?3C 3.K>4H B 3./K1M4H! K,;- ;79&'7, 2 3.2>F! >797<=7 1I<J+ >7G<8+7, 2 2! 3.64H 3.6-> 3.%1? 3.L?KM 3.-?4H 3.114/5 3.2?>5 3.2./0 22!B -./0 2! 6,789*)7,:;<=<'7, 1%./0!2?>./0 1%./0!! %&'()*+&, >797<=7.)&9P M,*A8O<+.)&9P $ D 3.?>C5 3.?>15 3.E1!B 3.64H 3.6-> 3.%1? 3.L?KM 3.K>4H M,*A8O<+ 1I<J+ >7G<8+7, 2 M,*A8O<+?(JJ7, 3.2MF?3C K,;- 4A9&'7, B! 3.2MF 3.K>MF6/5 M,*A8O<+ 1+*+7 %*9I<A MFKC@ 3.MF?>0 3.MF-;;> N 3.%E; ?

43 !"#$ $%&'()*+&,(%- ".$ /()0 USCI Block 8,9*'0 :; Diagram: <:=!"#$ SPI ".$ /()0Mode SLAU144D.pdf p.14-4 B3539:3 )=6=3 *65C9A3 )3=,&L- B3539:3 <FDD32,&.BG<,H,&.)L*J B3539:3 )C9D= B3E94=32 +!! +,&*)<,&I<JK,&))-'.,&.<B. <9= /0% %&'( )*&'( ++ +!!+ <B&'(!" :9;32 &7>5? 89235=9>AN 1C643 6A; 1>7629=O,&.&'( )*&'(!!,&*)<,&I<JK,&.)J*L K26A4M9= )C9D= B3E94=32,&*L8-. K26A4M9= <FDD32,&.KG<,H R,&.)K- K26A4M9= -A6Q73 &>A=2>7 )3=,&H- K26A4M9= )=6=3 *65C9A3 43

44 44!"#$ $%&'()*+&,(%- $.# /() USCI Block Diagram: I 2 8,9*'1 :; <:=!"#$ $ C Mode. #/()1 SLAU144D.pdf p.17-4,&%!+,&?&-o MN@ %::0122,&!M% A )E8F< A1G82<10,&.)7% A ;HFF10,&!AI;,J KL& )<4<1 *43E8@1 C04@2D8< ;HFF10,&!CI;,J C04@2D8< )E8F< A1G82<10 )5491 %::0122,&!)%,&)'%!+,&.)&',&))-'. ;8< &5=3>?1@104<=0,&.;A.,&!&'( %&'( )*&'( ++ +!!+ ;A&'(!B / :10,&*)C )*&'(!!

45 45 Outline 1 Introduction 16MHz CPU incl. 16 Registers Emulation (2BP) JTAG Interface Spy Bi Wire MAB MDB Brownout Protection Watchdog WDT+ 15/16 Bit Timer_A3 3 CC Registers Timer_B3 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C 2 Schematics and Pinout RST/NMI NOTE: See port schematics section for detailed I/O information. MSP430x22x4 functional block diagram 3 Internal structure 4 Digital Input/Output 5 Interrupts 6 Managing time VCC XIN XOUT ACLK Basic Clock Flash System+ SMCLK 32kB 16kB MCLK 8kB 16MHz MAB CPU incl. 16 Registers MDB Emulation (2BP) JTAG Brownout Interface Protection Spy Bi Wire VSS RAM 1kB 512B 512B ADC10 10 Bit 12 Channels, Autoscan, DTC Watchdog WDT+ 15/16 Bit OA0, OA1 2 Op Amps Timer_A3 3 CC Registers P1.x/P2.x 2x8 Ports P1/P2 2x8 I/O Interrupt capability, pull up/down resistors Timer_B3 3 CC Registers, Shadow Reg P3.x/P4.x 2x8 Ports P3/P4 2x8 I/O pull up/down resistors USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C 7 Serial Communication RST/NMI NOTE: See port schematics section for detailed I/O information. 8 Analog Input/Output 9 Conclusion 6 POST OFFICE BOX DALLAS, TEXAS POST OFFICE BOX 1443 HOUSTON, TEXAS

46 46 ADC10 /.0,)1 2% 3$4!"#$% 56*-7 ".80)89!"#$% &'()*+,-(.*' ;*4HDG " / 4HDIN@ %4HD/ ;4HDG 35</"%4 / "!PU;.+ /9U;.7!9U; 4*B*7*+R* 4HDIJ KJ<-LW"3E 3; << ; 4HD##8; *4HD## 3; << 4*BPL KJ<-L S // /" "/ "" %4HD/ %4HD" 3Y2. <IJ%HXL 3; %% 35</"I%< 3" 3/ 3! 3$ 3S 3U 3T 3V 3/! Z 3/$ Z 3/S Z 3/U Z """" """/ ""/" ""// "/"" "/"/ "//" "/// /""" /""/ /"/" /"// //"" //"/ ///" //// %4HD! / " 35</"IJ 35</"%%H=L 35</"5K;L %&'()* ;4## ;4G "" &+, 5161,*7 "/ 3<=> -.), /"##012 %34 8/ 99 8: /"?<=> %8- <.+6*72 // %?<=> 35</"<=> %-%L MN%O K%%- HJ< "" %3?F<IJ %-K " "/ 8S8:8/T8TS / %Q+R 3; << 35</"5D 35</"%-@L?%< [ KJ<-LW"ME 4*BPL 35</"?H? 4 + <.+27.))*7 43?C D)&AEC F*71(E*71&)A 4 35</"%3 3; %% 35</"<@ 35</"@M 35</"M/ Z?%FS$"L!!LL,*61R*A.+)Q9 <E&++*)A 3/!#3/U 21*, 2. RE&++*) 3// 1+.2E*7,*61R*A [@3/.+?%FS$"L!"L!,*61R*A

47 47 Conclusion: MSP430 ez430-rf2500 Development platform cheap very limited resources Microcontroller architecture all peripherals are memory-mapped low-power modes Not presented: CC2500 Radio Module wireless communication

The digital I/O is configured with user software. The setup and operation of the digital I/O is discussed in the following sections.

The digital I/O is configured with user software. The setup and operation of the digital I/O is discussed in the following sections. Digital I/O Introduction www.ti.com 8. Digital I/O Introduction MSP43 devices have up to eight digital I/O ports implemented, P to P8. Each port has up to eight I/O pins. Every I/O pin is individually