Factors which influence in many core processors

Transcription

1 Factors which influence in many core processors ABSTRACT: The applications for multicore and manycore microprocessors as RISC-V are currently useful for the advantages of their friendly nature, compared to previous chips, which have caused a great demand for these multi-core or many-core processors used in parallel computing for fluid emulation mainly on the atmosphere of the earth, and other applications. The result of this research, is the focus in determining the factors that influence high-performance systems, after reviewing and considering various authors, for its realization. This research focuses on two factors which influence on the data in computer systems shared memory (multi-core and many-core architecture) being these topology and memory consistency.

2 Factors which influence the performance Algorithms Topology System operating Architecture Taxonomy Heterogeneous Manycore Programming Model Homogeneous Languages programming Technology Memory Model Memory Cache

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4 Software-Defined Error-Correcting Codes Errors in memory often result in system-level crashes. Current error-correction techniques are costly and are oblivious to the underlying data stored in memory. SDECC pushes beyond current error-correction capabilities by combining three layers: System-level fault tolerance Error-correcting codes Side-information about data and instructions in memory à RISC-V! J

5 WASP-SC Austin Harris, Rohith Prakash The University of Texas at Austin SPARK Lab Goal: defend against utilization side-channels E.g. shared memory controllers, hardware accelerators Normalization (e.g. partitioning, worst-case) infeasible Solution: shape victim s utilization to be statistically indistinguishable across different inputs Optimally minimizes slowdown within provably configurable privacy bounds Modify Rocket to have cores sharing SHA3 accelerator Send commands through queue with our traffic shaping defense

6 VSSM

7 Sub-microsecond Adaptive Voltage Scaling in a 28nm RISC-V SoC Demo: Running user-mode programs in Linux on RISC-V silicon to demonstrate integrated power management Synchronizers To scope 1.8V 1.0V To scope 1.0V VOLTAGE AND CLOCK GENERATION (0.4 mm 2 ) DCDC toggle Back-Bias Generator NWELL PWELL 48 switched-capacitor DC-DC unit cells FSM... + DC-DC controller Adaptive clock generator V out V ref core clk POWER MANAGEMENT (0.1 mm 2 ) Toggle Counter Clock Counter CORE (1.07 mm 2 ) Rocket Core Scalar RF int 16KB Scalar Inst. Cache (Custom 8T SRAM Macros) Z-scale PMU 8KB Scratchpad Set body bias Set DC-DC V out Branch Prediction FPU 32KB Shared Data Cache (Custom 8T SRAM Macros) Vector Accelerator Vector Issue Unit... (16KB Vector RF uses eight custom 8T SRAM macros)... int int int int int Crossbar Functional units (64-bit Int. Mul., SP/DP FMA) Arbiter SRAM BIST Vector Memory Unit 8KB Vector Inst. Cache (Custom 8T SRAM Macros) Async. FIFO/Level shifters between domains Digital IO pads to wire-bonded chip-on-board UNCORE To/from off-chip FPGA FSB and DRAM INTEGRATED MEASUREMENT Programmable current mirror load I load V out waveform reconstruction I ref Voltage and Clock Generation Voltage Setting SC-DCDC Unit Cells Rocket Processor and Vector Accelerator Power Measurement Counters Core Clock Adaptive Clock Generator SC-DCDC Control PMU Pre-divide SC-DCDC Toggle Clock Power management algorithm loaded into scratchpad memory (compiled from C/C++) 1GHz Reference SC-DCDC Unit Cells Programmable counter Programmable counter Z-scale PMU execute power management algorithm Ben Keller 5 th RISC-V Workshop November 29, 2016

8 RV128 The Path to Embedded Exascale Courtesy Kogge et als 2008

9 UNNI: An open source core for easy transition from ARM Cortex-M0 to RISC-V Von Neumann architecture with 2-stage pipeline Optimized for ASIC implementation Written in SystemVerilog Low latency interrupt handling with tail-chaining and pre-emption Mikael Korpi OKiM Technologies

10 Full-Featured RISC-V Debug Solution Tim Newsome It works in silicon! Download directly to flash Demo Setup: laptop gdb OpenOCD USB 32x16 LED Display SiFive board GPIO SiFive E300U Coreplex RV32ACFIM JTAG FT2232HL chip Implementations SiFive CorePlex in silicon IQ-Analog NanoRisc5 on FPGA Open Source Rocket Chip implementation gdb and OpenOCD code Black box testsuite More Information Debug list at

11 Syntacore RISC-V cores demos Alexander Redkin 5 th RISC-V workshop Nov info@syntacore.com

12 Syntacore introduction IP company 1. Develops and licenses energy-efficient programmable cores With RISC-V ISA 2. Full service to specialize these for the customer needs Workload analysis/characterization Workload-specific customization with tools/compiler support IP hardening at the required library node SoC integration and SW migration support 2

13 Baseline SCRx cores SCRx: a family of the state-of-the art RISC-V compatible synthesizable processor cores SCR1: RV32IC[EM] SCR3: RV32IMC[E] <= demo SCR4: RV32IMCF[D] SCR5: RV[32 64]IM[A]CFD <=demo Stable, configurable, available for evaluation Baseline: every core can be extended/customized 3

14 Thank you! 4

15 ASIP Designer - Automating ASIP Design Architecture Definition, Optimization, and Implementation User-Defined Architecture Processor Model nml nml 1 Algorithms User-Defined Algorithms Architectural Optimization and Software Development C 3 ASIP Synthesis ASIP Designer creates full SDK Compiler-in-the-loop optimization Process starts with pre-existing example models RISC-V Starting point FMT ALU OPD Instruction Set RISC-V FMT Model MPY OPD FMT OPD SH Optimizing C Compiler Asm Binary Link RTL Generator Synthesizable RTL VHDL/Verilog ASIP Designer generates synthesizable RTL Performance/Power/Area Analysis seeds refinement/optimization 1 2 SDK Generation Architectural Optimization 2 3 HW Generation RTL Refinement Architecture Refinement Debugger & Profiler Instruction Set Simulator RTL Simulator ASIC FPGA RTL Synthesizer ASIP model is refined SDK is automatically adapted All elements stay in-sync 2016 Synopsys, Inc. 1

16 SHAVE: Software/Hardware Assurance Verified End-to-End Create practical, end-to-end assurance cases for mission critical software/hardware systems that run on COTS hardware. Case study: implement a crypto extension to RISC-V (like AES- NI), build a thin firmware layer and small application on top, and create an assurance case. Sponsored by the Air Force Research Laboratory (AFRL) and developed with funding from the Defense Advanced Research Projects Agency (DARPA) under contract number FA C Any views, opinions, findings, conclusions and/or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the United States Air Force, the Department of Defense or the U.S. Government.

17 LibreChainEDA Open Source IC Design Tool Flow Scripts Complete FOSS from concept to FPGA 100% Open Source EDA Tools IP-Xact based tool flows Design for Reuse best practices One stop shopping for installation