Lab 4 LVS and Post layout Simulation

Transcription

1 Lab 4 LVS and Post layout Simulation Objective: In this lab you will learn 1. How to check if your layout that you drew in lab 3 matches your schematic that you drew in lab How to do the post layout simulation using your custom layout. Create extracted view 1. In your library ECE433, open the layout view of the cell Inv. On the layout window click Verify à Extract, and then click OK. You can find the created extracted file in the library manager next to the other cell views of Inverter as it is shown in Fig.1. Fig. 1. Extracted view can be found next to the other cell views of Inv Double click on extracted to open it. The extracted view should look like Fig. 2. 1

2 Fig. 2. The extracted view for Inv Run LVS 1. On the layout window, click Verify à LVS. The LVS form should open (if any other window also opens, just click ok. Usually a welcome window opens as default). The LVS form is shown in Fig.3. You have to click Browse in this window and select the schematic and the extracted view of the cell Inv. 2

3 Fig. 3. LVS Form 1. Click Run in the LVS form. If both the windows (Schematic and Extracted) were saved correctly, you will receive the message shown in Fig. 4. (Therefore if the message shows that it failed, you need to go back and save these windows again). Or 3

4 Fig. 4. Message that shows your LVS job is completed and it either match or fail to match If you received the message as shown in Fig. 4, Click OK and then in the LVS form shown in Fig. 3, click on Output. The form should look like Fig. 5. Fig. 5. Output of the LVS 2. If your schematic matches your layout, you can see that it will say The net-lists match. If you get this message, it means that you have done the layout correctly. But if it says The net-lists failed to match, you need to find the problem and solve it. Then create the extracted file from your fixed layout and do the LVS again. In this file you can also find some hint where the problem is. You can also open the extracted file first and then click on Error Display in the LVS form shown in Fig 3. In this case a window will open that is 4

5 shown in Fig. 6. If you click Next in this window you can see that some lines in your extracted file is highlighted (you can change the highlight color in the error color field). The highlighted area shows you the location where the error is located at. Therefore you can use it as a hint for finding the problems in your layout. If the highlighted area is very small and you cannot see it, you can activate Auto-Zoom in this window. In this case every time you click Next, it will zoom to the position of the error. You can always zoom out using Shift + Z. Possible errors: Fig. 6. Open extracted file and then click error display for easier finding of errors I am pretty sure that a lot of you would have the following errors: 1. No n-well area under Metal1-N vias. You should create another n-well shown in green on top of the PMOS body. 5

6 Fig. 7 Possible error 1 2. Mistakenly put Metal1-P vias on n-well while Metal2-N vias on P substrate. Normally if you align the top n-well with PMOS body like shown in Fig. 7, and the DRC still gives you error, and you had to extend the n-well horizontally to avoid the errors, you have this kind of errors. 6

7 7 Revised by Hanfeng Wang 1/30/15

8 Fig. 8 Possible error 2: the vias should be attached like the figure shown above Post layout Simulation 1. The post layout simulation is very similar to the schematic simulation. You need to open the schematic view of the test_inv and follow all the steps of the schematic simulation in Lab 2. Or, you may have saved previous state, Session à Load state, usually the default the last state you saved. If you didn t save, you may have to follow the Lab2 ADE set up steps. The only difference is that you need to click Setup à Environment and type extracted before the word schematic in the switch view list. That is, you first have to select spectre as your simulator, add the model libraries and then use the extracted file for your simulation from Environment setting. You also need to choose the transient analysis and select the outputs to be plotted on schematic to run the simulation. Remember that if you do not select spectre simulation, you cannot change the environment settings, or add model libraries. 2. Click Run and see the simulation results. Fig. 7. Change the environment for post layout simulation The resulting waveform should not vary too much from Lab 2 outcome. 8

9 Fig. 8 Post layout waveform of inverter Save the state You can save the state in case future use. Two ways to save the state: with directory or cell view, I used to choose cell view. 9

10 Fig. 9 Select the cell view button to save the state By doing this, you may retrieve the state by double clicking it in your library manager. 10

11 Fig. 10 State visible in library manager 11