3DIC and the Hybrid Memory Cube

Transcription

1 3DIC and the Hybrid Memory Cube Dean Klein Micron Technology, Inc Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron s production data sheet specifications. Information, products, and/or specifications are subject to change without notice. All information is provided on an AS IS basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners Micron Technology, Inc. 1

2 The Need: Break Down the Memory Wall 4 Channel 3 Channel 2 Channel 2012 Micron Technology, Inc. 2

3 Reducing System Cost LGA Channel 3 Channel Socket Channel 2012 Micron Technology, Inc. 3

4 Managing System Complexity DDR 85 page specification 1 page of AC timing params 3 speed bins Standardization Time: < 3 yrs years 2012 Micron Technology, Inc. 4

5 Managing System Complexity DDR4 214 page specification 9 pages of AC timing params 12 speed bins for BOL (to 2400) DDR Standardized Time: >6 years and going 85 page specification 1 page of AC timing params 3 speed bins Standardization Time: < 3 yrs years 2012 Micron Technology, Inc. 5

6 Hybrid Memory Cube (HMC) Fast process logic and advanced DRAM design in one optimized package Power Efficient Smaller Footprint Increased Bandwidth Reduced Latency Lower TCO 6

7 Enabling Technologies Abstracted Memory Management Through-Silicon Via (TSV) Assembly Memory Vaults Versus DRAM Arrays Significantly improved bandwidth, quality and reliability versus traditional DRAM technologies Logic Base Controller Reduced memory complexity and significantly increased performance Allows memory to scale with CPU performance Innovative Design & Process Flow Incorporation of thousands of TSV sites per die reduces signal lengths and reduces power Enables memory scalability through parallelism Sophisticated Package Assembly Higher component density and significantly improved signal integrity 2012 Micron Technology, Inc. 7

8 HMC Architecture Start with a clean slate DRAM 8

9 HMC Architecture Re-partition the DRAM and strip away the common logic DRAM 9

10 HMC Architecture Stack multiple DRAMs DRAM 10

11 HMC Architecture Re-insert common logic on to the Logic Base die 3DI & TSV Technology DRAM7 DRAM6 DRAM5 DRAM4 DRAM3 DRAM2 DRAM1 DRAM0 Logic Chip Vault DRAM Logic Base 11

12 Request Write Data Logic Base Vault Control Vault Control Vault Control Memory Control Crossbar Switch HMC Architecture Memory Control Refresh Controller DRAM Sequencer Vault Control Write Buffer Crossbar Switch Read Buffer Read Data TSV Repair DRAM Repair Link Interface Controller Link Interface Controller Processor Links Link Interface Controller Logic Base Multiple high-speed local buses for data movement Advanced memory controller functions DRAM control at memory rather than distant host controller Reduced memory controller complexity and increased efficiency DRAM Link Interface Controller Detail of memory interface Vault 3DI & TSV Technology DRAM7 DRAM6 DRAM5 DRAM4 DRAM3 DRAM2 DRAM1 DRAM0 Logic Chip Vaults are managed to maximize overall device availability Optimized management of energy and refresh Self test, error detection, correction, and repair in the logic base layer Logic Base 12

13 HMC Architecture Link Controller Interface HMC-SR Options: 10 Gpbs, 12.5 Gbps or 15 Gbps HMC Host Example: 8 or 16 Transmit Lanes TX 16 Lanes RX RX 16 Lanes TX 8 or 16 Receive Lanes 13

14 TSV TSV TSV TSV TSV TSV TSV TSV Host Processor Memory Management Manufacturing Test Burn-in At-speed Functional Manage field maintenance and self test Manage 100+ different DRAM timing parameters Manage all present and future DRAM scaling and process variation issues DRAM Layer HOST Si Interposer DRAM Layer DRAM Layer DRAM Layer Re-drive Layer Non-managed DRAM (WIO, HBM, etc.) 14

15 TSV TSV TSV TSV TSV TSV TSV TSV Host Processor Memory Management Simple memory requests and responses. No DRAM timing to manage Functions moved to HMC for management Manufacturing Test Burn-in At-speed Functional Manage field maintenance and self test Manage 100+ different DRAM timing parameters Manage all present and future DRAM scaling and process variation issues DRAM Layer HOST Si Interposer DRAM Layer DRAM Layer DRAM Layer Re-drive Layer Non-managed DRAM (WIO, HBM, etc.) 15

16 The Package Up to 1.28 Tbps Memory Bandwidth! Standard BGA Packaging Solutions: Cost Effective Packaging using existing Ecosystems 16

17 HMC Near Memory All links between host CPU and HMC logic layer Maximum bandwidth per GB capacity HPC/Server CPU/GPU Graphics Networking systems Test equipment 17

18 HMC Far Memory Far memory Some HMC links connect to host, some to other cubes Scalable to meet system requirements Can be in module form or soldereddown Future interfaces may include Higher speed electrical (SERDES) Optical Whatever the most appropriate interface for the job! 18

19 HMC Reliability Built-In RAS features at a high level... Logic Stability (DRAM controls in logic) DRAM Array Logic / Interface Reliable handshake (packet integrity verified before memory access) DRAM Array DRAM Array Vault Data ECC protected Logic / Interface Host Logic / Interface Link Retry CRC Protection on Link Interface Logic / Interface DRAM Array Address / Command Parity for Array transactions 19

20 RAS Feature System Comparison FEATURE DRAM RDIMM HMC Extensive Test Flow Data ECC Address/Command Parity Mirroring (back-up memory) Sparing (Chipkill) Lockstep (redundancy w/better ECC) CRC Coding Self Repair BIST Error Status and Debug Registers DIMM Isolation (flags faulty DIMM) Memory Scrubbing Supported Redundant or not needed 20

21 Technology Comparison (Extreme Performance) What does it take to support 1.28TB/s of performance? Comparison of HMC to DDR3L-1600 and DDR Active Signals DDR3 requires ~14,300 DDR4 requires ~7,400 HMC only needs ~2,160, HMC is ~85% less than DDR3 $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ Operating Power (including CPU s) DDR3 system requires ~2.25KW DDR4 system requires ~1.23KW HMC system only needs ~350W, HMC is ~72% less than DDR4 Board Space DDR3 requires ~165,000 sq mm DDR4 requires ~82,500 sq mm HMC only needs ~8,712 sq mm, HMC is ~90% less than DDR4 Assumptions: 1DPC, (SR x4) RDIMMs, 6.2W/channel for 12.8GB/s, 8.4W/channel for 25.6GB/s 5W per Link for 160GB/s, 143 pins/channel for DDR3, 148 pins for DDR4, 270 per HMC, RDIMM area equals 10mm pitch x 165mm long, HMC w/keep outs equal 1089 sq mm, CPU for RDIMMS = 65W, CPU for HMC = 95W, each CPU supports up to 4 channels. 21

22 Technology Comparison (Single Link) What does it take to support 60GB/s of performance? Comparison of HMC to DDR3L-1600 and DDR DDR4 DDR4 DDR4 HMC DDR3 DDR3 DDR3 DDR4 Channels DDR3 requires 5 channels DDR4 requires 3 channels HMC only needs 1 Link Board Area DDR3 requires ~7,734 sq mm DDR4 requires ~3,843 sq mm HMC only needs ~1,089 sq mm Active Pins DDR3 requires 670 pins DDR4 requires 345 pins HMC only needs 72 pins BW/pin DDR3 ~90MB/pin DDR4 ~174MB/pin HMC ~833MB/pin Assumptions: Same as previous example of 1.28TB/s Bandwidth 22

23 Packet Buffer Memory Subsystem Comparison Switch Fabric Packet Buffer Requirements & Assumptions 4 100GbE ports per Network Processor / Traffic Manager Packet buffering on ingress or egress Maintain 800Gbps effective bandwidth across all packet sizes at each packet buffer Queue Mgmt Stats Table Lookups 100GbE 100GbE 100GbE Network Processor / Traffic Manager 100GbE Ingress or Egress Packet Buffer 2012 Micron Technology, Inc. 23

24 400Gbps Packet Buffer Comparison Network Processor Network Processor All devices drawn to scale Parameter DDR x16 4 HMC-15G-SR Links # of Memory Devices Total # of Pins Power: Host PHY+ Memory Memory Surface Area W 33W 6048mm 2 961mm 2 Host PHY Silicon 1.75x 1x Surface Area 1 1. Relative sizes represented HMC System Level Savings 85% fewer pins 41% lower power 84% smaller memory footprint 75% smaller host PHY 2012 Micron Technology, Inc. 24

25 Broad Adoption & Momentum Specification released April 2013 Over 110 Over Adopters 120 Adopters! to date! Accel, Ltd Fujitsu Limited Luxtera Inc. Pico Computing ADATA Technology Co., LTD Galaxy Computer System Co., Ltd. Marvell Renesas Electronics Corporation AIRBUS GDA Technologies Mattozetta Technologies Science & Technology Innovations Altior GLOBALFOUNDRIES Maxeler Technologies Ltd. SEAKR Engineering APIC Corporation GraphStream Incorporated MediaTek ST Microelectronics Arira Design HGST, a Western Digital Company Memoir Systems Inc. Suitcase TV Ltd Arnold&Richter Cine Technik HiSilicon Technologies Co., Ltd Mentor Graphics Tabula Atria Logic, Inc. HOY Technologies Miranda Tech-Trek BroadPak Huawei Technologies Mobiveil, Inc. Teradyne, Inc Cadence Design Systems, Inc. Infinera Corporation Montage Technology, Inc. The Regents of the University of California Convey Computer Corporation Information Sciences Institute USC Napatech A/S Tilera Corporation Cray Inc. Inphi National Instruments Tongji University DAVE Srl ISI/Nallatech NEC corpration T-Platforms Design Magnitude Inc. Israel Institute of Technology Netronome TU Kaiserslautern Dream Chip Technologies GmbH Juniper Networks New Global Technology UC, Irvine Engineering Physics Center of MSU Kool Chip Northwest Logic UMC esilicon Corporation Korea Advanced Institute of Science Obsidian Research University of Heidelberg ZITI Exablade Corporation Lawrence Livermore National Laboratory OmniPhy University of Rochester Ezchip Semiconductor LeCroy Corporation Oregon Synthesis Winbond Electronics Corporation FormFactor Inc. LogicLink Design, Inc. Perfcraft Woodward McCoach, Inc. ZTE Corporation 25

26 A Robust Ecosystem OEM s Enablers Tools 26

27 Industry Validation like adding a turbocharger to your computer - datacenteracceleration.com wicked fast - gigaom.com unprecedented levels of memory performance - Electronic News a complete paradigm shift - extremetech.com EE Times 40 th Anniversary: one of the top ten technologies expected to redefine the industry an entirely new category of memory - Tom s Hardware 27

28 HMC 3DIC The Bottom Line Improved costs at a system and TCO level When the need exists, the ecosystem develops. There are no competing technologies 28

29 HMC 3DIC The Bottom Line Improved costs at a system and TCO level When the need exists, the ecosystem develops. There are no competing technologies There are no universal solutions 29

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