Chapter 4: Processor Design. Block Diagram of 1-Bus SRC

Transcription

1 4-1 Chapter 4 Processor Design Chapter 4: Processor Design Topics 4.1 The Design Process Bus Microarchitecture for the SRC 4.3 Data Path Implementation 4.4 Logic Design for the 1-Bus SRC 4.5 The Control Unit 4.6 The 2- and 3-Bus Processor Designs 4.7 The Machine Reset 4.8 Machine Exceptions 4-2 Chapter 4 Processor Design Block Diagram of 1-Bus SRC Page 1

2 4-3 Chapter 4 Processor Design High-Level View of the 1-Bus SRC Design DD SUB ND OR SHR SHR SHL SHC NOT NEG C=B INC Chapter 4 Processor Design Constraints Imposed by the Microarchitecture One bus connecting most registers allows many different RTs, but only one at a time Memory address must be copied into M by CPU Memory data written from or read into MD First LU operand always in, result goes to C Second LU operand always comes from bus Information only goes into IR and M from bus decoder (not shown) interprets contents of IR M supplies address to memory, not to CPU bus 31 R0 R31 -bit general purpose registers LU C C B PC IR M To memory subsystem MD Page 2

3 4-5 Chapter 4 Processor Design bstract and Concrete RTN for SRC add Instruction bstract RTN: (IR M[PC]: PC PC + 4; instruction_execution); instruction_execution := ( add (:= op= 12) R[ra] R[rb] + R[rc]: Concrete RTN for the add instruction Step RTN T0 M PC: C PC + 4; T1 MD M[M]: PC C; T2 IR MD; IF T3 R[rb]; IEx. T4 C + R[rc]; T5 R[ra] C; 31 R0 R31 -bit general purpose registers LU C C B PC IR M To memory subsystem MD Parts of 2 RTs (IR M[PC]: PC PC + 4;) done in T0 Single add RT takes 3 concrete RTs (T3, T4, T5) 4-6 Chapter 4 Processor Design Concrete RTN Gives Information bout Sub-units The LU must be able to add two -bit values LU must also be able to increment B input by 4 Memory read must use address from M and return data to MD Two RTs separated by : in the concrete RTN, as in T0 and T1, are operations at the same clock Steps T0, T1, and T2 constitute instruction fetch, and will be the same for all instructions With this implementation, fetch and execute of the add instruction takes 6 clock cycles Page 3

4 4-7 Chapter 4 Processor Design Concrete RTN for rithmetic Instructions: addi bstract RTN: addi (:= op= 13) R[ra] R[rb] + c {2's complement sign extend} : Concrete RTN for addi: Step RTN T0. M PC: C PC + 4; T1. MD M[M]; PC C; T2. IR MD; Instr Fetch T3. R[rb]; Instr Execn. T4. C + c {sign ext.}; T5. R[ra] C; 31 R0 R31 -bit general purpose registers LU C C B PC IR M To memory subsystem MD Differs from add only in step T4 Establishes requirement for sign extend hardware 4-8 Chapter 4 Processor Design More Complete View of Registers and Buses in the 1-Bus SRC Design, Including Some Control Signals Concrete RTN lets us add detail to the data path Instruction register logic and new paths Condition bit flip-flop Shift count register Page 4

5 4-9 Chapter 4 Processor Design bstract and Concrete RTN for Load and Store ld (:= op= 1) R[ra] M[disp] : st (:= op= 3) M[disp] R[ra] : where disp := ((rb=0) c {sign ext.} : (rb 0) R[rb] + c {sign extend, 2's comp.} ) : The ld and St Instructions Step RTN for ld RTN for st T0 T2 Instruction fetch T3 (rb = 0 0: rb 0 R[rb]); T4 C + (16@IR 16 #IR ); T5 M C; T6 MD M[M]; MD R[ra]; T7 R[ra] MD; M[M] MD; 4-10 Chapter 4 Processor Design Notes for Load and Store RTN Steps T0 through T2 are the same as for add and addi, and for all instructions In addition, steps T3 through T5 are the same for ld and st, because they calculate disp way is needed to use 0 for R[rb] when rb = 0 15-bit sign extension is needed for IR Memory read into MD occurs at T6 of ld Write of MD into memory occurs at T7 of st Page 5

6 4-11 Chapter 4 Processor Design Concrete RTN for Conditional Branch br (:= op= 8) (cond PC R[rb]): cond := ( c =0 0: c =1 1: c =2 R[rc]=0: c =3 R[rc] 0: c =4 R[rc] 31 =0: c =5 R[rc] 31 =1 ): never always if register is zero if register is nonzero if positive or zero if negative The Branch Instruction, br Step RTN T0 T2 Instruction fetch T3 CON cond(r[rc]); T4 CON PC R[rb]; 4-12 Chapter 4 Processor Design Notes on Conditional Branch RTN c are just the low-order 3 bits of IR cond() is evaluated by a combinational logic circuit having inputs from R[rc] and c The one bit register CON is not accessible to the programmer and only holds the output of the combinational logic for the condition If the branch succeeds, the program counter is replaced by the contents of a general register Page 6

7 4-13 Chapter 4 Processor Design bstract and Concrete RTN for SRC Shift Right shr (:= op = 26) R[ra] ) # R[rb] 31..n : n := ( (c = 0) R[rc] 4..0 : Shift count in register (c ) c ): or constant field of instruction The shr Instruction Step Concrete RTN T0 T2 Instruction fetch T3 n IR 4..0 ; T4 (n = 0) (n R[rc] 4..0 ); T5 C R[rb]; T6 Shr (:= (n 0) (C #C : n n - 1; Shr) ); T7 R[ra] C; step T6 is repeated n times 4-14 Chapter 4 Processor Design Notes on SRC Shift RTN In the abstract RTN, n is defined with := In the concrete RTN, it is a physical register n not only holds the shift count but is used as a counter in step T6 Step T6 is repeated n times as shown by the recursion in the RTN The control for such repeated steps will be treated later Page 7

8 4-15 Chapter 4 Processor Design 4-16 Chapter 4 Processor Design The Register File and Its Control Signals R out gates selected register onto bus R in strobed selected register from bus From Figure R0 -bit general purpose 5 registers Select logic IR R31 B out differs from R out by gating 0 when R[0] is selected B = Base ddress IR Op ra rb rc Gra Grb Grc 3 R in R out B out to decoder 31 R R1 4 0 R D R D 5 R D 5 R0 7 Bus b<31...0> Page 8

9 4-17 Chapter 4 Processor Design 4-18 Chapter 4 Processor Design Extracting c1, c2, and OP from the Instruction Register, IR<31...0> I 21 is the sign bit of C1 that must be extended Op From Figure IR Select logic c c D IR D IR D IR To control unit I 16 is the sign bit of C2 that must be extended Sign bits are fanned out from one to several bits and gated to bus c1 out c2 out 4 1 D IR D IR IR in D Bus IR Page 9

10 4-19 Chapter 4 Processor Design 4-20 Chapter 4 Processor Design The CPU Memory Interface: Memory ddress and Memory Data Registers, M<31...0> and MD<31...0> MD is loaded from memory or from CPU bus From Figure 4.3 M To memory subsystem MD MD can drive CPU bus or memory bus MD bus MD rd Strobe MD wr MD out M in D MD MD D M M CPU bus Read Write Done data addr Memory bus Page 10

11 4-21 Chapter 4 Processor Design 4-22 Chapter 4 Processor Design The LU and Its ssociated Registers D From Figure 4.3 in LU C C B DD SUB ND... NOT C=B INC4 11 LU C B D C C out C in Page 11

12 4-23 Chapter 4 Processor Design From Concrete RTN to Control Signals: The Control Sequence The Instruction Fetch Step Concrete RTN Control Sequence T0 M PC: C PC + 4; PC out, M in, INC4, C in T1 MD M[M]: PC C; Read, C out, PC in, Wait T2 IR MD; MD out, IR in T3 Instruction_execution The register transfers are the concrete RTN The control signals that cause the register transfers make up the control sequence Wait prevents the control from advancing to step T3 until the memory asserts Done 4-24 Chapter 4 Processor Design Page 12

13 4-25 Chapter 4 Processor Design Control Steps, Control Signals, and Timing Within a given time step, the order in which control signals are written is irrelevant In step T0, C in, Inc4, M in, PC out == PC out, M in, INC4, C in The only timing distinction within a step is between gates and strobes The memory read should be started as early as possible to reduce the wait M must have the right value before being used for the read Depending on memory timing, Read could be in T Chapter 4 Processor Design Control Sequence for the SRC add Instruction add (:= op = 12) R[ra] R[rb] + R[rc]: The add Instruction Step Concrete RTN Control Sequence T0 M PC: C PC + 4; PC out, M in, INC4, C in, Read T1 MD M[M]: PC C; C out, PC in, Wait T2 IR MD; MD out, IR in T3 R[rb]; Grb, R out, in T4 C + R[rc]; Grc, R out, DD, C in T5 R[ra] C; C out, Gra, R in, End Note the use of Gra, Grb, and Grc to gate the correct 5-bit register select code to the registers End signals the control to start over at step T0 Page 13

14 4-27 Chapter 4 Processor Design Control Sequence for the SRC addi Instruction addi (:= op= 13) R[ra] R[rb] + c {2 s comp., sign ext.} : The addi Instruction Step Concrete RTN Control Sequence T0. M PC: C PC + 4; PC out, M in, Inc4, C in, Read T1. MD M[M]; PC C; C out, PC in, Wait T2. IR MD; MD out, IR in T3. R[rb]; Grb, R out, in T4. C + c {sign ext.}; c2 out, DD, C in T5. R[ra] C; C out, Gra, R in, End The c2 out signal sign extends IR and gates it to the bus 4-28 Chapter 4 Processor Design Control Sequence for the SRC st Instruction st (:= op = 3) M[disp] R[ra] : disp := ((rb=0) c {sign extend} : (rb 0) R[rb] + c {sign extend, 2 s complement} ) : The st Instruction Step Concrete RTN Control Sequence T0 T2 Instruction fetch Instruction fetch T3 (rb=0) 0: rb 0 R[rb]; Grb, B out, in T4 C + c {sign-extend}; c2 out, DD, C in T5 M C; C out, M in T6 MD R[ra]; Gra, R out, MD in, Write T7 M[M] MD; Wait, End Note B out in T3 compared to R out in T3 of addi Page 14

15 4-29 Chapter 4 Processor Design The Register File and Its Control Signals R out gates selected register onto bus R in strobed selected register from bus From Figure R0 -bit general purpose 5 registers Select logic IR R31 B out differs from R out by gating 0 when R[0] is selected B = Base ddress IR Op ra rb rc Gra Grb Grc 3 R in R out B out to decoder 31 R R1 4 0 R D R D 5 R D 5 R0 7 Bus b<31...0> Chapter 4 Processor Design Page 15

16 4-31 Chapter 4 Processor Design The Shift Counter The concrete RTN for shr relies upon a 5-bit register to hold the shift count It must load, decrement, and have an = 0 test Bus From Figure Decrement n 0 n=0 Shift count, n Decr Ld n: shift count 5-bit down counter n= n=0 4- Chapter 4 Processor Design Control Sequence for the SRC shr Instruction Looping Step Concrete RTN Control Sequence T0 T2 Instruction fetch Instruction fetch T3 n IR 4..0 ; c1 out, Ld T4 (n=0) (n R[rc] 4..0 ); n=0 (Grc, R out, Ld) T5 C R[rb]; Grb, R out, C=B, C in T6 Shr (:= (n 0) n 0 (C out, SHR, C in, (C #C : Decr, Goto6) n n-1; Shr) ); T7 R[ra] C; C out, Gra, R in, End Conditional control signals and repeating a control step are new concepts Page 16

17 4-33 Chapter 4 Processor Design The LU and Its ssociated Registers D From Figure 4.3 in LU C C B DD SUB ND... NOT C=B INC4 SHR 12 LU C D B C C out C in 4-34 Chapter 4 Processor Design Logic-Level Design for One Bit of the 1- Bus SRC LU Page 17

18 4-35 Chapter 4 Processor Design 4-36 Chapter 4 Processor Design Branching cond := ( c =0 0: c = 1 1: c = 2 R[rc] = 0: c = 3 R[rc] 0: c = 4 R[rc] 31 = 0: c = 5 R[rc] 31 = 1 ): This is equivalent to the logic expression cond = (c = 1) (c = 2) (R[rc] = 0) (c = 3) (R[rc] = 0) (c = 4) R[rc] 31 (c = 5) R[rc] 31 Page 18

19 4-37 Chapter 4 Processor Design Computation of the Conditional Value CON IR From Figure 4.3 CON in D CON Cond logic Bus Decoder =0 0 c <0 CON in D CON NOR gate does = 0 test of R[rc] on bus 4-38 Chapter 4 Processor Design Control Sequence for SRC Branch Instruction, br br (:= op = 8) (cond PC R[rb]): Step Concrete RTN Control Sequence T0 T2 Instruction fetch Instruction fetch T3 CON cond(r[rc]); Grc, R out, CON in T4 CON PC R[rb]; Grb, R out, CON PC in, End Condition logic is always connected to CON, so R[rc] only needs to be put on bus in T3 Only PC in is conditional in T4 since gating R[rb] to bus makes no difference if it is not used Page 19

20 4-39 Chapter 4 Processor Design Summary of the Design Process Starting with informal description formal RTN description block diagram architecture concrete RTN steps hardware design of blocks control sequences control unit and timing t each level, more decisions must be made These decisions refine the design lso place requirements on hardware still to be designed The nice one-way process above has circularity Decisions at later stages cause changes in earlier ones Happens less in a text than in reality because Can be fixed on re-reading Confusing to first-time student 4-40 Chapter 4 Processor Design Clocking the Data Path: Register Transfer Timing Gate signal: R out R in Source register D CK R1 Circuit propagation delay Strobe signal: Bus gate R out Gate prop. time, t g n-bit bus n Bus prop. delay, t bp t R2valid Logic block Combinational logic LU, etc. delay, t comb R in Latch hold time, t h Latch setup time, t su Minimum pulse width, t w Destination register D CK R2 Latch prop. delay, t l t R2valid is the period from begin of gate signal till inputs to R2 are valid t comb is delay through combinational logic, such as LU or cond logic Minimum clock period, t min Page 20

21 4-41 Chapter 4 Processor Design The Control Unit The control unit s job is to generate the control signals in the proper sequence Things the control signals depend on The time step Ti The instruction opcode (for steps other than T0, T1, T2) Some few data path signals like CON, n = 0, etc. Some external signals: reset, interrupt, etc. (to be covered) The components of the control unit are: a time state generator, instruction decoder, and combinational logic to generate control signals 4-42 Chapter 4 Processor Design Control Unit Detail with Inputs and Outputs Page 21

22 4-43 Chapter 4 Processor Design Synthesizing Control Signal Encoder Logic Step T3. T4. T5. add Control Sequence Grb, R, out in Grc, R,DD,C out in C, out Gra, R,End in addi Step Control Sequence T3. Grb, R, out in T4. c2,dd,c out in T5. C, out Gra, R,End in Step Control Sequence T0. PC,M,Inc4,C,Read out in in T1. C out,pc in,wait T2. MD,IR out in st Step Control Sequence T3. Grb, B, out in T4. c2, DD, C out in T5. C out,m in T6. Gra, R,MD,Write out in T7. Wait, End Design process: Comb through the entire set of control sequences. Find all occurrences of each control signal. Write an equation describing that signal. Example: Gra = T5 (add + addi) + T6 st + T7 shr +... shr Step Control Sequence T3. c1,ld out T4. n=0 (Grc, R, Ld) out T5. Grb, R out,c=b T6. n 0 (C out,shr,c in, Decr, Goto7) T7. C out, Gra, R in,end 4-44 Chapter 4 Processor Design Use of Data Path Conditions in Control Signal Logic add Step Control Sequence Step T3. Grb, R, out in T4. Grc, R,DD,C out in T5. C,Gra,R,End out in Step Control Sequence T0. PC out,m in,inc4,c in, Read T1. C out,pc in,wait T2. MD out,ir in addi Control Sequence Step T3. Grb, R, out in T4. c2,dd,c out in T5. C,Gra, R,End out in st Control Sequence Step T3. Grb, B, out in T4. c2, DD, C out in T5. C,M out in T6. Gra, R,MD,Write out in T7. Wait, End T3. c1 out,ld shr Control Sequence T4. n=0 (Grc, R,Ld) out T5. Grb, R,C=B out T6. n 0 (C,SHR,C, out in Decr, Goto7) T7. C out,gra, R in,end Example: Grc = T4 add + T4 (n=0) shr +... Page 22

23 4-45 Chapter 4 Processor Design Generation of the logic for C out and G ra T5 add T C out add addi T5 T7 ld Gra 4-46 Chapter 4 Processor Design Control Unit Detail with Inputs and Outputs Page 23

24 4-47 Chapter 4 Processor Design Branching in the Control Unit 3-state gates allow 6 to be applied to counter input Reset will synchronously reset counter to step T Chapter 4 Processor Design Control Unit Detail with Inputs and Outputs Page 24

25 4-49 Chapter 4 Processor Design The Clocking Logic: Start, Stop, and Memory Synchronization Mck is master clock oscillator 4-50 Chapter 4 Processor Design The Complete 1-Bus Design of SRC High-level architecture block diagram Concrete RTN steps Hardware design of registers and data path logic Revision of concrete RTN steps where needed Control sequences Register clocking decisions Logic equations for control signals Time step generator design Clock run, stop, and synchronization logic Page 25

26 4-51 Chapter 4 Processor Design Other rchitectural Designs Will Require a Different RTN More data paths allow more things to be done in one step Consider a two bus design By separating input and output of LU on different buses, the C register is eliminated Steps can be saved by strobing LU results directly into their destinations 4-52 Chapter 4 Processor Design The 2-Bus SRC Microarchitecture bus ( In bus ) 31 general purpose registers IR PC M MD 0 R0 R31 Memory bus Bbus ( Out bus ) Bus carries data going into registers Bus B carries data being gated out of registers LU function C = B is used for all simple register transfers B LU C Page 26

27 The 2-Bus add Instruction 4-53 Chapter 4 Processor Design Step Concrete RTN Control Sequence T0 M PC; PC out, C = B, M in, Read T1 PC PC + 4: MD M[M];PC out, INC4, PC in, Wait T2 IR MD; MD out, C = B, IR in T3 R[rb]; Grb, R out, C = B, in T4 R[ra] + R[rc]; Grc, R out, DD, Sra, R in, End Note the appearance of Grc to gate the output of the register rc onto the B bus and Sra to select ra to receive data strobed from the bus Two register select decoders will be needed bus ( In bus ) 31 general purpose registers IR PC M MD 0 R0 R31 Memory bus Bbus ( Out bus ) B LU 1997 V. Heuring C and H. Jordan 4-54 Chapter 4 Processor Design Performance and Design %Speedup = Where T1 bus T 2 bus T 2 bus 100 T = Exec' n.time = IC CPI τ Page 27

28 4-55 Chapter 4 Processor Design Speedup By Going to 2 Buses ssume for now that IC and τ don t change in going from 1 bus to 2 buses Naively assume that CPI goes from 8 to 7 clocks. % Speedup = T T T 1 bus 2 bus 2 bus 100 IC = 8 τ IC 7 IC τ 7 τ 100 = = 14% Class Problem: How will this speedup change if clock period of 2-bus machine is increased by 10%? 4-56 Chapter 4 Processor Design 3-Bus rchitecture Shortens Sequences Even More 3-bus architecture allows both operand inputs and the output of the LU to be connected to buses Both the C output register and the input register are eliminated Careful connection of register inputs and outputs can allow multiple RTs in a step Page 28

29 4-57 Chapter 4 Processor Design The 3-Bus SRC Design Cbus bus Bbus 31 0 R0 general purpose registers IR PC M MD R31 Memory bus -bus is LU operand 1, B-bus is LU operand 2, and C-bus is LU output Note M input connected to the B-bus LU B C The 3-Bus add Instruction 4-58 Chapter 4 Processor Design Step Concrete RTN Control Sequence T0 M PC: MD M[M]; PC out, M in, INC4, PC in, PC PC + 4: Read, Wait T1 IR MD; MD out, C = B, IR in T2 R[ra] R[rb] + R[rc]; Grc, R out, GBrb, RB out, DD, Sra, R in, End Note the use of 3 register selection signals in step T2: Grc, GBrb, and Sra In step T0, PC moves to M over bus B and goes through the LU INC4 operation to reach PC again by way of bus C PC must be edge-triggered or master-slave Cbus Memory bus bus B bus 31 0 R0 general purpose registers IR PC M MD R31 B LU C Page 29

30 4-59 Chapter 4 Processor Design Performance and Design How does going to three buses affect performance? ssume average CPI goes from 8 to 4, while τ increases by 10%: IC 8 τ IC 4 1.1τ % Speedup = 100 = 100 = IC 4 1.1τ % 4-60 Chapter 4 Processor Design Processor Reset Function Reset sets program counter to a fixed value May be a hardwired value, or contents of a memory cell whose address is hardwired The control step counter is reset Pending exceptions are prevented, so initialization code is not interrupted It may set condition codes (if any) to known state It may clear some processor state registers soft reset makes minimal changes: PC, T (trace) hard reset initializes more processor state Page 30

31 4-61 Chapter 4 Processor Design SRC Reset Capability We specify both a hard and soft reset for SRC The Strt signal will do a hard reset It is effective only when machine is stopped It resets the PC to zero It resets all general registers to zero The Soft Reset signal is effective when the machine is running It sets PC to zero It restarts instruction fetch It clears the Reset signal ctions are described in instruction_interpretation 4-62 Chapter 4 Processor Design bstract RTN for SRC Reset and Start Processor State Strt: Rst: Start signal External reset signal instruction_interpretation := ( Run Strt (Run 1: PC, R[0..31] 0); Run Rst (IR M[PC]: PC PC + 4; instruction_execution): Run Rst ( Rst 0: PC 0); instruction_interpretation): Page 31

32 4-63 Chapter 4 Processor Design Resetting in the Middle of Instruction Execution The abstract RTN implies that reset takes effect after the current instruction is done To describe reset during an instruction, we must go from abstract to concrete RTN uestions for discussion: Why might we want to reset in the middle of an instruction? How would we reset in the middle of an instruction? 4-64 Chapter 4 Processor Design The add Instruction with Reset Processing Step Concrete RTN T0 Rst (M PC: C PC + 4): Rst (Rst 0: PC 0: T 0): T1 Rst (MD M[M]: P C): Rst (Rst 0: PC 0: T 0): T2 Rst (IR MD): Rst (Rst 0: PC 0: T 0): T3 Rst ( R[rb]): Rst (Rst 0: PC 0: T 0): T4 Rst (C + R[rc]): Rst (Rst 0: PC 0: T 0): T5 Rst (R[ra ] C): Rst (Rst 0: PC 0: T 0): See text for the corresponding control signals Page

33 4-65 Chapter 4 Processor Design Control Sequences Including the Reset Function Step T0 T1 Control Sequence Reset (PC out, M in, Inc4, C in, Read): Reset (ClrPC, ClrR, Goto0): Reset (C out, PC in, Wait): Reset (ClrPC, ClrR, Goto0): ClrPC clears the program counter to all zeros, and ClrR clears the 1-bit Reset flip-flop Because the same reset actions are in every step of every instruction, their control signals are independent of time step or opcode 4-66 Chapter 4 Processor Design General Comments on Exceptions n exception is an event that causes a change in the program specified flow of control Often called interrupts We will use exception for the general term and use interrupt for an exception caused by an external event, such as an I/O device condition The usage is not standard. Other books use these words with other distinctions, or none Page 33

34 4-67 Chapter 4 Processor Design Combined Hardware/Software Response to an Exception The system must control the type of exceptions it will process at any given time The state of the running program is saved when an allowed exception occurs Control is transferred to the correct software routine, or handler, for this exception This exception, and others of less or equal importance, are disallowed during the handler The state of the interrupted program is restored at the end of execution of the handler 4-68 Chapter 4 Processor Design Hardware Required to Support Exceptions To determine relative importance, a priority number is associated with every exception Hardware must save and change the PC, since without it no program execution is possible Hardware must disable the current exception lest is interrupt the handler before it can start ddress of the handler is called the exception vector and is a hardware function of the exception type Exceptions must access a save area for PC and other hardware saved items Choices are special registers or a hardware stack Page 34

35 4-69 Chapter 4 Processor Design New Instructions Needed to Support Exceptions n instruction executed at the end of the handler must reverse the state changes done by hardware when the exception occurred There must be instructions to control what exceptions are allowed The simplest of these enable or disable all exceptions If processor state is stored in special registers on an exception, instructions are needed to save and restore these registers 4-70 Chapter 4 Processor Design n Interrupt Facility for SRC The exception mechanism for SRC handles external interrupts There are no priorities, but only a simple enable and disable mechanism The PC and information about the source of the interrupt are stored in special registers ny other state saving is done by software The interrupt source supplies 8 bits that are used to generate the interrupt vector It also supplies a 16-bit code carrying information about the cause of the interrupt Page 35

36 4-71 Chapter 4 Processor Design SRC Processor State ssociated with Interrupts Processor interrupt mechanism From Device ireq: Interrupt request signal To Device iack: Interrupt acknowledge signal Internal IE: 1-bit interrupt enable flag to CPU IPC : Storage for PC saved upon interrupt to CPU II : Information on source of last interrupt From Device Isrc_info : Information from interrupt source From Device Isrc_vect 7..0 : Type code from interrupt source Internal Ivect := 20@0#Isrc_vect 7..0 #4@0: Ivect Isrc_vect Chapter 4 Processor Design SRC Instruction Interpretation Modified for Interrupts instruction_interpretation := ( Run Strt Run 1: Run (ireq IE) (IR M[PC]: PC PC + 4; instruction_execution): Run (ireq IE) (IPC PC : II Isrc_info : iack 1: IE 0: PC Ivect ; iack 0); instruction_interpretation); If interrupts are enabled, PC and interrupt information are stored in IPC and II, respectively With multiple requests, external priority circuit (discussed in later chapter) determines which vector and information are returned Interrupts are disabled The acknowledge signal is pulsed Page 36

37 4-73 Chapter 4 Processor Design SRC Instructions to Support Interrupts Return from interrupt instruction rfi (:= op = 29 ) (PC IPC: IE 1): Save and restore interrupt state svi (:= op = 16) (R[ra] II : R[rb] IPC ): ri (:= op = 17) (II R[ra] : IPC R[rb]): Enable and disable interrupt system een (:= op = 10 ) (IE 1): edi (:= op = 11 ) (IE 0): The 2 rfi actions are indivisible, can t een and branch 4-74 Chapter 4 Processor Design Concrete RTN for SRC Instruction Fetch with Interrupts Step (ireq IE) Concrete RTN (ireq IE) T0 ( (ireq IE) ( (ireq IE) (IPC PC: II Isrc_info: M PC: C PC+4): IE 0: PC 20@0#Isrc_vect 7..0 #0000: Iack 1; Iack 0: End); T1 MD M[M] : PC C; T2 IR MD; PC could be transferred to IPC over the bus II and IPC probably have separate inputs for the externally supplied values iack is pulsed, described as 1; 0, which is easier as a control signal than in RTN Page 37

38 4-75 Chapter 4 Processor Design Recap of the Design Process: the Main Topic of Chapter 4 Informal description Formal RTN description Block diagram architecture Concrete RTN steps Hardware design of blocks Control sequences Control unit and timing SRC Chapter 2 Chapter Chapter 4 Processor Design Chapter 4 Summary Chapter 4 has done a nonpipelined data path and a hardwired controller design for SRC The concepts of data path block diagrams, concrete RTN, control sequences, control logic equations, step counter control, and clocking have been introduced The effect of different data path architectures on the concrete RTN was briefly explored We have begun to make simple, quantitative estimates of the impact of hardware design on performance Hard and soft resets were designed simple exception mechanism was supplied for SRC Page 38