Computer Organization
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1 Chapter 4 Computer Organization Von Neuman Concept Stored program concept General purpose computational device driven by internally stored program Data and instructions look same i.e. binary Operation being executed determined by HOW we look at the sequence of bits Fetch Decode View bits as instruction Execute Data might be fetched as a result of execution CS Arthur 2 1
2 Von Neuman Architecture CPU ALU Control Unit I/O Buses Memory Unit Devices CS Arthur 3 Von Neuman Machine Architecture CPU = ALU + Cntrl Unit ALU + Instruction set + Arithmetic & Logic - Functional Unit - Registers + Intermediate storage Cntrl Unit - fetch - decode - execute ALU Buses Address Bus / Data Bus wires over which Instr / data is transferred from memory to ALU Von Nuemann Bottleneck CS Arthur 4 2
3 CPU: ALU Component Assumes instruction format: OP code, LHO, RHO Instruction / data fetched & placed in register Instruction / data retrieved by functional unit & executed Results placed back in registers Control Unit sequences the operations CS Arthur 5 CPU: Control Unit Component PC => Program Counter IR => Instruction Register Von Nuemann Execution Cycle Fetch Unit Get instruction at location pointed to by PC and place in IR Decode Unit Determine which instruction & signal hardware that implements it Execute Unit Hardware for instruction execution (could cause more data fetches) CS Arthur 6 3
4 Fetch Execute cycle Decode(IR) Fetch CS Arthur 7 OS boot-up How does the system boot up? Bootstrap loader OS Application CS Arthur 8 4
5 A Bootstrap Loader The power-up sequence load PC, FIXED_LOC Address of BS Loader Where FIXED_LOC addresses the bootstrap loader (in ROM). The bootstrap loader has the form: load R1, =0 load R2, = LENGTH_OF_TARGET loop: read R1, FIXED_DISK_ADDRESS store R1, [FIXED_DEST, R1] incr R1 bleq R1, R2, loop br FIXED_DEST Reads OS in Branches to OS Fetch Decode Execute CS Arthur 9 Memory Unit Memory Unit CS Arthur 10 5
6 Memory Unit Memory Unit contains Memory Instructions & Data MAR (Memory Address Register) MDR (Memory Data register) CMD (Command Register) Get instruction at location pointed to by PC and place in IR CS Arthur 11 Memory Access Read from Memory MAR MemAddr CMD Read OP (from IR) Execute MDR Mem[ MAR ] Write to Memory MAR MemAddr CMD Write OP (from IR) Execute Mem[ MAR ] MDR CS Arthur 12 6
7 Device & Device Controller Device & Device Controller In OS Device Driver Device Controller Device Interfaces CS Arthur 13 Device Controller-Software Relationship Bus Device driver PCI SCSI Standard Interface CS Arthur 14 7
8 Device Controller Interface Driver interrogated these to check status of device Driver places command if status Done Interface to driver CS Arthur 15 Device Controller Device controller is a processor and allows 2 parts of the process to proceed concurrently Program Controller write Prints info CS Arthur 16 8
9 Device Driver Interface OS could provide higher level operations to application than the one Driver presents to it Interface presented by Driver to Application program thru OS Controller/Driver Interface Controller/Device Interface Terminal Printer Disk CS Arthur 17 How do interrupts factor in? Scenario (1) Program: while device_flag busy {} => Busy wait - consumes CPU cycles Scenario (2) Program: while (Flag!= write) { sleep( X ) } =>If write available while program sleeping - inefficient CS Arthur 18 9
10 How do interrupts factor in? Scenario (3) Program: issues write Driver: Suspend program until write is completed, then program is unsuspended This is Interrupt-driven CS Arthur 19 Interrupts Driven Service Request Process is suspended only if driver/controller/device cannot service request If a process is suspended, then, when the suspended process service request can be honored Device interrupts CPU OS takes over OS examines interrupts OS un-suspends the process Interrupts Eliminate busy wait Minimizes idle time CS Arthur 20 10
11 Interrupts Interrupt Handler in OS: disables interrupts : : Interrupt processed : : enables interrupts What if multiple devices (or 2 nd device) sends interrupt while the OS is handling prior interrupt? If priority of 2nd interrupt higher than 1st then 1st interrupt suspended 2 nd interrupt handled Resumption of handling 1st interrupt CS Arthur 21 11
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