High Speed DRAM Interface

Transcription

1 High Speed DRAM Interface Changsik Yoo DRAM Design 3 Samsung Electronics

2 Memory Channel

3 DRAM Interface Trend DRAM Freq. & Perf. System HW & OS 25MHz ( 200MB/S) 386/486 Win MHz (400MB/S) Pentium Win MHz (800MB/S) PII Win MHz (1.6GB/S) PIII/P7 Win 2K 1.6GHz? (3.2GB/S?) P7/P8 Win? DRAM type * Graphics VRAM VRAM 3D RAM WRAM DDR SG/SD SG/SDRAM RDRAM Main stream FP EDO PC66/100 PC133 NG (?) * Specialty Toggle mode BEDO DDR SDRAM CDRAM VCRAM FCRAM SLDRAM Mosys.DRAM

4 SSTL Bus for DDR SDRAM Vterm Rterm DRAM DRAM DRAM C/A Buffer CLK DRAM DRAM DRAM C/A Buffer Rstub Z0=50Ω CLK CLK DQS DQ DQ & DQS Memory Controller Command & Address CLK Clock Driver

5 Clocking of DDR SDRAM Source synchronous clocking using bi-directional data strobe (DQS) Write DQ ; center aligned to DQS Read DQ ; edge aligned to DQS System clock is not used for data transmission. System clock is to sample the command/address signals and define the time domain. Signal quality of data strobe is inferior to a free-running clock. Then, why don t we use a free-running clock instead of data strobe? DRAM RCLK DQ td In DRAM and chipset, data sampled by DQS should be transferred to the system clock domain for internal operation.

6 Data Strobe of DDR SDRAM Vtt Rtt Data Strobe (DQS) Data (DQ) Controller x1 DS Vref? x8 DQ Dout buffer DIN buffer

7 Basic Timing of DDR SDRAM CK,/CK 7.5 ns Read tdqsck = 0.1 * tck DQS-out DQ-out Write tac= 0.1 * tck tdqsck = 0.1 * tck tac = 0.1 * tck * tdqsq = 0.5ns (Skew between DQS & DQs) 7.5 DQS-in tdqss = 0.75~1.25tCK tds 0.5ns 3 3 tdh 0.5ns DQ-in

8 RAMBUS Channel Vterm DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM Clock Driver CFM CTM CTM = Clock To Master CFM = Clock From Master RQ = Command/Address Packet CTM Read DQ DQ RQ Z0=28Ω CFM Write DQ Memory Controller

9 Clocking of RAMBUS DRAM Source synchronous clocking using free-running clocks Write DQ ; center aligned to CFM Read DQ ; center aligned to CTM Depending on the physical location of DRAM, the phase difference between CTM and CFM changes. The phase difference is denoted as ttr. In DRAM and chipset, some special circuitry is included to handle ttr.

10 Future Memory Channel ;? Point-to-point bus can give much higher data rate than a multi-drop bus. How to terminate the bus? Graphic DDR SDRAM is now targeting ~1Gbps data rate. Then, why don t we use point-to-point DRAM channel? Limited memory capacity Serial chain style bus Media RAM by MicroUnity (US Patent )

11 Future Memory Channel ;?? Simultaneous bi-directional bus In multi-drop bus, it is difficult to extract the input data stream from a data stream on the channel. Imagine when you want to write to module 1 while you read from module 2. DRAMs on the module 1 do not have any information on the data pattern read from module 2. So, this technique can be used only for point-to-point bus.

12 Future Memory Channel ; DDR-II In JEDEC, DDR-II targeting 667Mb/s/pin is being defined as an extension of DDR. Interface is defined at VDDQ=1.8V. SSTL bus structure has been modified for higher data rate. ODT (On Die Termination) is employed for better signal integrity. ODT gives smaller ISI and better voltage margin. For detailed information on DDR-II, see JEDEC web-site.

13 Future Memory Channel ; Yellow Stone For consumer and communications applications

14 Future Memory Channel ; 4 PAM Signaling Timing burden relaxed but voltage margin reduced For high data rate multi-drop bus, attenuation is a serious problem and thus voltage margin is a big issue. Current integrating input receiver is used to filter out the noise. J. Zerbe, et al., 1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus JSSC, May, 2001

15 Wider RAMBUS Channel ; 32 Bit Channel Number of module connector pins = Money 16 bit channel currently in use 32 bit channel

16 Interface Circuits

17 Timing and Voltage Specifications

18 Timing Budget Calculation - An Example For RAMBUS read case at 800Mbps operation tq and tsh are from data books while the other numbers are arbitrarily chosen. Half bit time tq of chipset tsh of RDRAM tce ; Channel effect tj ; Clock jitter Margin 625ps 250ps 200ps 100ps 50ps 25ps

19 Delay Locked Loop Write DLL Read DLL Quadrature clock Duty correction DDR SDRAM No Yes No No RAMBUS DRAM Yes Yes Yes Yes Locking time < 200 cycles ~ ms

20 DLL for DDR SDRAM ISSCC 01 CLK (SSTL) MUX MUX Interpolater Direct PD & Control logic Compensation delay Data path All digital control including DCC

21 Digital Duty Cycle Correction ISSCC 01 extclk intclk intclkb_fb th tcc-2*th tcc-th intclkb tcc/2-th tcc/2 For power saving, it is desirable to turn off DLL during standby (pre-charge) state in DDR SDRAM. For fast standby exit, all the locking information including DCC is stored as digital codes. If DCC is done by analog integrator as in RAMBUS DRAM, standby exit time would be limited by DCC re-locking.

22 DLL for RAMBUS DRAM ; R-Loop

23 DLL for RAMBUS DRAM ; T-Loop

24 Input Receiver ; DDR SDRAM Single-ended DQ input Different low and high transition delay DQ is sampled by DQS after being buffered to CMOS level. Delay matching between DQ and DQS is critical. Delay mismatch directly affects tsh.

25 Data Input Sampling ; DDR SDRAM DIN Vref + - Buffer DIND DINED DINEDD D Q D Q PE Latch & Write Driver (even) DQS Vref + - PULSE GEN. PO D Q DINOD Latch & Write Driver (odd) CLK Vref + - DELAYED PULSE PCK DIND : Input data after Din buffer PE : Pulse generated by the rising edge of DQS PO : Pulse generated by the falling edge of DQS PCK : Internal Pulse generated by the rising edge of CLK

26 Output Driver ; DDR SDRAM Voltage mode push-pull driver ; small ron Key issues Through current from VddQ to VssQ Tri-state control ; timing control not easy Simultaneous switching noise ; tq degradation x1 DS x8 DQ

27 Simultaneous Switching Noise DQ[0:7] VDDQ VDD/VSS VDDQ/VSSQ VDD VDD DOP VDDQ DQ[8:15] VSSQ VDDQ VSS VSS DQ DQ[0:14] VDD VDD DON to off-chip DQ[15] VSSQ VSS VSS VSSQ DQ[15] VDDQ DQ[0:14] VSSQ

28 Simultaneous Switching Noise Reduction DQ[0:7] VDDQ VDD/VSS VDD VDDQ/VSSQ VDDQ DOP VDDQ DQ[8:15] DON[0:14] VSSQ VDDQ VSS VSSQ DQ DQ[0:14] VDD VDDQ to off-chip DQ[15] DON VSSQ VSS VSSQ VSSQ DQ[15] VDDQ DQ[0:14] DOP[0:14] VSSQ ISSCC 01

29 Slew Rate Control Method Slew rate control should be independent of driver strength control. Predriver Driver DQ Cload Predriver Driver DQ Cload

30 Input Receiver ; RAMBUS DRAM Clk Out IN Ref Outb Bias Clk Pre-amplifier Role? Gain? Sense-amplifier RS-latch B. Lau, et al., A 2.6-GByte/s Multipurpose Chip-to-Chip Interface JSSC, NOV. 1998

31 Input Related AC Specifications Spec. What is this? Determining factors tsh Input setup and hold time Input receiver uncertainty window DLL clock jitter Clock centering error Clock duty cycle error ViH / ViL Input voltage margin ttr (RQ and DQ coupling effect) Input receiver kick-back noise Pre-amplifier design

32 Read Data Output Circuitry ; RAMBUS V term pad & package trace line R term clk pin_en nmos array data_e data_o Data slew control clkb initial status 7 enable Level detection P.V. detection FSM & counter (level control) For good design, parasitics such as metal line resistance/capacitance and package inductance/capacitance should be modeled as accurate as possible. Revision is money!!!

33 Output Swing Level Detection ; RAMBUS V term V OH ini The effect of these resistors should be compensated. V term 0 V OL ini V M V ref FSM & Counter Ctrl[5:0] B. Lau, et al., A 2.6-GByte/s Multipurpose Chip-to-Chip Interface JSSC, NOV. 1998

34 Why Current Mode Driver in RAMBUS? If it is voltage mode driver, the reflected wave from chipset is reflected once again at the driver and these reflections will persist for long, deteriorating the signal integrity. The RAMBUS output driver is specified to give larger than 150-Ohm output resistance.

35 Summary Data rate of DRAM channel is continuously increasing. 800Mbps is in mass production. 1066Mbps looks feasible with minor changes. 1200Mbps, 1600Mbps.. will be seen in near future. In DRAM channel, peak data rate does not tell everything. It is only one of many factors determining the memory system performance. In order to devise a high-performance DRAM channel, good understanding of memory system is required.