Modern Memory Interfaces (DDR3) Design with ANSYS Virtual Prototype approach
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1 Modern Memory Interfaces (DDR3) Design with ANSYS Virtual Prototype approach 1 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
2 Agenda DDR Design Challenges How does simulation solve these design challenges? Circuit + EM Extraction! (Virtual Prototype) Virtual Prototype Accuracy Speed Capacity Repeatability & Automation Summary 2 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
3 DDR X Technology DDR3 Design Challenges for Signal Inetgrity Reduced Voltage Noise Margin Standard DDR SDRAMs DDR2 SDRAM DDR3 SDRAM DDR4 SDRAM Output buffer for DDR interface ~ V Without off-chip interconnect. C fixture (<2~3pF) Mobile DDR SDRAMs LPDDR LPDDR2 LPDDR3 1.2V POD(Peudo-open 1.8V 1.2V 1.8V 1.5V LVCMOS HSUL SSTL drain) For For For AC300 AC150 AC250 AC mV +300mV +250mV +175mV -150mV -300mV -250mV -175mV V IH.ac =1.44V(VDDx0.8) IH.ac =0.9V V IH.ac =0.75V IH.ac =1.15V V IH.ac =0.925V IH.ac =TBD V ref =0.9V =0.75V ref =0.6V V V IL.ac =0.575V IL.ac =0.45V IL.ac =TBD V V IL.ac =0.65V IL.ac =0.3V V IL.ac =0.36V(VDDx0.2) 0.36V Less 0.45V 0.3V 0.575V than 0.65V 0.52V Single-ened Single-ened without shunt(odt) termination V IH.dc =1.26V(VDDx0.7) IH.dc =1.025V IH.dc =0.85V V IH.dc =0.8V(VDDx0.7) =0.7V(VDDx0.7) IH.dc =TBD V IH.dc =0.5V(VDDx0.3) V IH.dc V =0.4V(VDDx0.3) IH.dc =TBD IH.dc =0.65V V IH.dc =0.54V(VDDx0.3) V IH.dc =0.775V 0V Logic Logic Voltage Level & AC&DC Logic Thresholds 3 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
4 DDR X Technology DDR3 Design Challenges for Signal Inetgrity Reduced Timing Margin Bit Bit Width(Unit Interval) = = 0.625ns 0.938ns 0.469ns 2.5ns 0.234ns Data Strobe LPDDR LPDDR2 DDR2 LPDDR3 DDR3 DDR4 4 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
5 Design challenges? Validation DDR X Technology & Challenges Prototype Measurement Interpret and implementation(calculation) of Design Spec such as DDR3, LPDDR2 and more Large amount output data report of results Capacity or Complexity and Time Chip to Chip or Chip to PKG Chip + Package + PCB + Connector/Cable + PCB + Package + Chip Full System 5 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14, pages of JEDEC DDR3 specs
6 ANSYS Solution Electrical Mechanical Fluid Dynamic 6 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14, Images and models courtesy of the Xilinx, Micron Technology, TE Connectivity.
7 Virtual System Prototyping Layout ECAD HFSS, PSI, SIwave Virtual Prototype Electromagnetic Extraction 3D CAD MCAD Electrical Vendor Specific Driver/Receiver Models Vendor Specific VRM Models Electronics Virtual System Virtual Compliance DesignerSI, UDS, UDD 7 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
8 Simulation Technology Solutions & Benefits HFSS PSI SIwave Accuracy 3D FEM Prism 2D FEM/MOM Speed Capacity ANSYS Designer SI Automation 8 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
9 Design Review (1/2) Main Board Side No termination resistors for all signals Point-to-Point Interconnect topology between FPGA and SODIMM Controlled skews by serpentine traces Layer Stackup; 16 layers, 2mm Thickness, 8 power planes, Substrate : FR4 Board size : 139.7mm x 266.7mm 9 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
10 Design Review (2/2) SODIMM Side Data Group Signals : Point-to-Point Topology with series termination resistor Clock/Address/Command Signals : Fly-by-Topology Ex) CAS signal with pull-up end termination Vtt termination rail 10 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
11 Simulation Technology 1/3 Hybrid Solution Main PCB, SODIMM PCB, SODIMM Connector SIwave Connector(S-Parameter from Vender or Simulation) SIwave 11 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
12 Simulation Technology 2/3 Full 3D FEM and Prism Main PCB, DIMM PCB, 204pin Connector(Full 3D EM Model) n-node Component from HFSS Spice Model HFSS Connector + PCB Sentinel PSI 12 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
13 Simulation Technology 3/3 HFSS Solver on Demand, HFSS in Designer can handle full 3D interconnect PCB, PKG and Package on PCB Model Clip Solve in Designer using HFSS 13 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
14 Simulation Technology Critical Net in HFSS Add full 3D HFSS interconnect Model include ALL(PKG, Connector, PCB) 14 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
15 Post Layout Simulation (1066Mbps) Differential Clock Signal +350mV -350mV Memory Controller 15 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14, 2012 Odd mode propagation 1-15 sodimm Connector ANSYS DesignerSI TM
16 Post Layout Simulation (1066Mbps) Data group signals Point-to-Point Topology Point-to-Point Topology Point-to-Point Topology With Series R(20Ohm) 16 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
17 Post Layout Simulation (1066Mbps) Data group signals Write Operation / ODT(on-die-termination) Disabled ANSYS DesignerSI TM DATA0 Differential + DATA1 Strobe0 + DATA2 + + DATA7 17 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
18 Post Layout Simulation (1066Mbps) Data group signals Write Operation / ODT(on-die-termination) Disabled Setup Margin Calculation (before derating) ANSYS DesignerSI TM DATA0 + DATA1 + DATA2 + + DATA7 DATA0 + DATA1 + DATA2 + + DATA7 AC150 Vref+150mV V IH.AC =0.9V Vref=0.75V AC150 Vref-150mV V IL.AC =0.6V Valid Before Time Tvb=152psec 77 psec Setup Margin 18 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14, psec setup time from receiver(jedec) specification The earliest strobe signal at Vref.diff 1-18
19 Post Layout Simulation (1066Mbps) Data group signals Write Operation / ODT(on-die-termination) Disabled Setup Margin Caculation (with derating value) ANSYS DesignerSI TM 3.53V/ns 6.15V/ns 3.53V/ns 6.15V/ns Slew Rate Comparison Between Differential DQS and Data Signals 19 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14, ) setup time(without derating) 1-19
20 UDS UDS (User Defined Solutions) 20 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
21 UDS (User Defined Solutions) allows calculations and postprocessing of simulated or raw transient simulation data Supported thru IronPython scripting Designer.sdf solutions file H-Spice.tr0 solutions file Useful in Virtual Compliance calculations for different standards Key benefits: Why ANSYS UDS? AC Data Timing Calculations (tds, tdh, derate ) Non-Ideal voltage supply is supported Every bit-by-bit falling and rising transition edge is calculated Fully customizable through Python scripts. Templates currently exists for LPDDR, DDR2 and DDR3 standards 21 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
22 Post Layout Simulation (1066Mbps) Data group signals Write Operation / ODT(on-die-termination) Disabled ANSYS UDS(User Defined Solution) for DDR application For the waveforms(tr0, sdf) from HSPICE or Nexxim Valid Before Time (Tvb) Setup Margin without derating value = Tvb( ps) setup time (75ps) Derating Value is automatically calculated!!! (After comparing tangential slew rates through UDS.) 22 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
23 Post Layout Simulation (1066Mbps) Data group signals Write Operation / ODT(on-die-termination) Disabled Hold Margin Calculation (before derating) ANSYS DesignerSI TM DATA0 + DATA1 + DATA2 + + DATA7 DC100 Vref+100mV V IH.DC =0.85V DC100 Vref-100mV V IL.DC =0.65V Valid After Time Tva=160psec 100psec Hold time from receiver(jedec) specification The latest strobe signal at Vref.diff 23 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14, psec Hold Margin
24 Post Layout Simulation (1066Mbps) Data group signals Write Operation / ODT(on-die-termination) Disabled Hold Margin Calculation (with derating value) ANSYS DesignerSI TM Valid After time(tva)=160psec Hold Margin(without derating value) = Tva(160psec) hold time(100psec) = 60psec Hold Time for DC100 & 1066Mbps 24 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
25 Post Layout Simulation (1066Mbps) Data group signals Write Operation / with ODT 120/60/40 Ohm ANSYS DesignerSI TM ODT_120 ODT_disabled at DDR3 at DDR3 SDRAM SDRAM ODT_60Ohm ODT_120 at DDR3 at DDR3 SDRAM ODT 40Ohm SDRAM ODT_60Ohm at DDR3 at SDRAM DDR3 SDRAM VDD(Q) VDD(Q) 240Ohm 120Ohm 80Ohm 240Ohm 120Ohm 80Ohm Negative Setup Margin! For all data signals, setup margin with derating value is positive. All positive hold margin! Hold margin with derating value is also positive. 25 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
26 UDD (User Defined Document) 26 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
27 UDD Slides UDD include Design Summery, Simulation Setup Per-Lain, Per-DQ and Per-Edge Calculation HTML Report support Hyperlink and automatic Post Processing. 27 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
28 Summary Modern Memory Interfaces (DDR3) Design with ANSYS Virtual Prototype approach Power of EM & Circuit Simulation The combination of ANSYS Solution are very helpful to get insight for your SI problem in all direction Easy Validation UDS, UDD Virtual Compliance Test H/W engineers can prevent from logical malfunction through SI simulation and optimized the system performance through what-if simulation. 28 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
29 Thank You 29 ANSYS, Inc. Proprietary 2012 ANSYS, Inc. November 14,
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