Energy Consumption Evaluation of an Adaptive Extensible Processor

Transcription

1 Energy Consumption Evaluation of an Adaptive Extensible Processor Hamid Noori, Farhad Mehdipour, Maziar Goudarzi, Seiichiro Yamaguchi, Koji Inoue, and Kazuaki Murakami December 2007

2 Outline Introduction General Overview of the Proposed Approach Multi-Exits Custom Instructions Energy Consumption Evaluation Evaluation Results Conclusions and Future Work 2

3 Outline Introduction General Overview of the Proposed Approach Multi-Exits Custom Instructions Energy Consumption Evaluation Evaluation Results Conclusions and Future Work 3

4 Introduction (1/2) Embedded processors have to achieve Low cost High-performance Low-power or low-energy consumption Key point How can processors adapt to target applications? Solution: ASIP w/ Re-configurability Application specific ISA Provide custom instructions (CIs) Implement re-configurable FUs 4

5 Introduction (2/2) Adaptive, extensible processor [DATE 07] Has a coarse-grain re-configurable functional unit Supports efficient Multi-Exits CIs Achieves high-performance and low-cost Question How about energy efficiency? Results: Energy saving v.s. base processor: 42% v.s. single basic-block based CIs: 15% 5

6 Outline Introduction General Overview of the Proposed Approach Multi-Exits Custom Instructions Energy Consumption Evaluation Evaluation Results Conclusions and Future Work 6

7 ADaptive EXtensible processor (ADEXOR) Generating and adding CIs AFTER chip fab. Utilization phase Instruction Dispatcher + & x LD/ST CFU1 CRFU Config Mem Register File 7

8 Execution Overview of ADEXOR subiu $25,$25, lbu $13,0($7) lbu $2,0($4) sll $2,$2,0x a0 sra $14,$2,0x a8 addiu $4,$4,1 4006b0 srl $8,$2,0x1c 4006b8 sll $2,$8,0x2 4006c0 addu $2,$2,$ c8 bgez $10,4006f0 4006d0 xori $13,$13,1 4006d8 addu $10,$10,$ subiu $25,$25, sll $2,$2,0x a0 sra $14,$2,0x lbu $13,0($7) 4006e0 bgez $10,4006f0.... GPP Register File ID/EXE Reg ALU EXE/MEM Reg ID/EXE Reg MUX CRFU Augmented HW Counter RFU Configuration Memory Triggered by mtc1 or sequencer GPP: General Purpose Processor Indexed by mtc1 or sequencer Hot Basic Block RFU: Reconfigurable Functional Unit 8

9 Integrating the CRFU and the Base Processor Triggered by mtc1 Reg0.... Reg31 or sequencer From decode stage Counter DEC/EXE Pipeline Registers CRFU Input Regs En ALU1 ALU2 ALU3 ALU4 CRFU Config Memory Counter EXE/MEM Pipeline Registers Triggered by mtc1 or sequencer Result bus 9

10 Microarchitecture of the CRFU Connections from input ports to inputs of the rows CRFU Input Ports Row1 Configuration bits FU FU FU FU Configuration bits Outputs of 1 st row to the inputs of 3 rd, 4 th and 5 th rows CRFU Output Ports Row5 Outputs of 2 nd row to the inputs of 4 th and 5 th rows Configuration bits 10

11 Outline Introduction General Overview of the Proposed Approach Multi-Exits Custom Instructions Evaluation Results Conclusions and Future Work 11

12 Why Multi-Exits Custom Instructions (MECIs)? adpcm Conventional BB-base CI Generation (Single-Enter Single-Exit) BB1 #Required nodes: 4 BB2 BB3 BB bgez 5 beq bne 95% 5% 30. bne BB6 BB5 Assume 20 nodes can be included in one CI in maximum 12

13 adpcm Why Multi-Exits Custom Instructions (MECIs)? BB-base CI w/ Conditional Execution Support (Single-Enter Single-Exit) #Required nodes: 22 (can not map) BB1 BB2 BB3 BB bgez 5 beq bne 95% 5% 30. bne BB6 BB5 Assume 20 nodes can be included in one CI in maximum 13

14 Why Multi-Exits Custom Instructions (MECIs)? adpcm Multiple-Exits Custom Instruction Conditional Execution + Hot-Path Selection BB1 #Required nodes: 17 BB2 BB3 BB bgez 5 beq bne 95% 5% Exit 30. Exit bne BB6 BB5 Assume 20 nodes can be included in one CI in maximum 14

15 Main features of MECIs Fixed point operations Multiply x Divide x Control flow Memory instructions x 15

16 Custom Instruction Invocation How to change the execution sequence and run custom instructions on the CRFU? Software (mtc1-like instruction) method Hardware (table look-up) method 16

17 Software method mtc bgez 5 beq exit bne exit1 exit2 bne inst. # address inst. operands (dest, src1, src2) addu R13 R0 R lw R R addiu R4 R subu R3 R2 R bgez R addiu R13 R beq R subu R3 R0 R addu R10 R0 R lw R8 R9 0x slt R2 R3 R addu R8 R8 R ori R10 R bne 4004a8 R addiu R10 R subu R3 R3 R addu R8 R8 R sra R9 R9 0x a0 slt R2 R3 R a8 ori R10 R b0 4004b8 subu bne R3 R R9 R c0 slt R2 R3 R9 inst. # address inst. operands (dest, src1, src2) lw R R mtc1 addu R13 #CI R0 R addiu R4 R subu R3 R2 R bgez R addiu R13 R beq R subu R3 R0 R addu R10 R0 R slt lw R2 R8 R3 R9 R9 0x addu R8 R8 R ori R10 R bne 4004a8 R addiu R10 R subu R3 R3 R addu R8 R8 R sra R9 R9 0x a0 4004a8 slt ori R2 R3 R9 R10 R b0 4004b8 subu bne R3 R R9 R c0 slt R2 R3 R9 exit3 Instruction scheduling Code before generating MECI 17 Code after generating MECI

18 Hardware method bgez 5 beq exit bne exit3 exit1 bne exit2 address CI Index sequencer table (CAM) 18

19 Outline Introduction General Overview of the Proposed Approach Multi-Exits Custom Instructions Energy Consumption Evaluation Evaluation Results Conclusions and Future Work 19

20 Compare Energy Consumption Energy Conventional RISC Processor (Base) ADEXOR Clock N CLOCK E CYCLE N CLOCK ECYCLE Components ($, RFs, FUs, ) AC COMP E COMP AC COMP E COMP comp comp Off-chip accesses N MISS E OFFCHIP N MISS EOFFCHIP CRFU E OVERHEAD 20

21 Energy Overhead for CRFU Energy Overhead Software-base Invocation Hardware-base Invocation CRFU Exe. Config. Memory # MECIs i= 1 # MECIs i= 1 # MECIs ( i) CRFU MECI( i) i= 1 N MECI E # MECIs ( i) CONFIG MECI i= 1 N MECI E N MECI E ( i) N MECI E ( i) CRFU MECI( i) CONFIG MECI Register-File (for port sharing) N RF R / W E RF OVERHEAD N RF R / W E RF OVERHEAD Invocation N IFETCH E TABLE LOOKUP 21

22 Energy Consumption Pros. Low activity of hardware components I-Cache, Bpred Decoder Register File Functional Unit Higher I-Cache hit rates Reduce the energy for offchip accesses Cons. CRFU configuration Accessing the config. Memory Setting control signals in the CRFU Increased complexity Communication between the processor s data-path and the CRFU 22

23 Outline Introduction General Overview of the Proposed Approach Multi-Exits Custom Instructions Energy Consumption Evaluation Evaluation Results Conclusions and Future Work 23

24 Experimental Setup Issue 4-way L1-Instruction Cache 16K, 2 way, 1 cycle latency, miss penalty 20 cycles L1- Data Cache 16K, 4 way, 1 cycle latency, miss penalty 20 cycles ALUs Multiplier Divider Branch predictor Branch prediction table size Extra branch misprediction 4 integer, 4 floating point 1 Integer, 1 Floating point 1 Integer, 1 Floating point bimodal

25 avg-mtc1 avg-seq gsm Access Reduction Decoder Branch Predictor Reg File I-Cache Int ALU Result Bus Miss of I-Cache Reducing access to components (%) 0 basicmath bitcounts qsort susan cjpeg djpeg dijkstra patricia blowfish rijndael stringsearch sha adpcm crc fft HW Invocation (Table Look-up)

26 Total Energy Reduction clock gating 200 MHz 250 MHz 300 MHz 350 MHz 400 MHz basicmath bitcounts qsort susan cjpeg djpeg dijkstra patricia blowfish rijndael stringsearch sha adpcm crc fft gsm avg-seq avg-mtc % HW Invocation (Table Look-up) Total energy reduciton (%)

27 avg-100x avg-50x avg-10x avg-1x gsm MECIs vs. CIs crc MECI-clock-gating CI-clock-gating MECI-300MHz CI-300MHz % SW Invocation (mtc1-like inst.) basicmath bitcounts qsort jpeg dijkstra patricia blowfish adpcm Total energy reduction (%)

28 Outline Introduction General Overview of the Proposed Approach Multi-Exits Custom Instructions Energy Consumption Evaluation Evaluation Results Conclusions and Future Work 28

29 Conclusions Adaptive, Extensible Processor A coarse-grain re-configurable FU Multi-Exits Custom Instructions Energy Efficiency v.s. base-processor: 42% reduction v.s. BB-base CIs: 15% more energy saving Future Work Chip implementation for accurate evaluations 29