CSE140: Components and Design Techniques for Digital Systems

Transcription

1 CSE140: Componts and Design Techniques for Digital Systems Tajana Simunic Rosing 1

2 Outline Today: Memory ROM RAM FIFO Queue Next: Register Transfer Level Design 2

3 CSE140: Componts and Design Techniques for Digital Systems Memory Tajana Simunic Rosing 3

4 Memory: basic concepts Stores large number of bits m x n: m s of n bits each k = Log2(m) ess input signals or m = 2^k s e.g., 4,096 x 8 memory: 32,768 bits 12 ess input signals 8 input/output signals Memory access r/w: selects read or write able: read or write only wh asserted multiport: multiple accesses to differt locations simultaneously r/w able A 0 A k-1 m s m n memory n bits per memory external view 2 k n read and write memory Q n-1 Q 0 4

5 Write ability/ storage permance Traditional ROM/RAM ROM read only, bits stored without power RAM read and write, lose stored bits without power Distinctions blurred Advanced ROMs can be writt to Storage permance Life of product Ts of years Battery life (10 years) Near zero Mask-programmed ROM Nonvolatile During fabrication only OTP ROM External programmer, one time only EPROM External programmer, 1,000s of cycles EEPROM In-system programmable External programmer External programmer OR in-system, block-orited writes, 1,000s of cycles e.g., EEPROM OR in-system, 1,000s of cycles Advanced RAMs can hold bits without power e.g., NVRAM Write ability and storage permance of memories, showing relative degrees along each axis (not to scale). FLASH Ideal memory NVRAM SRAM/DRAM Write ability In-system, fast writes, unlimited cycles 5

6 Random Access Memory (RAM) RAM Readable and writable memory Logically the same as register file RAM just one port; register file two or more RAM vs. register file RAM is larger RAM stores bits using a bit storage vs. FFs RAM implemted on a chip in a square keeps longest wires (hce delay) short W_ W_ rw RAM R_ R_ W_ R_ register file Register file 32 4 RAM block symbol 6

7 RAM Internal Structure rw 1024x32 RAM Let A = log 2 M d0 w(n-1) able w(n-2) w0 bit storage block (aka cell ) 0 1 (A-1) a0 a1 AxM d1 decoder a(a-1) cell clk rw e d(m-1) to all cells r(n-1) r(n-2) r0 able able rw RAM cell Similar internal structure as register file Decoder ables appropriate based on ess inputs rw controls whether cell is writt or read Let s see what s inside each RAM cell 7

8 32 10 rw 1024x32 RAM Static RAM (SRAM) - writing 0 1 (A-1) clk rw w(n-1) Let A = log 2 M able d0 a0 a1 A M d1 decoder a(a-1) Static RAM cell 6 transistors (recall inverter is 2 transistors) Writing this cell able input comes from decoder Wh 0, value d loops around inverters That loop is where a bit stays stored Wh 1, the bit value ters the loop is the bit to be stored in this cell ters on other side Example shows a 1 being writt into cell e d(m-1) to all cells r(n-1) w(n-2) r(n-2) w0 r0 bit storage block,, (aka cell ),, cell able able rw SRAM cell able SRAM cell able 1 d 0 d 1 1 cell d 0 0 8

9 Static RAM (SRAM) - reading rw 1024x32 RAM 0 1 (A-1) clk rw w(n-1) Let A = log 2 M able d0 a0 a1 A M d1 decoder a(a-1) Static RAM cell - reading Wh rw set to read, the RAM logic sets both and to 1 The stored bit d will pull either the left line or the right bit down slightly below 1 Sse amplifiers detect which side is slightly pulled down e d(m-1) to all cells r(n-1) w(n-2) r(n-2) w0 r0 bit storage block,, (aka cell ),, cell able able rw SRAM cell able 1 1 d <1 To sse amplifiers 9

10 Dynamic RAM (DRAM) rw 1024x32 RAM 0 1 (A-1) clk rw Dynamic RAM cell w(n-1) Let A = log 2 M able d0 a0 a1 A M d1 decoder a(a-1) d(m-1) 1 transistor (rather than 6) Relies on large capacitor to store bit e to all cells r(n-1) w(n-2) r(n-2) w0 Write: Transistor conducts, voltage level gets stored on top plate of capacitor Read: Just look at value of d Problem: Capacitor discharges over time Must refresh regularly, by reading d and th writing it right back r0 bit storage block,, (aka cell ),, cell able able rw DRAM cell able able d d (a) discharges (b) cell capacitor slowly discharging 10

11 Comparing Memory Types Register file Fastest But biggest size SRAM Fast More compact than register file DRAM Slowest And refreshing takes time But very compact Differt technology for large caps. register file MxN Memory implemted as a: SRAM DRAM Size comparison for the same number of bits (not to scale) REGISTER FILE SRAM DRAM OUT1 OUT2 OUT3 OUT4 R S R S R S R S D Q D Q D Q D Q Data' W Data Data CLK IN1 IN2 IN3 IN4 W 11

12 Geric SRAM timing CE R/W Adrs Data From SRAM From CPU read write time

13 Geric DRAM timing CE R/W RAS CAS Adrs Data row adrs col adrs time 13

14 Page mode access CE R/W RAS CAS Adrs row adrs col adrs col adrs col adrs Data time 14

15 Ram variations PSRAM: Pseudo-static RAM DRAM with built-in memory refresh controller Popular low-cost high-dsity alternative to SRAM NVRAM: Nonvolatile RAM Holds after external power removed Battery-backed RAM SRAM with own permantly connected battery writes as fast as reads no limit on number of writes unlike nonvolatile ROM-based memory SRAM with EEPROM or flash stores complete RAM contts on EEPROM or flash before power turned off 15

16 Extded out DRAM Improvemt of FPM (full page mode) DRAM Extra latch before output buffer allows strobing of cas before read operation completed Reduces read/write latcy by additional cycle ras cas ess row col col col Speedup through overlap 16

17 (S)ynchronous and Enhanced Synchronous (ES) DRAM SDRAM latches on active edge of clock Eliminates time to detect ras/cas and rd/wr signals A counter is initialized to column ess th incremted on active edge of clock to access consecutive memory locations ESDRAM improves SDRAM added buffers able overlapping of column essing faster clocking and lower read/write latcy possible clock ras cas ess row col 17

18 Rambus DRAM (RDRAM) More of a bus interface architecture than DRAM architecture Data is latched on both rising and falling edge of clock Brok into 4 banks each with own row decoder can have 4 pages op at a time Capable of very high throughput 18

19 DRAM integration problem SRAM easily integrated with CPU DRAM more difficult Differt chip making process betwe DRAM and convtional logic Goal of convtional logic (IC) designers: minimize parasitic capacitance to reduce signal propagation delays and power consumption Goal of DRAM designers: create capacitor cells to retain stored information 19

20 RAM Example: Digital Sound Recorder RAM rw wire microphone analog-todigital converter 16 ad_buf ad_ld 12 Ra Rrw R processor da_ld digital-toanalog converter wire speaker Behavior Record: Digitize sound, store as series of bit digital values in RAM We ll use a 4096x16 RAM (12-bit wide RAM not common) Play back later from RAM 20

21 RAM Example: Digital Sound Recorder Record behavior Local register: a (12 bits) S T a< x16 RAM a=0 ad_ld=1 ad_buf=1 Ra=a Rrw=1 R=1 U a=a+1 analog-todigital converter 16 ad_buf ad_ld 12 processor Ra Rw R da_ld digital-toanalog converter a=4095 Keep local register a Stores currt ess, ranges from 0 to 4095 Create state machine that counts from 0 to 4095 using a For each a Read analog-to-digital conv: ad_ld=1, ad_buf=1 Write to RAM at ess a: Ra=a, Rrw=1, R=1 21

22 RAM Example: Digital Sound Recorder Play behavior V Local register: a (12 bits) W a< x16 RAM bus a=0 ad_buf=0 Ra=a Rrw=0 R=1 X da_ld=1 a=a+1 analog-todigital converter 16 ad_buf ad_ld 12 processor Ra Rw R da_ld digital-toanalog converter a=4095 Create state machine that counts from 0 to 4095; for each a: Read RAM Write to digital-to-analog conv. Note: Must write d-to-a one cycle after reading RAM, wh the read is available on the bus 22

23 Read-Only Memory ROM Memory that can only be read from Data lines are output only Advantages over RAM Nonvolatile Low power Compact x32 ROM ROM block symbol Let A = log 2 M d0 able bit storage block (aka cell ) 0 1 (A-1) clk a0 a1 AxM d1 decoder a(a-1) e d(m-1) able able r(n-1) r(n-2) r0 ROM cell 23

24 ROM Types 1 line 0 line Mask-programmed ROM cell cell Bits are hardwired as 0s or 1s during chip manufacturing able Fuse-Based Programmable ROM Each cell has a fuse Programmer blows certain fuses (using higher-than-normal voltage) Those cells will be read as 0s (involving some special electronics) Cells with unblown fuses will be read as 1s Aka. One-Time Programmable ROM able 1 cell fuse line 1 line cell blown fuse 24

25 ROM Types Erasable Programmable ROM (EPROM) Uses floating-gate transistor in each cell Programmer uses higher-than-normal voltage to cause electrons to tunnel into the gate Electrons become trapped in the gate Only done for cells that should store 0 floating-gate transistor Other cells will be 1 To erase, shine ultraviolet light onto chip Gives trapped electrons ergy to escape Requires chip package to have window Electronically-Erasable Programmable ROM (EEPROM) Programming similar to EPROM Erasing one at a time electronically Flash memory Like EEPROM, but large blocks of s can be erased simultaneously EEPROM & FLASH are in-system programmable able line 1 write busy cell e Ð e Ð line trapped electrons 1024x32 EEPROM 25 cell 0

26 ROM Example: Digital Telephone Answering Machine Record the outgoing announcemt Wh rec=1, record digitized sound in locations 0 to 4095 Wh play=1, play those stored sounds to digital-to-analog converter busy 4096x16 Flash We re not home. analog-todigital converter 16 ad_buf ad_ld 12 Ra Rrw Rer processor bu da_ld digital-toanalog converter rec record play microphone speaker 26

27 ROM Example: Digital Telephone Answering Machine S a=0 er=1 rec Local register: a (13 bits) bu T er=0 bu U ad_ld=1 ad_buf=1 Ra=a Rrw=1 R=1 a=a+1 a<4096 V a=4096 da rw analog-todigital converter 16 ad_buf ad_ld 12 microphone 4096x16 Flash Ra processor record Rrw R er rec play speaker bu da_ld digital-toanalog converter High-level state machine Once rec=1, begin erasing flash by setting er=1 Wait for flash to finish erasing by waiting for bu=0 Execute loop that sets local register a from 0 to 4095, reading analog-to-digital converter and writing to flash for each a 27

28 Composing Memory Wider Words x8 1024x8 ROM ROM x8 ROM x8 ROM 8 (31..0) 10 Making memory s wider 1024x32 ROM Easy just place memories side-by-side until desired width obtained Share ess/control lines, concatate lines Example: Compose 1024x8 ROMs into 1024x32 ROM 32 28

29 Composing Memory More Words a10 just chooses which memory to access a10a9a8 Provin ce 1 Provin ce 2 a x8 ROM Creating memory with more s Combine memories until the number of desired s is achieved Use decoder to select Example: Compose 1024x8 memories into 2048x8 memory More s and wider s first make ough s, th wid 1024x8 ROM a10 a9..a0 i0 2048x8 ROM 8 1x2 dcd e d0 d1 1024x8 ROM x8 ROM 8

30 r Queues back front B write items to the back of the queue read (and remove) items from front of the queue FIFO Queue (first-in-first-out) Write at the back: push, Read at the front: pop Treat memory as a circle Common uses: Computer keyboard Pushes pressed keys onto queue; Meanwhile pop and sd to computer Digital video recorder Pushes frames onto queue; Meanwhile pops frames, compresses them, and stores them Routers Pushes incoming packets onto queue; Meanwhile pops packets, processes destination information, and forwards each packet out over appropriate port r f 4 30

31 Queues Two conditions have front=rear need FSM to detect: Full: No pushes until a pop Empty: No pops until a push Use Register file for storage Implemt Rear and front with up counters: rear as RF s write ess, front as read ess w wr rd reset Controller 8 16 register file w r 3 clr inc 3-bit up counter rear eq w wr = clr r rd inc 3-bit up counter front 3 r full 8-16-bit queue empty 31

32 Summary Memory RAM ROM Combining Memory Queue 32