Hardware Platforms for Embedded Computing

Transcription

1 Hardware Platforms for Embedded Computing Graphics: Alexandra Nolte, Gesine Marwedel, 2003

2 Importance of Energy Efficiency Efficient software design needed, otherwise, the price for software flexibility cannot be paid. Hugo De Man (IMEC) Philips, 2007

3 Embedded vs. general-purpose processors Embedded processors may be optimized for a category of applications. Customization may be narrow or broad. We may judge embedded processors using different metrics: Code size. Memory system performance. Preditability. Disappearing distinction: embedded processors everywhere

4 Microcontroller Architectures CPU Address Bus Data Bus 0 2 n Memory Program + Data Von Neumann Architecture CPU Address Bus Fetch Bus Address Bus 0 0 Memory Program Harvard Architecture Data Bus Data

5 RISC processors RISC generally means highly-pipelinable, one instruction per cycle. Pipelines of embedded RISC processors have grown over time: ARM7 has 3-stage pipeline. ARM9 has 5-stage pipeline. ARM11 has eight-stage pipeline. ARM11 pipeline [ARM05].

6 ARM Cortex Based on ARMv7 Architecture & Thumb -2 ISA ARM Cortex A Series - Applications CPUs focused on the execution of complex OS and user applications First Product: Cortex-A8 Executes ARM, Thumb-2 instructions ARM Cortex R Series - Deeply embedded processors focused on Real-time environments First Product: Cortex-R4(F) Executes ARM, Thumb-2 instructions ARM Cortex M Series - Microcontroller cores focused on very cost sensitive, deterministic, interrupt driven environments First Product: ARM Cortex-M3 (2uA, 0.5mW/MHz) Executes Thumb-2 instructions

7 Cortex-M3 Processor

8 Central Core Harvard architecture Separate Instruction & Data buses enable parallel fetch & store Advanced 3-Stage Pipeline Includes Branch Forwarding & Speculation Additional Write-Back via Bus Matrix

9 Microcontrollers CPU Memory ROM RAM I/O A single chip Subsystems: Timers, Counters, Analog Interfaces, I/O interfaces

10 A Microcontroller SOC example: STM32 Value line 64K-128KBytes System Diagram Core and operating conditions - ARM Cortex -M DMIPS/MHz up to 24 MHz V to 3.6 V range to +105 C Rich connectivity - 8 communications peripherals Advanced analog - 12-bit1.2 µs conversion time ADC - Dual channel 12-bit DAC Enhanced control - 16-bit motor control timer - 6x 16-bit PWM timers LQFP48, LQFP/BGA64, LQFP100 CORTEX TM -M3 CPU 24 MHz JTAG/SW Debug Nested vect IT Ctrl 1 x Systick Timer DMA 7 Channels 1 x 16-bit PWM Synchronized AC Timer Up to 16 Ext. ITs 37/51/80 I/Os 1 x SPI 1 x USART/LIN Smartcard/IrDa Modem Control ARM Lite Hi-Speed Bus Matrix / Arbiter (max 24MHz) Bridge ARM Peripheral Bus (max 24MHz) Flash I/F Bridge 64kB - 128kB Flash Memory 8kB SRAM 20B Backup Data Clock Control ARM Peripheral Bus (max 24MHz) 6 x 16-bit Timer 2 x Watchdog (independent & window) 2-channel 12-bit DAC 1 x 12-bit ADC up to16 channels Temperature Sensor Power Supply Reg 1.8V POR/PDR/PVD XTAL oscillators 32KHz + 4~25MHz Int. RC oscillators 40KHz + 8MHz PLL RTC / AWU 1 x CEC 2 x USART/LIN Smartcard / IrDa Modem Control 1 x SPI 2 x I 2 C

11 DSP Applications Audio applications MPEG Audio Portable audio Digital cameras Wireless Cellular telephones Base station Networking Cable modems ADSL VDSL Embeded computing needs lots of DSP capabilities

12 DSP architectures n-1 Application: y[j] = i=0 x[j-i]*a[i] i: 0 i n-1: y i [j] = y i-1 [j] + x[j-i]*a[i] Architecture: Example: Data path ADSP210x * +,- Addressregisters A0, A1, A2.. i+1, j-i+1 Address generation unit (AGU) AX D AR x +,-,.. AY AF P a x[j-i] MX MR MY a[i] MF x[j-i]*a[i] y i-1 [j] - Parallelism - Dedicated registers MR:=0; A1:=1; A2:=n-2; MX:=x[n-1]; MY:=a[0]; for ( j:=1 to n) {MR:=MR+MX*MY; MY:=a[A1]; MX:=x[A2]; A1++; A2--}

13 DSP - Features (1) Multiply/accumulate (MAC) and zero-overhead loop (ZOL) instructions (as shown) Heterogeneous registers (as shown) Separate address generation units (AGUs) (as in ADSP 210x)

14 Single Issue vs VLIW instr instr instr instr instr instr instr instr instr instr instr instr op op op op op op op op op op op op execute 1 instr/cycle Compiler instr instr instr instr instr execute 1 instr/cycle 3 ops/cycle op op op nop op op op op nop op nop op op op op 3-issue VLIW Single Issue CPU 2/25/2016 Embedded Computer Architecture H. Corporaal and B. Mesman 14

15 ARM Processors Families 15

16 Cortex-M4 ARMv7E-M Architecture Thumb-2 only DSP extensions Optional FPU (Cortex-M4F) Otherwise, same as Cortex-M3 Implements full Thumb-2 instruction set Saturated math (e.g. QADD) Packing and unpacking (e.g. UXTB) Signed multiply (e.g. SMULTB) SIMD (e.g. ADD8) Cortex M3 Total 60k* Gates University Program Material Copyright ARM Ltd

17 Binary Upwards Compatibility ARMv7-M Architecture ARMv6-M Architecture University Program Material Copyright ARM Ltd

18 Cortex-M4 DSP instructions Remember VLIW? University Program Material Copyright ARM Ltd

19 Multi-processors SoCs for Embedded Computing Graphics: Alexandra Nolte, Gesine Marwedel, 2003

20 Application pull 1TOPS/W 100GOPS/W 5 GOPS/W [IMEC] Mobile Base-band Image recognition H264 encoding 10GOPS/W UWB A/V Sign streaming recognition n Si Xray H264 decoding Fully recognition (security) dictation Expression recognition Gbit radio Adaptive route Gesture recognition Auto personalization 3D ambient Structured interaction decoding Ubiquitous 3D projectednavigation Autonomous display driving HMI by motion Structured Gesture detection encoding Collision avoidance Language Emotion recognition 3D TV 3D gaming Year of Introduction

21 Power Bottleneck Power trend Power Consumption Sub- Threshold Leakage Dynamic Power Gate- Oxide Leakage Possible trajectory for high-k dielectrics Physical Gate Length [nm] Power density trend Power Density (Watts/cm 2 ) nm 180nm 130nm 90nm 65nm 0 Leakage Power Dynamic Power [STM ASIC]

22 Multi-Core & Power Cache Large Core Power Performance 2 Small Core 1 Power = 1/4 Performance = 1/2 1 1 C1 C3 Cache C2 C Multi-Core: Power efficient Better power and thermal management

23 µarchitecture Techniques Cache % of Total Area 100% Increase on-die Memory 75% Pentium M 50% Pentium III 25% 486 Pentium Pentium 4 Multi-threading Single Thread Full HW Utilization ST Wait for Mem Multi-Threading MT1 Wait for Mem MT2 Wait MT3 0% 1u 0.5u 0.25u 0.13u 65nm Improved performance, no impact on thermals & power delivery Large Core Chip Multi-processing C1 C2 Cache C3 C4 Relative Performance 3,5 3 2,5 2 1,5 1 Multi Core Single Core Die Area, Power

24 Integrated SoC Mobile High-speed SMP for almost sequential GP Processor arrays for domain-specific throughput computing (100x GOPS/W) ultra parallel 24

25 H-SOC in 2013 Apple A7 Used in IPad AIR & IPhone 5s

26 H-SOC in 2015/16 Tegra K1

27 Heterogeneous Computing in K1 Visual Analytics & Computational Photography

28 Accelerated (Heterogeneous) Embedded Computing Graphics: Alexandra Nolte, Gesine Marwedel, 2003

29 Hardware Execution Model CPU Lane 0 Lane 1 Lane 0 Lane 1 Lane 0 Lane 1 Lane 15 Lane 15 Lane 15 CPU Memory Core 0 GPU Core 1 Core 15 GPU Memory GPU is built from multiple parallel cores, each core contains a multithreaded SIMD processor with multiple lanes but with no scalar processor CPU sends whole grid over to GPU, which distributes thread blocks among cores (each thread block executes on one core) Programmer unaware of number of cores 29

30 CPUs vs GPUs Control CPU ALU ALU ALU ALU GPU Cache DRAM DRAM David Kirk/NVIDIA and Wen-mei W. Hwu, ECE 408, University of 30

31 CUDA Programmer's View of GPUs A GPU contains multiple SIMD Units.

32 CUDA Programmer's View of GPUs A GPU contains multiple SIMD Units. All of them can access global memory.

33 Simplified CUDA Programming Model Computation performed by a very large number of independent small scalar threads (CUDA threads or microthreads) grouped into thread blocks. // C version of DAXPY loop. void daxpy(int n, double a, double*x, double*y) { for (int i=0; i<n; i++) y[i] = a*x[i] + y[i]; } // CUDA version. host // Piece run on host processor. int nblocks = (n+255)/256; // 256 CUDA threads/block daxpy<<<nblocks,256>>>(n,2.0,x,y); device // Piece run on GP-GPU. void daxpy(int n, double a, double*x, double*y) { int i = blockidx.x*blockdim.x + threadid.x; if (i<n) y[i]=a*x[i]+y[i]; } 33

34 Thread Hierarchy in CUDA Grid contains Thread Blocks Thread Block contains Threads

35 Sharing memory Mobile GPUs share memory with CPU Converging also for general computing: Heterogeneous System Architecture

36 Energy Efficiency Again MP+GPU MP What if workload is not Friendly to MultiProc or GPU? Efficient software design needed, otherwise, the price for software flexibility cannot be paid. Hugo De Man (IMEC) Philips, 2007

37 FPGA Reconfigurable computing Computer architecture combining some of the flexibility of software with the high performance of hardware by processing with very flexible high speed computing fabrics like field-programmable gate arrays (FPGAs). The principal difference when compared to using ordinary microprocessors is the ability to make substantial changes to the datapath itself in addition to the control flow. The main difference with custom hardware, i.e. application-specific integrated circuits (ASICs) is the possibility to adapt the hardware during runtime by "loading" a new circuit on the reconfigurable fabric. [wikipedia]

38 ASIC or FPGA? ASIC = specify, design and fabricate a new chip FPGA = specify, design and configure a configurable chip

39 FPGA Architecture The basic structure of an FPGA is composed of the following elements: Look-up table (LUT): This element performs logic operations Flip-Flop (FF): This register element stores the result of the LUT Wires: These elements connect elements to one another, both Logic and clock Input/Output (I/O) pads: These physically available ports get signals in and out of the FPGA. ESS FPGA for Dummies Maurizio Donna

40 FPGA Components: Logic How can we implement any circuit in an FPGA? Combinational logic is represented by a truth table (e.g. full adder). Implement truth table in small memories (LUTs). A function is implemented by writing all possible values that the function can take in the LUT The inputs values are used to address the LUT and retrieve the value of the function corresponding to the input values ESS FPGA for Dummies Maurizio Donna

41 FPGA Components: Logic A LUT is basically a multiplexer that evaluates the truth table stored in the configuration SRAM cells (can be seen as a one bit wide ROM). How to handle sequential logic? Add a flip-flop to the output of LUT (Clocked Storage element). This is called Basic Logic Element (BLE): circuit can now use output from LUT or from FF. ESS FPGA for Dummies Maurizio Donna

42 FPGA Components: wires Before FPGA is programmed, it doesn t know which CLBs will be connected: connections are design dependent, so there are wires everywhere (both for DATA and CLOCK)!!!!! CLBs are typically arranged in a grid, with wires on all sides. CLB CLB CLB CLB CLB CLB To connect CLB to wires some Connection box are used: these devices allow inputs and outputs of CLB to connect to different wires ESS FPGA for Dummies Maurizio Donna

43 FPGA Components: wires Connection boxes allow CLBs to connect to routing wires but that only allows to move signals along a single wire; to connect wires together Switch boxes (switch matrices) are used: these connect horizontal and vertical routing channels. The flexibility defines how many wires a single wire can connect into the box. Switch box/matrix ROUTABILITY is a measure of the number of circuits that can be routed CLB CLB HIGHER FLEXIBILITY = BETTER ROUTABILITY CLB CLB ESS FPGA for Dummies Maurizio Donna

44 FPGA Components: wires FPGA layout is called a FABRIC : is a 2-dimensional array of CLBs and programmable interconnections. Sometimes referred to as an island style architecture. ESS FPGA for Dummies Maurizio Donna

45 FPGA Components: memory The FPGA fabric includes embedded memory elements that can be used as random-access memory (RAM), read-only memory (ROM), or shift registers. These elements are block RAMs (BRAMs), LUTs, and shift registers. Using LUTs as SRAM, this is called DISTRIBUTE RAM Included dedicated RAM components in the FPGA fabric are called BLOCKs RAM ESS FPGA for Dummies Maurizio Donna

46 FPGA Components: input/output The IO PAD connect the signals from the PCB to the internal logic. The IOB are organized in banks (depending on the technology and the producer the number of IOB per bank change). All the PAD in the same bank, share a common supply voltage: not all the different standard could be implemented at the same time in the same bank!!!! There are special PAD for ground (GND), supplies (VCC, VCCINT, VCCAUX, etc ), clocks and for programming (JTAG). ESS FPGA for Dummies Maurizio Donna

47 FPGA Components: input/output The IO Blocks (IOB) support a wide range of commercial standard (LVTTL, LVCMOS, LVDS, etc ) both single ended and differential (in that case pair of contiguous pad are used). In the PAD are available FF that are use to resynchronize the signal with the internal clock. ESS FPGA for Dummies Maurizio Donna

48 HW Design flow

49 Designing with FPGA FPGAs are configured using a HW design flow Describe the desired behavior in a HDL Use the FPGA design automation tools to turn the HDL description into a configuration bitstream After configuration, the FPGA operates like dedicated hardware HW design expertise needed, low abstraction level, much slower than SW design on processors! What about mixing FPGAs and Processors?

50 Traditional Discrete Component Architecture Source: The Zynq Book

51 Heterogenous Architecture CPU+FPGA Source: The Zynq Book

52 Mapping of an Embedded SoC Hardware Architecture to Zynq Source: Xilinx White Paper: Extensible Processing Platform

53 Comparison with Alternative Solutions ASIC ASSP 2 Chip Solution Zynq Performance Power Unit Cost Total Cost of Ownership Risk Time to Market Flexibility Scalability positive, negative, neutral Source: Xilinx Video Tutorials

54 Basic Design Flow for Zynq SoC Source: The Zynq Book

55 Design Flow for Zynq SoC Source: Xilinx White Paper: Extensible Processing Platform