Comprehensive RISC-V Solutions for Diversified SoCs

Transcription

1 Comprehensive RISC-V Solutions for Diversified SoCs 2018/11/ Andes RISC-V Con Santa Clara Charlie Su, Ph.D. CTO and SVP

2 Agenda Diversified SoC Requirements AndeStar V5: Best Extensions to RISC-V AndesCore 25-Series Processors Supporting Environments Andes Custom Extensions (ACE) Concluding Remarks Driving Innovations 2

3 Diversified SoC Requirements Driving Innovations 3

4 Diversified Usage of AndesCore Rich experience based on customer diversified needs: Interrupt sources: <16? >100? Interrupt latencies: care and don t care Data processing: Efficiency: DSP+SIMD based on existing GPR s Performance: scalable vectors with more resources Write-back and write-through caches Loading RO-data from icache! Hardwired engines vs. coprocessors Small cores in MCU s or large SoC s Open-source compilers or commercial compilers Driving Innovations 4

5 AndeStar V5: Best Extension to RISC-V Driving Innovations 5

6 Merits of RISC-V ISA Compact kernel (I/E) Modular extensions: M, A, C, F, D, Freedom of custom extensions Andes comprehensive solutions through custom extensions RISC-V Architecture Extensibility is the key to advance RISC-V by Standardizing on the common baseline Allowing innovations to extend RISC-V for their respective market Krste Asanovic 1, Healthy Discussion of Architectural Choices 2 : RISC-V was designed to support specialization while avoiding fragmentation by mandating a frozen common ISA standard around which the software community coalesces, while leaving ample space for innovative custom extensions that do not interfere Note 1: Chariman of the RISC-V Foundation, Berkeley Professor, and SiFive co-founder Note 2: EE Times, 7/11/2018 Driving Innovations 6

7 Andes Comprehensive RISC-V Solutions Best extensions to RISC-V AndeStar Architecture V5 Highly optimized design for long life cycle AndesCore Processors Standby & VIC AndesCore ucore Instr LM Intf Data LM Intf COP Intf ITLB MMU/MPU DTLB Instr Cache EDM Data Cache AndeSight Tools Professional IDE with high code quality DMA Engine Bus Interface Unit Handy peripheral IPs to speed up SoC construction AndeShape Platforms AndeSoft Stacks Extensive SW stacks from bare metal, RTOS to Linux Driving Innovations 7

8 Andes Extended RISC-V Solutions More choices for customers Andes works closely with partners to grow RISC-V ecosystem Driving Innovations 8

9 AndeStar V5: Best Extensions to RISC-V AndeStar V5: RISC-V + Andes Extensions Baseline ISA extensions: Faster memory accesses Faster branches More compact code on top of RV-C Andes Custom Extension (ACE) frameworks for DSA Powerful tools No CPU design experience needed DSP/SIMD ISA based on GPRs: Chairing P-ext TG with Andes popular DSP ISA as the starting point Full cache support: Management operations (flush, invalidate, etc.) at the line level Uncached accesses Write-back and write-through PLIC extension: Vectored dispatch Priority-based preemption Save >50% of instructions Co-chairing Fast Interrupt TG to push to the standard Driving Innovations 9

10 State of RISC-V SW Driving Innovations 10

11 GNU Toolchains GCC, binutils: May, 2017 Newlib: Aug, 2017 Glibc (rv64i): Feb, 2018 GDB: Mar, 2018 OpenOCD: July, 2018 Glibc (rv32i): Submitted since July 2018 (by Andes) Review in progress Driving Innovations 11

12 LLVM Toolchains LLVM: RV32IMAFDC: June, 2018 Relaxation: May, 2018 (by Andes) 64b support: review in progress since Oct, 2018 Missing hard-float calling convention compiler-rt: Mar, 2018 LLD: Aug, 2018 (by Andes) Initial port (relocation and TLS) in Oct Dynamic linking review in progress since Oct, 2017 Missing link-time relaxation Driving Innovations 12

13 Linux and Friends U-boot: Jan, 2018 (by Andes) Kernel (rv64i): Jan, 2018 Key utilities: (by Andes) Perf: Feb, 2018 Kernel Module: May, 2018 Ftrace: May, 2018 Kernel (rv32i): Jun, 2018 (by Andes) Kernel with no FPU: Oct, 2018 Driving Innovations 13

14 AndesCore 25-Series Processors Driving Innovations 14

15 Common Features of the 25-Series 32-bit and 64-bit cores From scratch for the best PPA AndeStar V5 ISA Superset of RISC-V IMAC ISA 5-stage pipeline, single-issue 1 full-cycle for key SRAMs Speed similar to traditional 8-stage cores Only use single-ported Configurable multiplier Sequential: 1~8 bits per cycle Parallel: pipelined 2 cycles Optional branch prediction PLIC SRAM/AHBL PMU AHB/AXI Debug Module SRAM/AHBL Driving Innovations 15

16 Common Features of the 25-Series Memory subsystem I/D Local Memory (LM): optional Size: 4KB to 16MB Interface: SRAM or AHB-lite I/D caches: optional Size: 8KB to 64KB Direct-map, 2-way, 4-way Error protection: optional Parity or ECC 1 (SECDED) Bus interface A master port (AHB/AXI) An optional slave port (AHB) JTAG debug module up to 8 triggers(breakpoints/watchpoints) PLIC PMU Debug Module Note 1: ECC for LM only supports SRAM intf currently. AHB-lite intf available upon request. SRAM/AHBL AHB/AXI SRAM/AHBL Driving Innovations 16

17 V5 AndesCore : the 25-Series N25/NX25: Fast-n-small cores for control tasks in AI, AR/VR, networking, storage, and more N25F/NX25F: +FPU (F or FD) +,, x, x+, x : pipelined 5 cycles, : run in the background 15 cycles for SP, 29 cycles for DP FP load/store: support Half-Precision (HP) A25/AX25: +FPU +Linux Support RISC-V MMU and S-mode SV{32, 39, 48}, all page sizes 4-way 32~128-entry Shared-TLB 4 or 8-entry ITLB and DTLB Whetstone/MHz: 1.04 IMACFD Perf Ext. CoDense NX25 NX25F AX N25F CM7 CA7 N25 N25F A25 SP DP Driving Innovations 17 A C E

18 28nm PPA for 25-Series Smallest usable N25/NX25 1 : ILM/DLM, no caches/btb 1 GHz: 37K, mm 2, 4.1 uw/mhz NX25@ 1 GHz: 56K, mm 2, 6.0 uw/mhz Features N*25 N*25F A*25 I/D Local Memory KB I$/D$ BTB Yes Yes Yes SP/DP FPU -- Yes Yes MMU and S-Mode Yes Worst-Case Max. Freq. (GHz) Coremark/MHz (rv32), 3.52 (rv64) DMIPS/MHz (ground rule) (rv32), 2.09 (rv64) Note 1: TSMC 28HPC+ RVT 9T library, TSMC high-speed memory. Frequency condition: 0.81v/-40 o c. Note 2: BSP V5.0.0 toolchain; DMIPS/ground rule uses no-inline option. Driving Innovations 18

19 RTL Configuration Tool Driving Innovations 19

20 RTL Configuration Tool Driving Innovations 20

21 Summary of 25-Series Advantages Higher performance (20%) Smaller code size (12%) Rich features for embedded applications Complete features for caches HW misaligned accesses StackSafe stack protection Power management support Fast interrupt handling 2-wire debug support Better Verilog RTL code CPU Open Source Andes N25 GCC Foundation Andes ISA Used RV32IMAC V5 CoreMark/MHz (+8.7%) (+20%) DMIPS/MHz (no-inline) (+6.3%) (+22%) CSiBE 1,185 1,340 Code Size (KB) (-12%) Vendors Readability CAD Tool Configuration by Andes Good Friendly Customers Some Poor Unfriendly Vendors Driving Innovations 21

22 Supporting Environments Platform IPs, ICE, IDE, Boards Driving Innovations 22

23 Pre-integrated AXI and AHB Platform JTAG JTAG Debug Xport Debug Module Interrupt Requests PLIC 25-series BIU BIU master master slave slave Inst. Memory Data Memory CPU Subsystem AXI/AHB IP GPIO I2C PWM/PIT RTC QSPI UART WDT APB Bridge AXI/AHB Bus Matrix Sys. Mgmt Unit DMA Bus Masters Bus Slaves APB IP Customer s or Partner s IP s Driving Innovations 23

24 AndeShape ICE Features Feature AICE2 AICE-MINI Host Interface USB 2.0 Power Supply Multi-Core Debugging Profiling Andes Debug Interface USB bus powered Up to 16 targets Supported JTAG (JDP, 5-wire) Serial (SDP, 2-wire) I/O Voltage (V) 1.8~ ~3.3 Target Connector Download Speed (Write RAM, KB/s) Upload Speed (Read RAM, KB/s) AICE 20 pins AICE 10 pins Trace 20 pins 700 (5w) 500 (2w) 500 (5w) 400 (2w) AICE 20 pins 300 (5w) 100 (2w) 200 (5w) 100 (2w) AICE2 AICE-MINI Driving Innovations 24

25 AndeSight : Professional IDE Eclipse-based, enriched by 13-year effort FreeRTOS Task List FreeRTOS Event List Driving Innovations 25

26 Physical/Virtual Boards and SW Stacks AndeShape Development Boards Full-Featured ADP-XC7 Compact Corvette-F1 (Arduino-compatible) With and ICE on board Simulators supported in AndeSight Andes near-cycle accurate simulator standalone and in SystemC TLM 2.0 Any gdb-remote capable simulator such as Qemu Qemu Virtual Board AX25 with AE350 SoC platform, booted U-Boot and Linux Used by opensuse project for UEFI AndeSoft SW Stack Rich sample projects for Andes-enhanced features RTOS es: FreeRTOS, ThreadX, Contiki, more IoT Stack connecting to the Cloud Driving Innovations 26

27 Andes Custom Extensions (ACE) Driving Innovations 27

28 Driving Innovations 28 Concise Verilog, C code, and attribute setting - scalar/vector - background - wide IO ACE Framework C O P I L O T Custom-OPtimized Instruction development Tools Extended Tools Extended ISS Extended RTL Automated Env. For Cross Checking Test Case Generator Extended RTL Extended ISS Compiler Asm/Disasm Debugger IDE CPU ISS (near-cycle accurate) Extensible Baseline Components Executable or library CPU RTL Source file

29 Driving Innovations 29 Inner Product of Vectors with 64 8-bit Data reg CfReg { //coef. Custom Register num= 4; width= 512; } ram VMEM { //vector Custom Memory interface= sram; address_bits= 3; //8 elements width= 512; } insn ip64b { operand= {out gpr IP, in CfReg C, in VMEM V}; csim= %{ //multi-precision lib. used IP= 0; for(uint i= 0; i<64; ++i) IP+= ((C >>(i*8)) & 0xff) * ((V >>(i*8)) & 0xff); %}; latency= 3; //enable multi-cycle ctrl }; ip64b.ace //ACE_BEGIN: ip64b assign IP= C[ 7:0] * V[ 7:0] + C[15:8] * V[15:8]... + C[511:504] * V[511:504]; //ACE_END ip64b.v VMEM CfReg ACE Logic GPR 512 Speedup: 85x Intrinsic: long ace_ip64b(cfreg_t, VMEM_t);

30 Driving Innovations 30 RTL Debugging Auto-generate waveform control file Operands and ACE interface signals will be added into waveform control file automatically.

31 Driving Innovations 31 Benefits of ACE Users focus on instruction functions, not CPU pipeline Offload housekeeping tasks to COPILOT tools opcode selection instruction decoding operand mapping input operand accesses output operand updates Auto-generate both RTL and simulator code dependence checking Adding instructions is more like ASIC design

32 Concluding Remarks Driving Innovations 32

33 V5 Processor Roadmap BB + P,F ACE 1 < 2 BumbleBee area,power + 4-core P-ext. + V-ext. >2x perf. Aries Multicore (optimized) 25 Series N25/N25F/A25 NX25/NX25F/AX25 Aries Unicore/ Multicore Note: Roadmap is subject to change without notice. Driving Innovations 33

34 Concluding Remarks Comprehensive solutions based on rich SoC experience AndeStar V5: extension to RISC-V with good support AndesCore 25-Series processors: N25/NX25: Fast-n-small cores for control tasks N25F/NX25F: FP cores for compute-intensive tasks and AI A25/AX25: Application processors Powerful ACE unlocking RISC-V s potential for DSA Strong tools and SW support Continued roadmap to serve a broader market Focused and pure-play CPU IP company for 13 years Andes: Trusted Computing Expert and Your Best RISC-V Partner! Driving Innovations 34

35 Thank You! Andes: Trusted Computing Expert and Your Best RISC-V Partner! Driving Innovations 35