Millimeter-Scale Nearly Perpetual Sensor System with Stacked Battery and Solar Cells

Transcription

1 1 Millimeter-Scale Nearly Perpetual Sensor System with Stacked Battery and Solar Cells Gregory Chen, Matthew Fojtik, Daeyeon Kim, David Fick, Junsun Park, Mingoo Seok, Mao-Ter Chen, Zhiyoong Foo, Dennis Sylvester, David Blaauw Electrical Engineering & Computer Science Department The University of Michigan, Ann Arbor University of Michigan 1 1

2 Power Budget, W Motivation 2 Long Device Lifetime Small Form Factor Implantable Medical Devices Military Surveillance Infrastructure Monitoring Smart RFID 1k m 10m 1m 100µ 10µ 1µ 100n 10n 1n 100p minute minute hour hour day day month year decade 10p Desired Lifetime, s Alkaline AA 20mm Li Coin 1mm 2 Li Thin-film month year decade University of Michigan 2 2

3 Power Budget, W Motivation 3 Long Device Lifetime Small Form Factor Implantable Medical Devices Military Surveillance Infrastructure Monitoring Smart RFID 1k m 10m 1m 100µ 10µ 1µ 100n 10n 1n 100p minute minute hour hour day day month year decade 10p Desired Lifetime, s Alkaline AA 20mm Li Coin 1mm 2 Li Thin-film month year decade University of Michigan 3 3

4 8.75mm 3 Sensor System 4 Battery Solar Cells Processor, SRAM and PMU University of Michigan 4 4

5 8.75mm 3 Sensor System 5 Solar cells 2 series solar cells 0.18 µm CMOS Removed nitride and silicide Battery 3.6 V Cymbet thin-film Li 12 µah capacity 2.5 mm x 3.5 mm Integrated circuits Near-threshold Cortex-M3 Low-voltage SRAM Power Management Unit Battery Solar Cells Processor, SRAM and PMU University of Michigan 5 5

6 Typical Operation 6 Active Read sensor Process data Store data Request Grant Wakeup Gen Ctrl JTAG PMU ARM Cortex- M3 Processor State NR-SRAM R-SRAM CDC Sensor Temp. Sensor University of Michigan 6 6

7 Typical Operation 7 Active Read sensor Process data Store data Request Grant Wakeup Gen Ctrl JTAG PMU ARM Cortex- M3 Processor State NR-SRAM R-SRAM CDC Sensor Temp. Sensor University of Michigan 7 7

8 Typical Operation 8 Active Read sensor Process data Store data Request Grant Wakeup Gen Ctrl JTAG PMU ARM Cortex- M3 Processor State NR-SRAM R-SRAM CDC Sensor Temp. Sensor University of Michigan 8 8

9 Typical Operation 9 Active Read sensor Process data Store data Request Grant Wakeup Gen Ctrl JTAG PMU ARM Cortex- M3 Processor State NR-SRAM R-SRAM CDC Sensor Temp. Sensor University of Michigan 9 9

10 Typical Operation 10 Active Read sensor Process data Store data Request Grant Wakeup Gen Ctrl JTAG PMU ARM Cortex- M3 Processor State NR-SRAM R-SRAM CDC Sensor Temp. Sensor University of Michigan 10 10

11 Typical Operation 11 Active Read sensor Process data Store data Request Grant Wakeup C l o c k G e n S l e e p C t r l Timer J T A G P M U Mode A R M C o r t e x - M 3 P r o c e s s o r S l e e p S t a t e N R - S R A M R - S R A M C D C S e n s o r T e m p. S e n s o r University of Michigan 11 11

12 Typical Operation 12 Active Read sensor Process data Store data Request Grant Wakeup Gen Ctrl JTAG PMU ARM Cortex- M3 Processor State NR-SRAM R-SRAM CDC Sensor Temp. Sensor University of Michigan 12 12

13 Typical Operation 13 Active Read sensor Process data Store data Request Grant Wakeup Gen Ctrl JTAG PMU ARM Cortex- M3 Processor State NR-SRAM R-SRAM CDC Sensor Temp. Sensor University of Michigan 13 13

14 Cortex-M3 14 Near-threshold 32-bit microcontroller 0.18 µm CMOS Standard cell library Removed gates with 4+ transistor stacks for robustness Removed gates with size 4x and larger for power/performance tradeoff Characterized at low voltage 24kb R-SRAM PMU Controller Debug ARM Cortex-M3 32-bit Processor State Ctrl Clk Scan SCN 2.2mm 16kb NR-SRAM Temp CDC 2.7mm University of Michigan 14 14

15 R-SRAM 15 Instruction memory Data logging Debug 16kb NR-SRAM Powered on during sleep Low leakage data retention Banks can be individually shut down Reduce leakage of unused SRAM 24kb R-SRAM PMU Controller ARM Cortex-M3 32-bit Processor State Ctrl Clk Scan Temp SCN CDC 2.7mm Twelve 2 kb banks 2.2mm University of Michigan 15 15

16 R-SRAM Operation 16 WL VDD CELL 220nm 500nm VDD READ 880nm 180nm RWL BL 440nm 500nm 440nm 500nm BL RWL 540nm 180nm RBL Robust 400 mv operation Read buffer prevents read upset failures Read buffer pull up prevents unwanted RBL discharge University of Michigan 16 16

17 R-SRAM Operation 17 WL VDD CELL 220nm 500nm Power Gated VDD READ 880nm 180nm RWL BL 440nm 500nm 440nm 500nm BL Low leakage 6T portion not power gated to retain data Power gate read buffer during sleep IO devices and length biasing RWL 540nm 180nm RBL University of Michigan 17 17

18 R-SRAM Operation 18 VDD BOOST WL VDDBOOST VDD CELL 220nm 500nm VDDBOOST VDD READ 880nm 180nm RWL BL 440nm 500nm 440nm 500nm BL RWL 540nm 180nm Higher speed operation (write limited) HVT PMOS pass gates increase speed by 50% 550 mv VDD BOOST is readily available from the PMU WL and BL boosting increases speed by 2.5x RBL University of Michigan 18 18

19 NR-SRAM 19 Temporary storage for DSP algorithms Debug 16kb NR-SRAM Power gated during sleep Similar 10T topology to R-SRAM All SVT devices SVT NMOS pass gates are used for speed No pass gate boosting 24kb R-SRAM PMU Controller ARM Cortex-M3 32-bit Processor State Ctrl Clk Scan Temp SCN CDC 2.7mm Eight 2 kb banks 2.2mm University of Michigan 19 19

20 SRAM Summary and Layout µm CMOS at 500mV Phoenix JSSC 09 NR-SRAM R-SRAM Devices 14T 10T 10T PFET PG Bitcell Area 40.0 μm μm μm 2 Energy/Access/Bit 0.22 fj 0.60 fj 1.18 fj NFET PD Frequency 100 khz 1 MHz 1 MHz Write Asynchronous 1-cycle Multi-cycle Read 1-cycle 1-cycle 1-cycle Leakage/Bit 7.1 fw 6.3 pw 3.3 fw PFET PU R-SRAM Layout Read Buffer Inverter RWL VDD CELL BL GND BL VDD CELL VDD READ RBL GND WL RWL PFET PU NFET PD PFET PG Transmission Gate University of Michigan 20 20

21 SRAM Summary and Layout µm CMOS at 500mV Phoenix JSSC 09 NR-SRAM R-SRAM Devices 14T 10T 10T PFET PG NFET PD Bitcell Area 40.0 μm μm μm 2 Energy/Access/Bit 0.22 fj 0.60 fj 1.18 fj Frequency 100 khz 1 MHz 1 MHz Write Asynchronous 1-cycle Multi-cycle Read 1-cycle 1-cycle 1-cycle Leakage/Bit 7.1 fw 6.3 pw 3.3 fw PFET PU R-SRAM Layout Read Buffer Inverter RWL VDD CELL BL GND BL VDD CELL VDD READ RBL GND WL RWL PFET PU NFET PD PFET PG Transmission Gate University of Michigan 21 21

22 PMU 22 Converts power among the solar cells, battery and integrated circuits Debug 16kb NR-SRAM Co-optimized for efficiency in active and sleep modes Harvests energy during active and sleep mode Recharges the battery 24kb R-SRAM PMU Controller ARM Cortex-M3 32-bit Processor State Ctrl Clk Scan Temp SCN CDC 2.7mm 2.2mm University of Michigan 22 22

23 PMU Overview 10µA Active Mode 23 V BATT Switch Capacitor Network CLK SCNOUT Switched Capacitor Network Solar Monitor SCN Monitor Enable 50Hz 1.2MHz LC Φ 2C Φ 1C Φ 2B C 5 C 6 C 4 V REF Lin Reg Φ 1B C 3 LC Cortex-M3 NRSRAM Ctrl RSRAM Φ 2A Φ 1A C 1 C 2 Ladder SCN divides 3.6 V battery voltage by MHz reduced swing clock with level converters 8.3x energy reduction over full-swing clocking University of Michigan 23 23

24 PMU Overview 10µA Active Mode 24 V BATT Switch Capacitor Network CLK SCNOUT Voltage Reference (V REF ) Solar Monitor SCN Monitor Enable 50Hz 1.2MHz Zero-V TH V REF Lin Reg Cortex-M3 NRSRAM Ctrl RSRAM V REF Seok, CICC 09 Sub-V TH -biased linear regulator removes power supply noise V DD for Cortex-M3 and SRAM set by 8 pa V TH -based V REF 0.05%/V line sensitivity 20 ppm/ºc temperature coefficient University of Michigan 24 24

25 PMU Overview 1nA Mode 25 V BATT Switch Capacitor Network CLK SCNOUT 50Hz Delay Element Solar Monitor SCN Monitor Enable 50Hz 1.2MHz V REF Lin Reg A Z Z A Cortex-M3 NRSRAM Ctrl RSRAM SCN clocked at 50 Hz Linear regulator bypassed and bias current removed 63 pw clock generated with leakage-based delay element University of Michigan 25 25

26 PMU Overview 1nA Mode 26 V BATT Switch Capacitor Network CLK SCNOUT 50Hz Delay Element Solar Monitor SCN Monitor Enable 50Hz 1.2MHz 0-> >0 V REF Lin Reg A Z Z A Cortex-M3 NRSRAM Ctrl RSRAM SCN clocked at 50 Hz Linear regulator bypassed and bias current removed 63 pw clock generated with leakage-based delay element University of Michigan 26 26

27 PMU Overview 1nA Mode 27 V BATT Switch Capacitor Network CLK SCNOUT 50Hz Delay Element Solar Monitor SCN Monitor Enable 50Hz 1.2MHz V REF Lin Reg A Z Z A Cortex-M3 NRSRAM Ctrl RSRAM SCN clocked at 50 Hz Linear regulator bypassed and bias current removed 63 pw clock generated with leakage-based delay element University of Michigan 27 27

28 PMU Overview SCN clocking V BATT Switch Capacitor Network CLK SCNOUT Skipped Pulses PMU 28 Solar Monitor SCN Monitor Enable 50Hz 1.2MHz SCN OUT V REF Lin Reg SCN Cortex-M3 NRSRAM Ctrl RSRAM Measured Waveforms SCN is clocked on demand to accommodate varying loads SCN monitor checks SCN OUT voltage and gates clock Reduces clock energy to increase efficiency by 20% University of Michigan 28 28

29 Photovoltaic Current, A PMU Overview Energy harvesting 29 V BATT Solar Monitor SCN Monitor V REF Switch Capacitor Network Lin Reg Enable 50Hz 1.2MHz Cortex-M3 NRSRAM CLK SCNOUT Ctrl RSRAM suns (AM 1.5) suns suns suns suns Photovoltaic Voltage, mv The solar monitor checks the PV voltage (V PV ) If V PV > V SCNOUT, the PV cells are connected to SCN OUT University of Michigan 29 29

30 Photovoltaic Current, A PMU Overview Energy harvesting 30 V BATT Solar Monitor SCN Monitor V REF Switch Capacitor Network Lin Reg Enable 50Hz 1.2MHz Cortex-M3 NRSRAM CLK SCNOUT Ctrl RSRAM suns (AM 1.5) suns suns suns suns Photovoltaic Voltage, mv The solar monitor checks the PV voltage (V PV ) If V PV > V SCNOUT, the PV cells are connected to SCN OUT If V SCNOUT > V BATT /6, the same SCN recharges the battery University of Michigan 30 30

31 Energy per Inst, J Frequency, Hz Processor Performance vs. Energy M 500p 400p 10M 300p 1.8 V 95 MHz 1M 200p 100p 0.4 V 73 khz 0.8 V 17 MHz 100k 0.5 V 0 1 MHz 10k V DD, V University of Michigan 31 31

32 Energy per Inst, J Frequency, Hz Processor Performance vs. Energy M 500p 400p 10M 300p 1.8 V 95 MHz 1M 200p 100p 0.4 V 73 khz 0.8 V 17 MHz 100k 0.5 V 0 1 MHz 10k V DD, V University of Michigan 32 32

33 Energy per Instruction, J Energy Supplied by PMU 33 90p 80p 70p 60p 50p 40p 30p 20p 10p 0 Total Energy Leakage Dynamic Minimum Energy Operating Point 0.5 V, 37 pj 0.4 V, 28 pj 0.6 V, 54 pj V DD, V University of Michigan 33 33

34 Power, W Power, W Power Supplied by PMU 34 10n 1n 100p 0.4 V 100 pw Total R-SRAM 0.5 V 230 pw 0.6 V 680 pw V DD, V Power at 400mV 1 100n 10n 100p R-SRAM 80.53% 1n Timer 19.46% Cortex-M3 < 0.01% NR-SRAM < 0.01% 35 pw 1 W 13 nw 100 pw Phoenix JSSC'09 Kwong JSSC '09 Warneke ISSCC '04 University of Michigan p This Work

35 V BATT, V I BATT, A Nearly-Perpetual Operation Active Active Time, s University of Michigan 35 35

36 Measurements per Day Nearly-Perpetual Usage Model 36 16k 14k 12k 10k 8k Bright Indoor 1 per 4 mins Cloudy 3 per minute Sunny 10 per minute 6k 4k 2k 0 1 measurement requires 10k instructions Light, suns AM 1.5 Mode Harvesting Lifetime One measurement every hour No 5 years Idle lifetime No 49 years Up to10 measurements per minute Yes Nearly-infinite University of Michigan 36 36

37 Summary 37 Small sensors and long lifetimes create new applications in medical, infrastructure and environmental monitoring Size constrains on-sensor energy storage and average power for desired lifetime Multi-year lifetime requires sub-nanowatt power consumption Near-threshold processing Low-leakage SRAM mode power management Energy harvesting enables nearly-perpetual operation University of Michigan 37 37

38 38 Thank You University of Michigan 38 38