3D Technologies For Low Power Integrated Circuits

Transcription

1 3D Technologies For Low Power Integrated Circuits Paul Franzon North Carolina State University Raleigh, NC

2 Outline 3DIC Technology Set Approaches to 3D Specific Power Minimization Comparative energy/operations Leverage Rent s Rule? The low-hanging fruit : Energy-optimized memory interfaces 3D-specific architectures Next: Heterogenous Integration CAD approaches to 3D optimization 2

3 3DIC Technology Set Bulk Silicon TSVs and bumps (25-40 m pitch) Face to face microbumps (2-30 m pitch) C TSV ~ 30 ff Tezzaron 3

4 3DIC Technology Set TSVs in an SOI process Tier-3 Transistor Layers 3D Via RF Back Metal Cvia ~ 0.4 ff Oxide Bond Interface Tier-2 3D Via Tier-1 Tier-1 Transistor Layer 20 m MIT Lincoln Labs 4

5 3DIC Technology Set Interposers: Thin film or 65/90 nm BEOL Assembly : Chip to Wafer or Wafer to wafer 5

6 Outline 3DIC Technology Set Approaches to 3D Specific Power Minimization Comparative energy/operations Is leveraging Rent s Rule enough? Energy-optimized memory interfaces 3D-specific architectures Heterogeneous Integration CAD approaches to 3D optimization 6

7 Energy per Operation DDR3 4.8 nj/word Optimized DRAM core 128 pj/word MIPS 64 core 400 pj/cycle 11 nm 0.4 V core 200 pj/op 45 nm 0.8 V FPU 38 pj/op SERDES I/O 1.9 nj/word 20 mv I/O 128 pj/word LPDDR2 512 pj/word 1 cm on interposer 300 pj/word On-chip/mm 7 pj/word TSV I/O (ESD) 7 pj/word TSV I/O (no ESD) 2 pj/word (64 bit words) Various Sources 7

8 Wire Power Reduction Exemplar power distribution FFT Processor 8

9 Shorter wires Modest Returns Relying on wire-length reduction alone is not enough 2D Design 0.13 m Cell Placement split across 6.6 m face-to-face bump structure Results get less compelling with technology scaling, as the microbumps don t scale 9

10 Memory on Logic Conventional TSV Enabled Less Overhead Flexible bank access nvidea x32 to x128 or Less interface power 3.2 >10 pj/bit pj/bit Flexible architecture Short wires Exploit dense face-to-face or Mobile N x 128 wide I/O Processor & SRAM 10

11 Mobile Graphics Problem: Want more graphics capacity but total power is constrained Solution: Trade power in memory interface with power to spend on computation POP with LPDDR2 LPDDR2 TSV IO TSV Enabled Power Consumption GPU Power Consumption GPU 532 M triangles/s 695 M triangles/s Won Ha Choi 11

12 Synthetic Aperture Radar Processor Built FFT in Lincoln Labs 3D Process Metric Undivided Divided % Bandwidth (GBps) Energy Per Write(pJ) Energy Per Read (pj) Memory Pins (#) Total Area (mm 2 ) % Thor Thorolfsson 12

13 3D FFT Floorplan All communications is vertical Support multiple small memories WITHOUT an interconnect penalty AND Gives 60% memory power savings Thor Thorolfsson 13

14 RePartition FFT to Exploit Locality Every partition is a PE Every unique intersection is a memory 14

15 2DIC vs. 3DIC Implementation vs. Metric 2D 3D Change Total Area (mm 2 ) % Total Wire Length (m) % Max Speed (Mhz) % 63.7MHz (mw) % FFT Logic Energy (µj) % Thor Thorolfsson 15

16 Memory bank size tradeoffs E.g. 32 x 2 kbit SRAM 10x less energy/bit than 1 x 64 kbit SRAM With 17% increase in area (partially recoverable by in 3D) 16

17 Tezzaron SAR Processor Metric Total Wire length (mm) Max. Frequency (MHz) Max Performance (MFlops) Parasitic Power (mw) Logic Power (mw) Memory Power (W) 2D 3D mpl 3D % % % % % % % % % % % Thor Thorolfsson 17

18 Next level of Exploitation Key: Architecture Optimized for 3D Exploitation Heterogeneous Integration (different voltages, processes) Power optimization without compromise Heterogeneous Memory - Energy optimized algorithmic approach 18

19 3D Miniaturization Miniature Sensors Focii mm 3 scale - Human Implantable (with Jan Rabaey, UC(B)) cm 3 scale - Food Safety & Agriculture (with KP Sandeep, NCSU) System Design Right sizing power harvesting for application Problems: Maximizing RF power harvesting potential Technology integration MEMS, Energy storage, passives in true 3D Peter Gadfort, Akalu Lentiro, Steve Lipa 19

20 Outline 3DIC Technology Set Approaches to 3D Specific Power Minimization Comparative energy/operations Leverage Rent s Rule? The low-hanging fruit : Energy-optimized memory interfaces 3D-specific architectures Next: Heterogenous Integration CAD approaches to 3D optimization 21

21 SystemC Methodology for Pathfinding User configuration Power Library ISA mode ISA Library Reference for control Commands Arch. setup, Execution control Power Manager Power Model (TLM) Unit energy, TSV constants 1. Logic: command processor, streamer, etc 2. Memory 3. Power Tracker Simulation results Update TSV constants Update virtual coord. 1. Stores power information 2. Generates pre-placement related information 3. Update virtual coordinates and TSV constants Won Ha Choi 22

22 Thermal and Physical Flow: Comprehensive technology file Resolution of simulation: Grid Size PETSC: Sparse Matrix Solver Thermal MNAM Composite technology file WireX: Thermal Extractor Power vector Textual Floor plan Power Hotspot only Transient Simulator e.g. HSPICE/fREEDA Static Thermal Profile Transient Thermal Profile Shivam Priyadashi23

23 Conclusions Getting Power Advantages from 3DIC: Method Logic-on-logic shorter wires Exploiting DRAM on logic as a low power interface Architecting System for Vertical Spatial Locality Trade area for power Exploiting Heterogenity 15%+ (??) Advantages 2% - 13% power improvement 30% improvement if application (mostly) fits in stacked DRAM Varies. 5% to 60% (?) Up to 20% at system level, when done from memories 25

24 Acknowledgements Faculty: William Rhett Davis, Michael B. Steer, Professionals: Steven Lipa, Neil DiSpigna, Students: Hua Hao, Samson Melamed, Peter Gadfort, Akalu Lentiro, Shivam Priyadarshi, Christopher Mineo, Julie Oh, Won Ha Choi, Zhou Yang, Ambirish Sule, Gary Charles, Thor Thorolfsson, Department of Electrical and Computer Engineering NC State University 26