Process and Design Solutions for Exploiting FD SOI Technology Towards Energy Efficient SOCs

Transcription

1 Process and Design Solutions for Exploiting FD SOI Technology Towards Energy Efficient SOCs Philippe FLATRESSE Technology R&D Central CAD & Design Solutions STMicroelectronics International Symposium on Low Power Electronics and Design

2 28nm Planar UTBB FD-SOI Transistor 2 High-K Metal Gate Thin Body (7nm) Substrate Ultra Thin Body & BOX Fully Depleted SOI transistor 2

3 28nm Planar UTBB FD-SOI Advantages 3 24nm Body-Bias Hybrid zone Shorter channel length 24nm technology! Better electrostatics Faster operation Low voltage Reduced variability Total dielectric isolation Latch up immunity Lower leakage current Less sensitive to temperature 3

4 Body Biasing (BB) A very reasonable effort for extremely worthwhile benefits An extremely powerful and flexible concept in FD-SOI to : Boost performance Optimize passive and dynamic power consumption Cancel out process variations and extract optimal behavior from all parts 0 1.3V Comparatively easy to implement if you ve ever done DVFS you ll have no difficulty with Body Biasing No area penalty compared to Bulk Reuse of Bulk design techniques Speed/Power control 4

5 Extended Body Bias Range in UTBB FD-SOI NMOS PMOS I PN (FBB) I GIDL (RBB) BULK UTBB FD-SOI -300mV +300mV -3V +3V RBB FBB nobb RBB nobb FBB 5

6 UTBB FD-SOI: Extended Body Voltage Range Conventional Well (CW) - RBB Gndsn NMOS PMOS Vddsp -3V nobb +3V 6 p-well n-well Flip Well (FW) - FBB RBB FBB Vdd/2+ 300mV Gndsn NMOS PMOS Gndsp -3V nobb +3V RBB FBB n-well p-well -300mV Efficient knob for speed/leakage optimization 6

7 Body Bias Efficiency - Silicon Evidence FBB RBB 7

8 FBB usage per market segment Infrastructure - Networking Servers and Storage Consumer Internet of Things µap Ultra-Low-Energy Configuration Supply: V high number multicore DVFS & FBB tuning for best MIPS/W ratio. Adapt perf&power to workload Supply: V Wide DVFS FBB linked to CPU workload & thermal conditions Supply: 0.6V-0.9V FBB: 0-1.5V FBB to solve the power/performance paradigm Ultra Low Voltage 0.3V- 0.4V Reverse Body Biasing Power efficiency Flexibility Perf/Power Ultra power efficiency 28 FD-SOI: Up to -50% total power reduction versus 0.6V FBB for ultimate power efficiency tuning 28 FD-SOI: Up to -50% power reduction FBB provides +18% max. performance boost versus 28G(mobile) 28 FD-SOI: Up to x 4 perf/power ratio versus 28G(mobile) at low voltage Low voltage power efficient performance. Reduce idle current 8

9 Improved Memory Minimum Voltage Vddmin on 0.120µm² bitcell Probability (%) Vddmin -100mV Vddmin 28FDSOI Vddmin 28LP Vnom A Vt (mv.µm) 3 2,5 2 1,5 Mismatch -40% on FDSOI vs. LP Vddmin (V) 1 Pass Gate Pull Down Pass Gate Pull Down Vmin gain thanks to better mismatch on FD-SOI devices (undoped channel) 9

10 FD-SOI Unique Single Well Architecture 10 SRAM regular wells p-well nfet RVT pfet LVT ST patented bitcell architecture SRAM flip-well architecture Single Well SRAM Optimized stability helping behavior at low voltage Probability (%) SRAM single well regular wells single well Vddmin -70mV Power efficiency 0 0,4 0,45 0,5 0,55 0,6 Vddmin (V) 10

11 Si Evidence: LDPC on UTBB FD-SOI Frequency (MHz) UTBB FD-SOI 0.35V +168 % 100 BULK-LP (ref) 0 0,3 0,5 0,7 0,9 1,1 1,3 1,5 Vdd (V) +73% +46% FBB=1V nobb FBB=0.3V LDPC 6T-SRAM (FBB 1V) functional down to 0.41V 2013 IEEE - International Solid-State Circuits Conference Ultra-Wide Body-Bias Range LDPC Decoder in 28nm UTBB FD-SOI 11

12 State of the Art UWVR DSP in FDSOI: 2014 IEEE - International Solid-State Circuits Conference 27.1 : A 460MHz@397mV 2.6GHz@1.3V 32bit VLIW DSP 12

13 Cortex A9: FD-SOI allowing Ultra-Wide DVFS FD-SOI allows the widest Vdd range for voltage scaling 3 CPU freq. (GHz) 3.0 GHz at 1.34V Still guaranteeing top notch speeds at very low operating voltage >5x when compared to 28LP technology >35% when compared to 28G technologies GHz at 1.0V 1 GHz at 0.61V DVFS energy efficiency optimization is further extended thanks to body bias Allowing to balance and optimize the static and dynamic power consumption components 300 MHz at 0.5V CPU supply (V) 13

14 Cortex A9 Power vs. Performances Total Power (mw) A9 Single Dhrystone power consumption 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 28nm-bulk Pow 28nm-FD-SOI Pow 28nm-FD-SOI FBB Pow Gain Gain FBB 0 ARM 0.8GHz ARM 1.2GHz ARM 1.5GHz ARM 1.85GHz ARM 2.0GHz ARM 2.3GHz 0%

15 28nm FD-SOI Best in class efficiency 140% 120% +43% vs low Vdd +83% vs 28G 100% Energy efficiency (relative DMIPS/mW) 80% 60% +50% vs high Vdd +25% vs 28G 40% 20% 0% 20% 40% 60% 80% 100% 120% low Vdd Speed (relative highvdd (overdrive) 15

16 Faster, Cooler, Simpler technology FD-SOI transistors up to 30% faster than bulk Outstanding power efficiency at every level Extensive use of existing fab infrastructure Enhanced design options Back-biasing as a flexible and powerful optimization Very large operating range for the same design Ultra-wide range DVFS Mature process & ecosystem Ecosystem ready at all stage: wafer supply, design and manufacturing Extended IP offer Strategic collaboration between Samsung and ST gives your SOC competitive advantages 16