CPU Design Tradeoffs. Building the Beta. Performance Measure. The Beta ISA MIPS = C.P.I. Clock Frequency (MHz) PUSHING PERFORMANCE...

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1 uilding the eta CPU esign Tradeoffs I wonder where this goes? Maximum Performance: measured by the numbers of instructions executed per second Minimum Cost : measured by the size of the circuit. Lab #5 due Thursday Quiz #3 Friday est Performance/Price: measured by the ratio of MIPS to size. In power-sensitive applications MIPS/Watt is important too. L4 uilding a eta L4 uilding a eta 2 Performance Measure 6 OpCode The eta IS Millions of s per Second MIPS = Clock Frequency (MHz) C.P.I. X X X X Rb (UNUSE) Operate class: Reg[]! Reg[] op Reg[Rb] 6 X X X X Operate class: Reg[]! Reg[] op SXT(C) classes distinguished by OOE: O MEM Transfer of Control PUSHING PERFORMNCE... Clocks per instruction Opcodes, both formats: SU MUL* IV* *optional CMPEQ CMPLE CMPLT N OR XOR SHL SHR SR X X X X TOY: cycle/inst. LTER: more MHz via pipelining L4 uilding a eta 3 L: Reg[]! Mem[Reg[]SXT(C)] ST: Mem[Reg[]SXT(C)]! Reg[] JMP: Reg[]! ;! Reg[] EQ: NE: LR: Reg[]! Mem[ 4 4*SXT(C)] Reg[]! ; if Reg[]= then! *SXT(C) Reg[]! ; if Reg[]" then! *SXT(C) L4 uilding a eta 4

2 pproach: Incremental Featurism Multi-Port s Each instruction class can be implemented using a simple component repertoire. We ll try implementing data paths for each class individually, and merge them (using MUXes, etc). Steps:. Operate instructions 2. Load & Store s 3. Jump & ranch instructions 4. Exceptions 5. Merge data paths Our ag of Components: W R R s Muxes LU R2 (3-port) R2 lack box LU Memories R R/W ata dest clk asel Read Port ite Port Read Port clk s Q Q bsel ite ddress ite Enable ite ata CLK 5 (independent Read addresses) W R 5 5 R R2 (3-port) R2 (Independent Read ata) 2 combinational RE ports*, clocked WRITE port *internal logic ensures Reg[3] reads as L4 uilding a eta 5 L4 uilding a eta 6 Timing Starting point: LU Ops 2 combinational RE ports, clocked WRITE port -bit (4-byte) instruction: R R Reg[] new Reg[] OpCode Rb (unused) CLK t P t P Means, to ET, Reg[R4]! Reg[R2] Reg[R3] W new Reg[] What if (say) W=R??? R reads old value of Reg[R] until next clock edge! t S t h First, we ll need hardware to: Read next -bit instruction ECOE instruction:, SU, XOR, etc RE operands (, Rb) from ; PERFORM indicated operation; WRITE result back into (). L4 uilding a eta 7 L4 uilding a eta 8

3 Fetch/ecode LU Op ata Path! Use a counter to FETCH the next instruction: PROGRM COUNTER () OOE <3:26> INSTRUCTION WOR FIELS CONTROL SIGNLS! use as memory address! add 4 to, load new value at end of cycle! fetch instruction from memory º use some instruction fields directly (register numbers, 6-bit constant) º use bits <3:26> to generate controls LUFN X X X X : <25:2> : <2:6> LUFN W R R Rb (UNUSE) Operate class: Reg[]! Reg[] op Reg[Rb] Rb: <5:> LU R2 R2! L4 uilding a eta 9 L4 uilding a eta LU Operations (w/constant) Load X X X X Operate class: Reg[]! Reg[] op SXT(C) L: Reg[]! Mem[Reg[]SXT(C)] : <2:6> Rb: <5:> : <2:6> Rb: <5:> : <25:2> R W W R R2 R2 : <25:2> R W W R R2 R2 C: SXT(<5:>) C: SXT(<5:>) LUFN LUFN LU SEL LUFN LUFN LU R/W ata dr R 2 SEL L4 uilding a eta L4 uilding a eta 2

4 Store JMP ST: Mem[Reg[]SXT(C)]! Reg[] 2 SEL 4 3 JMP: Reg[]! ;! Reg[] : <2:6> : <25:2> C: SXT(<5:>) R W W R Rb: <5:> : <25:2> R2SEL R2 R2 No! : <25:2> : <2:6> C: SXT(<5:>) R W W R Rb: <5:> : <25:2> R2SEL R2 R2 R2SEL SEL LUFN LUFN LU R/W ata dr R SEL R2SEL SEL LUFN LUFN LU R/W ata dr R 2 SEL 2 SEL L4 uilding a eta 3 L4 uilding a eta 4 SEL EQ/NE s *SXT(C) 4*SXT(<5:>) SEL R2SEL SEL LUFN : <25:2> : <2:6> C: SXT(<5:>) LUFN EQ: Reg[]! ; if Reg[]= then! *SXT(C) NE: R W W R Rb: <5:> LU 2 Reg[]! ; if Reg[]" then! *SXT(C) SEL R2 R2 : <25:2> R2SEL R/W ata dr R Load Relative Hey, WIT MINUTE. What s Load Relative good for anyway??? I thought Code is PURE, i.e. RE-ONLY; and stored in a PROGRM region of memory; ata is RE-WRITE, and stored either On the STCK (local); or In some GLOL VRILE region; or In a global storage HEP. LR: So why an instruction designed to load data that s near the instruction??? ddresses & other large constants Reg[]! Mem[ 4 4*SXT(C)] C: X = X * 23456; ET: L(X, r) LR(c, r) MUL(r, r, r) ST(r, X)... c: LONG(23456) L4 uilding a eta 5 L4 uilding a eta 6

5 SEL IF LR *SXT(C) SEL R2SEL SEL SEL LUFN LR: Reg[]! Mem[ 4 4*SXT(C)] : <25:2> : <2:6> C:SXT( <5:>) R W W SEL LUFN R Rb: <5:> : <25:2> R2SEL LU 2 SEL R2 R2 R/W ata dr R Exceptions What if something happens?! Execution of an illegal op-code! Reference to non-existent memory! ivide by zero Or, maybe, just something unanticipated! User hits a key! packet comes in via the network GOL: handle all these cases (and more) in SOFTWRE:! Treat each such case as an (implicit) procedure call! Procedure handles problem, returns to interrupted program.! TRNSPRT to interrupted program!! Important added capability: handlers for certain errors (illegal opcodes) can extend instruction set using software (Lab 7!). L4 uilding a eta 7 L4 uilding a eta 8 Exception Processing Plan:! Interrupt running program! Invoke exception handler (like a procedure call)! Return to continue execution. Implementation How exceptions work:! on t execute current instruction! Instead fake a forced procedure call! save current (actually current 4)! load with exception vector! x4 for synch. exception, x8 for asynch. exceptions We d like RECOVERLE INTERRUPTS for Synchronous events, generated by CPU or system FULTS (eg, Illegal, divide-by-, illegal mem address) TRPS & system calls (eg, read-a-character) synchronous events, generated by I/O (eg, key struck, packet received, disk transfer complete) KEY: TRNSPRCY to interrupted program.! Most difficult for asynchronous interrupts Question: where to save current 4?! Our approach: reserve a register (R3, aka XP)! Prohibit user programs from using XP. Why? Example: IV unimplemented L(R3,,R) L(R3,,R) IV(R,R,R2) ST(R2,C,R3) Forced by hardware IllOp: PUSH(XP) Fetch inst. at Mem[Reg[XP] 4] check for IV opcode, get reg numbers perform operation in SW, fill result reg P(XP) JMP(XP) L4 uilding a eta 9 L4 uilding a eta 2

6 Xdr ILL Exceptions SEL ad Opcode: Reg[XP]! ;! IllOp Other: Reg[XP]! ;! Xadr *SXT(C) IRQ SEL R2SEL SEL SEL LUFN WSEL XP : <25:2> : <2:6> WSEL C: SXT(<5:>) W W SEL LUFN R R Rb: <5:> : <25:2> R2SEL LU 2 W S E L R2 R2 ata dr W E R F R R/W O L ST JMP LUFN F(op) F(op) "" "" "" SEL WR R2SEL SEL 2? :? : 3 4 SEL WSEL -- EQ NE Implementation choices:! ROM indexed by opcode, external branch & trap logic! PL! random logic (eg, standard cell gates) LR Illop IRQ L4 uilding a eta 2 L4 uilding a eta 22 Xdr ILL eta: Our Final nswer Next Time: Tackling the ottleneck SEL *SXT(C) IRQ XP : <25:2> : <2:6> WSEL C: SXT(<5:>) R W W R Rb: <5:> : <25:2> R2SEL R2 R2 W E R F Is that all there is to building a processor??? No. You ve gotta print up all those little eta Inside stickers. SEL SEL R2SEL SEL SEL LUFN WSEL LUFN LU R/W ata dr R 2 W S E L L4 uilding a eta 23 L4 uilding a eta 24