Building the Beta. Handouts: Lecture Slides, PS 7, Lab 6. I wonder where this goes? Spring /5/01. L15- Building the Beta 1 A B

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1 Building the Beta I wonder where this goes? B LU Beta Kit 0 1 Instruction Handouts: Lecture Slides, PS 7, Lab 6 L15- Building the Beta 1

2 CPU esign Tradeoffs Maximum Performance: measured by the numbers of instructions executed per second Minimum Cost : measured by the size of the circuit. Best Performance/Price: measured by the ratio of MIPS to size. In power-sensitive applications MIPS/Watt is important too. L15- Building the Beta 2

3 Performance Measure Millions of Instructions per Second MIPS = Clock Frequency (MHz) C.P.I. Clocks per instruction PUSHING PERFORMNCE... TOY: 1 cycle/inst. NEXT TIME: more MHz via pipelining NEXT NEXT TIME: fixing various pipelining issues L15- Building the Beta 3

4 The Beta IS OPCOE 10x x x x Rc Ra Rb (unused) Operate class: Reg[Rc] Reg[Ra] op Reg[Rb] 1 1 xxxx Rc Ra literal C (signed) 01x x x x Operate class: Reg[Rc] Reg[Ra] op SXT(C) Opcodes, both formats: SUB MUL* IV* *optional CMPEQ CMPLE CMPLT N OR XOR SHL SHR SR Rc Ra literal C (signed) Instruction Instruction classes classes distinguished distinguished by by OPCOE: OPCOE: OP OP OPC OPC MEM MEM Transfer Transfer of of Control Control L: ST: JMP: BEQ: BNE: LR: Reg[Rc] Mem[Reg[Ra]+SXT(C)] Mem[Reg[Ra]+SXT(C)] Reg[Rc] Reg[Rc] PC+4; PC Reg[Ra] Reg[Rc] PC+4; if Reg[Ra]=0 then PC PC+4+4*SXT(C) Reg[Rc] PC+4; if Reg[Ra] 0 then PC PC+4+4*SXT(C) Reg[Rc] Mem[PC *SXT(C)] L15- Building the Beta 4

5 pproach: Incremental Featurism Each instruction class can be implemented using a simple component repertoire. We ll try implementing data paths for each class individually, and merge them (using MUXes, etc). Steps: 1. Operate instructions 2. Load & Store Instructions 3. Jump & Branch instructions 4. Exceptions 5. Merge data paths Our Bag of Components: Registers 0 1 Muxes LU B Black box LU R1 R2 W WE W Register File (3-port) Instruction W R R/W ata R1 R2 Memories L15- Building the Beta 5

6 Multi-Port Register Files ite Port (independent Read addresses) 5 5 dest clk EN EN EN EN ite ddress ite Enable ite ata 5 32 W WE W R1 R2 Register File (3-port) asel bsel CLK R1 R Read Port Read Port B (Independent Read ata) EN s combinational RE ports*, 1 clocked WRITE port clk Q *internal logic ensures Reg[31] reads as 0 Q L15- Building the Beta 6

7 Register File Timing 2 combinational RE ports, 1 clocked WRITE port R R Reg[] new Reg[] t P t P CLK WE W W new Reg[] What if (say) W=R1??? R1 reads old value of Reg[R1] until next clock edge! t S t h L15- Building the Beta 7

8 Starting point: LU Ops 32-bit (4-byte) instruction: OpCode Rc Ra Rb (unused) Means, to BET, Reg[R4] Reg[R2] + Reg[R3] First, we ll need hardware to: Read next 32-bit instruction ECOE instruction:, SUB, XOR, etc RE operands (Ra, Rb) from Register File; PERFORM indicated operation; WRITE result back into Register File (Rc). L15- Building the Beta 8

9 Instruction Fetch/ecode Use a counter to FETCH the next instruction: PROGRM COUNTER (PC) PC Instruction 32 OPCOE <31:26> Control Logic INSTRUCTION WOR FIELS use PC as memory address add 4 to PC, load new value at end of cycle fetch instruction from memory º use some instruction fields directly (register numbers, 16-bit constant) º use bits <31:26> to generate controls CONTROL SIGNLS L15- Building the Beta 9

10 LU Op ata Path PC 00 10XXXX Rc Ra Rb unused Instruction OP: Reg[Rc] Reg[Ra] op Reg[Rb] +4 Ra: <20:16> Rb: <15:11> W R1 R1 Register File R2 R2 W WE Control Logic LUFN LU B! LUFN 32 L15- Building the Beta 10

11 LU Operations (w/constant) 11XXXX Rc Ra literal C (signed) PC OPC: Reg[Rc] Reg[Ra] op SXT(C) Instruction Ra: <20:16> Rb: <15:11> R1 W W R1 Register File R2 R2 W WE C: SXT(<15:0>) 32 Control Logic 1 0 LUFN LU B LUFN L15- Building the Beta 11

12 Load Instruction Rc Ra literal C (signed) PC 00 L: Reg[Rc] Mem[Reg[Ra]+SXT(C)] Instruction +4 Ra: <20:16> Rb: <15:11> R1 W W R1 Register File R2 R2 W WE C: SXT(<15:0>) Control Logic 1 0 WSEL LUFN LUFN LU B 32 ata dr R W R/W WSEL L15- Building the Beta 12

13 Store Instruction PC 00 Instruction ST: Rc Ra literal C (signed) Mem[Reg[Ra]+SXT(C)] Reg[Rc] +4 Ra: <20:16> Rb: <15:11> 0 1 R2SEL R1 W W R1 Register File R2 R2 W WE C: SXT(<15:0>) Control Logic R2SEL WSEL LUFN LUFN LU B ata dr R W R/W WSEL L15- Building the Beta 13

14 JMP Instruction JT PCSEL Rc Ra literal C (signed) PC 00 JMP: Reg[Rc] PC+4; PC Reg[Ra] Instruction +4 Ra: <20:16> Rb: <15:11> 0 1 R2SEL R1 W W R1 Register File R2 R2 W WE C: SXT(<15:0>) JT Control Logic 1 0 PCSEL R2SEL WSEL LUFN LUFN LU B ata dr R W R/W PC WSEL L15- Building the Beta 14

15 BEQ/BNE Instructions JT Rc Ra literal C (signed) PCSEL BEQ: Reg[Rc] PC+4; if Reg[Ra]=0 then PC PC+4+4*SXT(C) PC 00 Instruction BNE: Rc Ra literal C (signed) Reg[Rc] PC+4; if Reg[Ra] 0 then PC PC+4+4*SXT(C) +4 PC+4+4*SXT(C) + 4*SXT(<15:0>) Ra: <20:16> Z R1 W W R1 Rb: <15:11> JT Register File 0 1 R2 R2 R2SEL W WE No! Z C: SXT(<15:0>) 1 0 Control Logic PCSEL R2SEL WSEL LUFN LUFN LU B ata dr R W R/W PC WSEL L15- Building the Beta 15

16 Load Relative Instruction LR: Rc Ra literal C (signed) Reg[Rc] Mem[PC *SXT(C)] Hey, WIT MINUTE. What s Load Relative good for anyway??? I thought Code is PURE, i.e. RE-ONLY; and stored in a PROGRM region of memory; ata is RE-WRITE, and stored either On the STCK (local); or In some GLOBL VRIBLE region; or In a global storage HEP. So why an instruction designed to load data that s near the instruction??? ddresses & other large constants C: C: X X = = X X * * ; ; BET: BET: L(X, L(X, r0) r0) LR(c1, LR(c1, r1) r1) MUL(r0, MUL(r0, r1, r1, r0) r0) ST(r0, ST(r0, X) X) c1: c1: LONG(123456) LONG(123456) L15- Building the Beta 16

17 LR Instruction JT PCSEL Rc Ra literal C (signed) PC IF 00 LR: Reg[Rc] Mem[PC *SXT(C)] Instruction +4 + PC+4+4*SXT(C) Z Control Logic Ra: <20:16> Z C:SXT( <15:0>) R1 W W SEL 1 0 R1 JT Rb: <15:11> Register File R2 R2 0 R2SEL W WE PCSEL R2SEL SEL WSEL LUFN LUFN LU B ata dr R W R/W PC WSEL L15- Building the Beta 17

18 Exception Processing We d like RECOVERBLE INTERRUPTS for FULTS (eg, Illegal Instruction) - CPU or SYSTEM generated [synchronous] TRPS & system calls (eg, read-a-character) - CPU generated [synchronous] I/O events (eg, key struck) - externally generated [asynchronous] GOL: Interrupt running program, invoke exception handler (like a procedure call), return to continue execution. KEY: TRNSPRENCY to interrupted program. Most difficult for asynchronous interrupts L15- Building the Beta 18

19 Implementation IMPLEMENTTION: FORCE procedure call: new PC, save old PC for return. but WHERE to save old PC? Use LP? don t execute current instruction PPROCH: nother reserved register, XP (aka R30). Why can t interrupted program use XP? Example: IV unimplemented L(R31,,R0) L(R31,B,R1) IV(R0,R1,R2) ST(R2,C,R31) Forced by hardware IllOp: PUSH(XP) Fetch inst. at Mem[Reg[XP] 4] check for IV opcode, get reg numbers perform operation in SW, fill result reg POP(XP) JMP(XP) L15- Building the Beta 19

20 Xdr ILL OP JT Exceptions PCSEL PC Bad Opcode: Reg[XP] PC+4; PC IllOp 00 Other: Reg[XP] PC+4; PC Xadr 0 Instruction +4 + PC+4+4*SXT(C) IRQ Z Control Logic XP 1 0 Ra: <20:16> WSEL Z C: SXT(<15:0>) W W SEL 1 0 R1 R1 JT Rb: <15:11> Register File R2 R2 0 R2SEL W WE PCSEL R2SEL SEL WSEL LUFN WSEL LUFN PC+4 LU B ata dr R W R/W WSEL L15- Building the Beta 20

21 Control Logic OP OPC L ST JMP BEQ BNE LR Illop trap LUFN F(op) F(op) WSEL WR R2SEL 0 1 PCSEL Z? 1 : 0 Z? 0 : SEL WSEL Implementation choices: ROM indexed by opcode, external branch & trap logic PL random logic (eg, standard cell gates) L15- Building the Beta 21

22 Beta: Our Final nswer Xdr ILL OP JT PCSEL PC 00 Instruction +4 + PC+4+4*SXT(C) IRQ Z Control Logic XP 1 0 Ra: <20:16> WSEL Z C: SXT(<15:0>) W W SEL 1 0 R1 R1 JT Rb: <15:11> Register File R2 R2 0 R2SEL W WE PCSEL R2SEL SEL WSEL LUFN WSEL LUFN PC+4 LU B ata dr R W R/W WSEL L15- Building the Beta 22

23 Next Time: Pipelined Betas Hey, building a computer is not really all that difficult So let s run down to the lab and put Intel out of business! L15- Building the Beta 23