Block 1: ZYNQ-7000 Architecture. Objectives:

Transcription

1 Blck 1: ZYNQ-7000 Architecture Describe the architecture and cmpnents that cmprise the Zynq All Prgrammable SC prcessing system (PS) Relate a user design gal t the functin, benefit, and use f the Zynq All Prgrammable SC Effectively select and design an interface between the Zynq PS and prgrammable lgic (PL) that meets prject gals Analyze the tradeffs and advantages f perfrming a functin in sftware versus PL Describe the AXI intercnnect t the prgrammable lgic (PL) Identify basic mdes f device cnfiguratin List the input/utput peripherals (IOPs) that are available in the prcessing system Describe the difference between multiplexed I/O (MIO) and extended MIO (EMIO) usage Describe the bt sequence f the Zynq device Describe the difference between secure and nn-secure bt mdes List the memry cntrllers that are available in the PS Discuss the decisin-making prcess between prgrammable lgic and sftware architectures Zynq All Prgrammable SC Overview Prcessr with Prgrammable Lgic Applicatin Prcessing Unit (APU) Input/Output Peripherals (IOP) Datapath and Memry Prgrammable Lgic (PL) Inside the Applicatin Prcessr Unit (APU) APU Cmpnents Crtex-A9 Prcessr Overview NEON/FPU Cprcessr PS Memry and Cache Resurces Snp Cntrl Unit System-Level Cntrl Registers Timers and Mre Timers 1

2 General Interrupt Cntrller (GIC) DMA Prcessr Input-Output Peripherals Prcessr Peripheral Overview GPIO I2C UART CAN SPI SD/SDIO USB Ethernet Intrductin t AXI What is AXI? Variatins f AXI AXI Transactins Zynq All Prgrammable SC PS-PL Interface PS-PL Interface Overview Intercnnects in the PS AXI Master Interfaces AXI Slave Interfaces AXI ACP Interface Zynq All Prgrammable SC Bting Cnfiguratin Sequence Overview Sftware Bt PL Cnfiguratin Device Cnfiguratin Interface Typical Use Cases Zynq All Prgrammable SC Memry Resurces Memry Resurces Overview On-Chip Memry (OCM) Static Memry Cntrller (SMC) DDRx Memry Cntrller (DMC) Linear Quad SPI Flash Cntrller (QSPI) Blck RAM Prgrammable Lgic t Memry 2

3 Blck 2: Embedded Design Flw Describe the majr sub-blcks f a Zynq All Prgrammable SC prcessr system Enumerate the key aspects f the Zynq All Prgrammable SC prcessing system List sme f the peripherals available in the Vivad IP catalg Describe the embedded design flw Shw hw the hardware and sftware design envirnments are linked Cnstruct a simple embedded design using the IP Integratr (IPI) tl Lcate prcessr IP and add prcessrs t an IPI sub-system Cnfigure the prcessr IP f an embedded design Identify the IP available fr an embedded system design Describe hw t add hardware t an existing IP integratr (IPI) blck diagram Use the IPI wrkspace view t cnstruct and mdify a design Explain hw the varius blck design's cmpnents are cnfigured Discuss hw memry can be cnstructed within the IP integratr wrkspace Embedded Design Overview Embedded Prcessr Cmpnent Overview f Embedded Develpment Embedded Develpment Design Flw SDK Sftware Platfrm Management IP Integratr and the PS Cnfiguratin Wizard Starting Out Building a System with IP Integratr Re-Custmizing the Zynq All Prgrammable SC PS Adding Hardware t an Embedded System Embedded System Tls and Prducts IP Delivery in the Vivad Design Suite Adding Hardware with IP Integratr Blck Memry Usage 3

4 Hardware Aspects f the Interruptsystem in the Zynq device Need Yur Attentin Interrupts in the Crtex-A9 Prcessr Interrupt Cntrller Interrupt Inclusin Labs: 1. Hardware Cnstructin Using the Vivad IP Integratr 2. Adding and Dwnlading Sftware 3. Adding IP t a Hardware Design 4

5 Blck 3: Embedded Sftware Develpment Implement an effective sftware design envirnment fr a Xilinx embedded system using the Xilinx SDK tls Write a basic user applicatin (under Standalne) using the Xilinx Sftware Develpment Kit (SDK) and run it n an embedded system platfrm Examine the Xilinx libraries fr required services and features Use a bard supprt package (BSP) t access system services frm the sftware applicatin Determine whether yur embedded system applicatin requires a standalne system r an perating system List the cntents f a BSP Explain the difference between level 0 and level 1 sftware drivers Write and cmpile an errr free prgram Dwnlad and execute a prgram Use SDK sftware and errr navigatin features Identify the cntent, functinality, and use f the mre ppular system services in the Standalne Sftware Platfrm Describe the address space f the Crtex -A9 prcessrs Describe the interrupt structure f the Crtex -A9 prcessr Register the interrupt handler/interrupt service rutine (ISR) Describe the Xilinx device driver implementatin standard Standalne Sftware Platfrm Develpment Overview Libraries Prcessr Services Device Drivers Standalne Bard Supprt Package Sftware Develpment Using SDK Overview SDK: Sftware Develpment Kit 5

6 Eclipse IDE SDK Help SDK Prject Creatin SDK Prject Optins SDK Run Optins Writing Sftware and Cmpiling Writing Cde in the Xilinx Standalne Envirnment Overview Xilinx Data Types Using Device Drivers Using Timers GPIO Detailed Example Tips and Tricks Address Management Address Management Object Files and Sectins Linking and Lcating Linker Scripts Sftware Aspects f the Interruptsystem in the Zynq device Overview Interrupts in the Crtex-A9 Prcessr Interrupt Inclusin Using an Interrupt Cntrller fr Multiple Interrupts Create the Embedded Sftware Interrupt-Structure Cnsideratins fr Implementing Interrupts Sftware Platfrm Dwnlad and Bt Overview Btlader Optins fr the Zynq All Prgrammable SC Btlader Sequence f the Zynq All Prgrammable SC Bting the Zynq All Prgrammable SC frm Off-Chip Flash r Anther Peripheral Writing a Custm Device Driver Overview Including the Driver in the BSP MDD File Tcl File MSS File Driver Cde Structure 6

7 Labs: 1. Basic System Implementatin 2. Embedded Sftware Applicatin Develpment 3. Sftware Interrupts 4. File Systems 5. Writing a Device Driver 7

8 Blck 4: Verificatin fr Hardware and Sftware Generate an IP template using the Create and Package IP Wizard Attach custm IP t the wizard-prvided skeletn HDL Manage a custm AXI IP design using the prvided Vivad IDE prject Describe the Bus Functinal Mdel (BFM) and hw it helps in verificatin List the BFM IP catalg cmpnents ffered by Xilinx Describe the basic tenets f the BFM Verilg API tasks Describe the Vivad Design Suite BFM design flw Identify the current debugging capabilities in SDK Describe the differences between the XMD and GDB debuggers List the features f the GDB debugger Use the SDK debugger perspective List the benefits f hardware/sftware debugging using the Vivad Lgic Analyzer Designing a Custm AXI Peripheral Talking AXI AXI Backend Signaling Requirements Creating a Custm AXI Peripheral Bus Functinal Mdel Simulatin Debugging Custm IP BFM Simulatin Bus Functinal Stimulus BFM Simulatin Flw Using the Create & Package IP Wizard Putting Tgether Custm IP Details Package IP Tab Sftware Applicatin Debugging Overview XMD Debugger GNU Debugger Debugging in SDK 8

9 Mdifying the Hardware Advanced Debugging Capabilities Debugging Using the Vivad Runtime Lgic Analyzer Overview Hardware Debugging Debug Cnfiguratin Wizard Sftware Debugging Debugging in SDK Platfrm Debugging Labs: 1. Building Custm AXI IP fr an Embedded System 2. BFM Simulatin fr an AXI Peripheral 3. Integrating a Custm Peripheral 4. Applicatin Debugging 5. Hardware/Sftware C-Debugging using the Vivad Lgic Analyzer 9

10 Blck 5: Optimizatin f Embedded Systems Apply sftware techniques t imprve perability Describe what prfiling is and hw it wrks Write a sftware applicatin fr prfiling Use the SDK prfiling perspective Use prfiling reprts t evaluate sftware efficiency Discuss sftware tradeffs t hardware Identify when t use an AXI external cnnectr cmpnent List the AXI bridge cmpnents and describe when t use them Describe the differences between AXI CDMA, DataMver and DMA cmpnents List the peratinal features f the Zynq All Prgrammable SC PS DMAC Explain the usage f the AXI streaming FIFO cmpnent Identify advanced methds f interfacing an embedded prcessing system t prgrammable lgic Describe the tw techniques t bt the secnd CPU Outline the DMA features and services n the Zynq All Prgrammable SC Sftware Applicatin Prfiling Overview Writing Sftware fr Prfiling SDK Prfiling Reading and Evaluating Prfiling Reprts Prfiling in Linux Ging t Prgrammable Lgic Meeting Perfrmance Gals Perfrmance Objectives Sftware r Prgrammable Lgic? DDRx Memry Speed and Latency Achieving Maximum DMA Perfrmance Sleep and Pwer Reductin System Data Mvement Lw Latency and High Bandwidth 10

11 AXI Everything AXI Outside the Embedded Realm AXI Cnnectr and Bridges AXI DMA Advanced Prcessr and Peripheral Interface Optins Data-Passing Mechanisms IP Catalg Cmpnents PS IOP Cmpnents in the Zynq All Prgrammable SC Utility Cmpnents Advanced Bt Methdlgy n the Zynq AP SC Starting Yur Engines Single-Prcessr Bt Dual-Prcessr Bt Prgrammable Lgic Cnfiguratin Secure Bt Advanced DMA Cntrller Cnfiguratin n the Zynq All Prgrammable SC Optimizing DMA Zynq All Prgrammable SC DMAC Basics Prgramming DMA n the Zynq All Prgrammable SC Use Cases fr Zynq All Prgrammable SC DMA Labs: 1. SDK Prfiling 2. Extending Memry Space with Blck RAM 3. Extending Memry Space with a DDR3 Cntrller 4. Cnfiguring DMA n the Zynq All Prgrammable SC 5. Bt Lading frm Flash Memry 11

12 Blck 6: Embedded Linux n Zynq Systems Part 1: Describe prcesses, tasks and the scheduler Use different file systems Master the Linux cmmand line and write custm shell scripts Describe useful C-Libraries Manage the develpment envirnment and the crss cmpiler Use virtual file systems Learn the basics f the rt file systems Debug yur applicatins n Zynq SC Scheduler, prcesses, tasks, Users, Grups and file access Rt file system (File System Hierarchy Standard (FHS)) File systems like ext2,3 fat32 and the Memry Technlgy Deivice Framewrk fr flash based memry. Using Linux cmmand line Creating shell scripts Linux initializatin system Develpment envirnment and crss cmpiler C-Libraries uclibc, glibc, eglibc Using Xilinx SDK and JTAG debugger fr Linux applicatin debugging n Zynq Creating and applying patches Labs: Frmatting bt flash device Getting t knw Linux cmmand line utilities Shell scripting, an easy way t autmate tasks Updating f sftware surces with patches Flash memry devices and the MTD framewrk Using the sysfs GPIO driver Installing and cnfiguring SSH 12

13 Blck 7: Embedded Linux n Zynq Systems Part 2 Describe the Linux bt prcedure n Xilinx Zynq SC Build yur wn kernel, btlader and rt file system Build a rt file system frm scratch Build a simple webserver Use the tls yct r buildrt Linux bt prcedure n Xilinx Zynq SC Dwnlad, cnfiguratin and cmpilatin f u-bt bt lader Dwnlad, cnfiguratin and cmpilatin f Linux kernel Creating a cnsle based rt file system frm scratch Device file creatin init-prcess set up mdify init scripts t adapt bt sequence Autmatic embedded Linux system creatin with build system like yct r buildrt Labs: Cnfiguring the u-bt bt lader frm surces Cnfiguring u-bt fr netwrk bt using TFTP Cmpiling the Kernel Creating a rt file system Using a build system fr autmated Linux develpment Installing and cnfiguratin f a simple webserver using the build system 13

14 Blck 8: Embedded Linux driver develpment n Zynq Systems Linux basics fr drvier develpment Everything we need t knw abut Linux t understand Linux driver and develp ur custm slutins Linux driver mdules Fundamentals abut Linux ladable mdules Character Driver Mst suitable interface between user space and kernel space fr FPGA cmpnents n XILINX Zynq Platfrm Driver and device tree Interface f driver t XILINX Zynq FPGA fabric via AXI intercnnect. Linux Driver APIs Timer, delays, threads, wrk queues, semaphres, mutex, wait queues Cntrlling and debugging f a driver Sysfs file system, printk, OOPS-messages, GDB Linux Driver Basics Virtual, lgical and physical addressing Prcess cntexts Makefiles fr driver mdule develpment Character-, Blck, and Netwrk-Devices Hardware Access Device Tree Basics Register access and interrupts Clck management Prtectin Mechanisms Race cnditins Mutex and Semaphres Spinlcks 14

15 Timing and Wrking Kernel Threads, Tasklets and wrk queues Jiffies, high reslutin timers and wait queues Labs: 1. Implementatin f a basic kernel mdule 2. Basic char driver implementatin 3. Upgrading the basic char driver 4. Cmpiling the device tree 5. Register and unregister a platfrm driver 6. Cntrlling and managing clck signals 7. Cntrl LEDs cnnected t a GPIO cntrller 8. Implement interrupts fr platfrm driver 9. Cmbine the previus develp mdules 10. Implement a kernel thread 11. Wrk queue implementatin 12. Hrtimer implementatin 13. wait queue implementatin 14. sysfs implementatin 15. using binary attributes with sysfs 15