ECE 465, Spring 2010, Instructor: Prof. Shantanu Dutt. Project 2 : Due Fri, April 23, midnight.

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1 ECE 465, Spring 2010, Instructor: Prof Shantanu Dutt Project 2 : Due Fri, April 23, midnight 1 Goal The goals of this project are: 1 To design a sequential circuit that meets a given speed requirement in terms of the numbers of clock cycles (cc s) 2 To design a sequential circuit that is composed of multiple interacting FSMs that are obtained using a divide-and-conquer (D&C) approach Using this approach, the outputs of the FSMs are stitched-up using a purely combinational circuit to produce the desired output of the original problem 3 To synthesize each FSM using the one-hot design style 2 Design Problem A digital circuit is needed that can determine the remainder of an -bit number after division by 3 (ie, determine ) However, since can be large, and hardware cost needs to be kept low, it was determined that a combinational circuit that has all bits of inputed to it in parallel cannot be afforded (such a circuit will have hardware cost proportional to, ie, its hardware cost will be ) The circuit s cost needs to be much less than this, and in fact, a constant cost (ie, independent of ) is most desirable, and at most the cost should be One can design a finite state machine (FSM) to which each bit of is fed sequentially, (either LSB or MSB first), on a bit-serial input line (each bit on line is fed once every clock cycle) It was, however, determined that it will take clock cycles (cc s) for a single FSM to compute the remainder (ie, modulus 3) function, and that that is too slow A speed of around cc s ( a few cc s) is desired You need to design a Moore machine based sequential circuit that meets the above specifications, and works automatically for any of the following values of : 16, 32, 64, 128 A possible high-level schematic for the required circuit is shown in Fig 1 You need to organize and describe your design systematically as follows 1 Draw and describe the D&C tree (this includes the breakup and the stitchup) for your design 2 The design steps (derivation of the design, and then the actual logic design) of the combinational stitch-up logic 3 The input to your circuit is an an -bit number (which you need to load into an -bit register/shiftregister), where is either of 16, 32, 64, 128, and the value of encoded as a 2-bit quantity he 2 bits of are the 2 MSBs of the actual binary representation of the number Design the logic for automatically partioning the -bit and feeding the partitioned bits to the multiple FSMs needed in the circuit 1

2 FSM 1 n-bit shift register Partitioning Logic Stitch-up Logic S A 2 n n a1 ak FSM k A mod 3 Figure 1: Possible schematic for the required mod 3 circuit

3 Note that, besides the bit, it may be necessary to feed to each FSM a start bit, which when high indicates to it that the bit on the lie is the 1st bit it is receiving, and a finish bit, which when high indicates to it that it has received the last bit for the current 4 Give a clearly labeled state transition diagram of the core FSM needed in your design Each state of the FSM should be labeled so as to understand the meaning of the state, ie, what the state remembers about past inputs There should be a clear indication of the reset state Note that after each FSM has been fed the final bit it needs to process, it should enter a state at which it should remain until an explicit reset signal is sent (which would then make it go to the reset state) 5 Synthesize the core FSM into a sequential circuit using one-hot state encoding (also called unary encoding) techniques (one-hot design generally uses D FFs) Clearly draw this one-hot sequential circuit The connection of the system reset input to the FFs set ot reset inputs should be shown so that the circuit goes to the reset state, when the system reset signal is active 6 Give a block-level schematic of the entire circuit that shows how the multiple modules (input register/shift-register, partitioning logic, the multiple FSMs, the stitch-up logic, and any other modules needed in your design) 7 Assuming that a -input gate has a delay of units, analytically determine for an -bit, the delay of: a) the partitioning logic, b) the next-state logic unit of an FSM, c) the output logic unit of an FSM, and d) the stitch-up logic, as functions of (if it happens that the delay of some unit(s) is a constant, ie, independent of, then that is fine) Assume also, that the maximum value of is a power of 2, say,, and that the different values of can be,! "$# Based on the above delay components, analytically determine the delay of your circuit for producing for an -bit Assume that a D-flip-flop s delay and setup times are %'&(& and %*),+ Writing down the final delay expressions is not enough; you need to derive them step by step 8 Determine, also as a function of, the combinational hardware cost of your circuit in terms of total gate inputs of the next-state and output logic units across all your FSMs, the partitioning logic, and the stitch-up logic Separately, also determine the number of D FFs required in your design as a function of Hints: 1 D&C Hint: /21 # 354 ;:<1 # 354 #6 7 #6 7 /,1 #68 7 # :=,1 #68 # 2000 points 2 FSM design hint: The core FSM needs to remember the following (a) The remainder of the number seen so far For example, if an FSM has been fed the 1st 5 bits, say,?>@bababa<@c ED F>@BABABA(@C ED of the number that it needs to process, then, it needs to determine, and remember it as a particular state (b) Some information about the number of bits that it has been fed so far, though not necessarily the exact number, so that it knows the,g value of the next bit that it will receive 2

4 H H A 3 Implementation and Simulation using Quartus II You are required to implement and simulate your design using the Quartus II CAD software as specified below: 1200 points 1 The project is to be done in groups of 2 (the same team that you had for Project 1) 2 Choose the schematic capture tool in Quartus to specify your design 3 Device family to be used for the project is Cyclone which is selected by default in Quartus 4 Please note the following two important issues for your design and its timing analysis: Keep your design as a circuit and do not make it a chip It seems that in the latter, the timing analyzer models the inputs and outputs of the circuit as i/o pins of a chip, which means they have a high capacitive load, and this skews the timing analysis of your design a bit In any case, your design will be **part** of a chip, and thus should be kept as a circuit to get more realistic timing analysis for it Note also that for performing timing analysis of your design you NEED TO set the Fitter setting in Quartus II to Standard Fit in order to get a more accurate critical path delays of your design 5 Implement your design using D-FFs, registers, shift-register (if not available, you can design shift registers easily using D-FFs and 2:1 Muxes), 2-input AND/OR/NAND/NOR/XOR/XNOR gates, NOT gates, 2:1 and 4:1 Muxes, and 1:2 and 1:4 Demuxes from the Quartus in-built library 6 Design the basic next-state and output logic units using the above components, and simulate them for correctness (generate your own inputs for this simulation) Also perform timing analysis to obtain the maximum delay of each combinational unit in each FSM 7 Design the partitioning logic using the above components, and obtain its delay Note that the partitioning logic will be in the delay path for the external input being fed to the FSMs, and that this path starts from the output of the register/shift-register that stores the -bit 8 Based on the delays obtained in the above two items and the FFs propagation delay and set-up times, determine a safe clock period (I IKJ the minimum clock period needed) for each FSM implementation 9 Using the above designs and other in-built library components like positive-edge triggered D-FFs, obtain the one-hot FSM implementation 10 Design the stitch-up logic using the above components Simulate it and obtain its delay Note that while the stitch up logic is obviously on the output path, it does not need to necessarily figure in the delays of various combinational units that determine the clock period for FSM operation This is so, since for this problem, the final outputs of the circuit (which is also the outputs of the stitch-up logic) is determined only after all bits of have been processed by the FSMs, ie, the delay of the stitch-up logic is irrelevant in the normal working of the FSMs (their state transitions for each input bit they receive) 11 Using the above determined clock period, perform simulations of each FSM using your own inputs 3

5 12 Using the above determined clock period, simulate your entire design for all the input vectors ( s and s) provided by the TA (you should also do your own simulations beforehand) 13 Determine the delay of your circuit in terms of absolute time units (ie, not in terms of cc s but in terms of time units like ns s) Time starts after the input is stored in an input register/shift-register Mention the various components of this delay 14 Plot both the empirical delays (obtained above for the Quartus implementation) and your analytical delays for inputs of sizes 16 to 128, and comment on whether two sets of delays are consistent, at least in terms of their order notation 15 You need to submit a clearly written project report detailing all your work including all the steps and results of the design process (discussed in the previous section), use of the schematic capture tool, simulation results of component(s) and the final design, and other findings, if any, and conclusions The report should be professionally written using a text processing software (eg, MS Word, latex), and all figures, plots, tables, etc in it should also be generated preferably using some software tool You should avoid hand-drawn/written material Submit only one report per team Important Note on Honor Policy: Students are encouraged to interact with each other, share ideas and also discuss them with the instructor or the TA However, the final design should be each team s own design, Copying of the project between groups cannot be condoned, and if evidence of copying is detected, we will unfortunately have to report the concerned groups for disciplinary action, and they will fail the course 4