! Initially developed under DOD auspices, later standardized as IEEE standards , , & (standard logic data type)
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1 VHDL Introduction, Part I Figures in this lecture are from: Rapid Prototyping of Digital Systems, Second Edition James O. Hamblen & Michael D. Furman, Kluwer cademic Publishers, 2001, ISN Dr. omputer Science Department Kent State University Kent, OH US VHDL History 2! VHDL = VHSI Hardware Description Language " VHSI = Very High Speed Integrated ircuits " oth US Department of Defense (DOD) programs! Initially developed under DOD auspices, later standardized as IEEE standards , , & (standard logic data type)! Syntax similar to D and Pascal! concurrent language, initially aimed at simulation, later at synthesis " Specific subsets and cookbook design styles supported by logic and behavioral synthesis tools " Write code like this & you ll get this expected design
2 Signals, Time, and Simulation! Variables vs. signals " VHDL variables change value without delay " VHDL signals have an associated delay! signal is given a value at a specific point in time, and retains that value until it is given a new value " waveform is a sequence of values over time " Example: in1 <= 0, 1 after 5 ns, 0 after 15 ns; " variable has a single value, whereas a signal has multiple value / time pairs! discrete event simulator executes VHDL code by advancing time to the next event, updating signal values, then possibly scheduling new events 3 Simple Gate Network (Desired Hardware) X Y 4
3 Simple Gate Network (VHDL ode) LIRRY IEEE; -- Include Libraries for standard logic data types USE IEEE.STD_LOGI_1164.LL; -- Entity name normally the same as file name ENTITY gate_network IS -- Ports: Declares module inputs and outputs PORT(,, : IN STD_LOGI; -- Standard Logic Vector ( rray of 4 its ) D : IN STD_LOGI_VETOR( 3 DOWNTO 0 ); -- Output Signals X, Y : OUT STD_LOGI ); END gate_network; 5 -- Defines internal module architecture RHITETURE behavior OF gate_network IS EGIN -- oncurrent assignment statements operate in parallel -- selects bit 1 of standard logic vector D X <= ND NOT( OR ) ND ( D( 1 ) XOR D( 2 ) ); -- Process must declare a sensitivity list, -- In this case it is (,,, D ) -- List includes all signals that can change the outputs PROESS (,,, D ) EGIN -- Statements inside process execute sequentially Y <= ND NOT( OR ) ND ( D( 1) XOR D( 2 ) ); END PROESS; END behavior; VHDL Design Styles! VHDL was designed to support both behavioral and structural designs as various levels of abstraction " ehavioral description says what the design does, but not how it is implemented " Structural description specifies the interconnection of a set of components, but not what the components do " The design process tends to convert high-level behavioral descriptions to low-level structural ones! VHDL design entities include " Entity declaration interface (named I/O ports) " rchitecture declaration behavioral or structural description of the design entity 6
4 Simple Gate Network (Entity) LIRRY IEEE; -- Include Libraries for standard logic data types USE IEEE.STD_LOGI_1164.LL; -- Entity name normally the same as file name ENTITY gate_network IS -- Ports: Declares module inputs and outputs PORT(,, : IN STD_LOGI; -- Standard Logic Vector ( rray of 4 its ) D : IN STD_LOGI_VETOR( 3 DOWNTO 0 ); -- Output Signals X, Y : OUT STD_LOGI ); END gate_network; X Y 7 Simple Gate Network (rchitecture) -- Defines internal module architecture RHITETURE behavior OF gate_network IS EGIN -- oncurrent assignment statements operate in parallel -- selects bit 1 of standard logic vector D X <= ND NOT( OR ) ND ( D( 1 ) XOR D( 2 ) ); -- Process must declare a sensitivity list, -- In this case it is (,,, D ) -- List includes all signals that can change the outputs PROESS (,,, D ) EGIN -- Statements inside process execute sequentially Y <= ND NOT( OR ) ND ( D( 1) XOR D( 2 ) ); END PROESS; END behavior; X Y 8
5 VHDL Data Types! oolean, integer, real! STD_LOGI to model logic values " 0, 1, Z, U, X,, L, W, H " Z = tri-state, U = uninitialized, X = unknown, = don t care, L = weak 0, W = weak unknown, H = weak 1 Table 6.2 STD_LOGI conversion functions. Function Example: TO_STDLOGIVETOR( bit_vector ) TO_STDLOGIVETOR( X"FFFF" ) onverts a bit vector to a standard logic vector. Generates a 16-bit standard logic vector of ones. "X" indicates hexadecimal and "" is binary. ONV_STD_LOGI_VETOR( integer, bits ) ONV_STD_LOGI_VETOR( 7, 4 ) onverts an integer to a standard logic vector. Produces a standard logic vector of "0111". ONV_INTEGER( std_logic_vector ) ONV_INTEGER( "0111" ) onverts a standard logic vector to an integer. Produces an integer value of VHDL Operations Precedence: **,S,NOT *,/,MOD,REM +, (sign) +,,& SLL,SRL,SL, =,/=,<,<=,>,>= ND,NOT,OR, NOT,XOR, XNOR (note: all at same level) VHDL Operator Table 6.1 VHDL Operators. Operation + ddition - Subtraction * Multiplication* / Division* MOD REM & SLL** SRL** SL** SR** ROL** ROR** Modulus* Remainder* oncatenation used to combine bits logical shift left logical shift right arithmetic shift left arithmetic shift right rotate left rotate right = equality /= Inequality < less than <= less that or equal > greater than >= greater than or equal NOT ND OR NND NOR XOR XNOR* logical NOT logical ND logical OR logical NND logical NOR logical XOR logical XNOR *Not supported in many VHDL synthesis tools. In the MX+PLUS II tools, only multiply and divide by powers of two (shifts) are supported. Mod and Rem are not supported in MX+PLUS II. Efficient design of multiply or divide hardware typically requires the user to specify the arithmetic algorithm and design in VHDL. ** Supported only in VHDL. Note: VHDL is not case sensitive
6 oncurrent and Sequential Statements 11! oncurrent statements " Signal assignment " onditional signal assignment (WHEN-ELSE) " Selected signal assignment (WITH-SELET-WHEN) " Process! Statements inside a process are executed sequentially " Variables, arrays, queues " Variable assignments (no delay) " IF-THEN-ELSE,SE-WHEN, LOOP " WIT UNTIL, WIT FOR, WIT ON " WRNING not everything you do in a process may be synthesizable by your synthesis tools! Four Multiplexers LIRRY IEEE; USE IEEE.STD_LOGI_1164.LL; ENTITY multiplexer IS -- Input Signals and Mux ontrol Mux_Out3, Mux_Out4 : OUT STD_LOGI ); END multiplexer; PORT(,, Mux_ontrol : IN STD_LOGI; Mux_Out1, Mux_Out2, Mux_ontrol 0 1 Mux_Outx RHITETURE behavior OF multiplexer IS EGIN -- selected signal assignment statement Mux_Out1 <= WHEN Mux_ontrol = '0' ELSE ; -- with Select Statement WITH mux_control SELET Mux_Out2 <= WHEN '0', WHEN '1', WHEN OTHERS; -- OTHERS case required since STD_LOGI -- has values other than "0" or "1" PROESS (,, Mux_ontro l) EGIN -- Statements inside a process IF Mux_ontrol = '0' THEN -- execute sequentially. Mux_Out3 <= ; ELSE Mux_out3 <= ; END IF; 12 SE Mux_ontrol IS WHEN '0' => Mux_Out4 <= ; WHEN '1' => Mux_Out4 <= ; WHEN OTHERS => Mux_Out4 <= ; END SE; END PROESS; END behavior;
7 Signal ssignment! oncurrent signal assignment " Example: a <= 1 ; z <= a XOR b; " LHS signal type must match RHS! onditional signal assignment " Example: z <= s0 WHEN sel= 0 ELSE s1; " Last ELSE should have no condition to handle all cases not otherwise covered 13! Selected signal assignment " Example: WITH sel SELET z <= s0 WHEN 0, s1 WHEN 1 ; " over all cases in mutually-exclusive fashion, possibly use WHEN OTHERS for last case Processes! process may begin main: process (, ) " Name of process is main " Sensitivity list for process is,! Sensitivity list " If one of these signals changes, the process executes " Should contain any signals on the right-hand-side of an assignment, or in any boolean condition! onditionals in IF statements must return a boolean " OK to write: if reset = 1 then " NOT OK to write: if reset then! Returns a standard logic type (!) 14
8 Sequential Statements (Inside Process)! IF-THEN-ELSE " Only statements in the first condition matched will be executed " Nesting allowed, each level adds more multiplexing or other additional logic, so should be done carefully! SE-WHEN " Good when all branching is based on signle condition! LOOP, WHILE-LOOP, FOR-LOOP " Repetition! WIT UNTIL (boolean), WIT FOR (time expression), WIT ON (signal) -- waits for event on that signal 15
Concurrent & Sequential Stmts. (Review)
VHDL Introduction, Part II Figures in this lecture are from: Rapid Prototyping of Digital Systems, Second Edition James O. Hamblen & Michael D. Furman, Kluwer Academic Publishers, 2001, ISBN 0-7923-7439-
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