CS Digital Systems Project Laboratory
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1 CS 194- igital Systems Project Laboratory Lecture 1 Virtex-5 Microarchitecture Not a professor. John is OK John Lazzaro ( And also, an introduction to the project. Special Guest: Greg Gibeling www-inst.eecs.berkeley.edu/~cs194-/ 1
2 Topics for today s lecture Introduction to the project platform (Xilinx ML evaluation board). Class organization, semester schedule, administrivia... Project ideas (Greg Gibeling) 2
3 Project platform: Xilinx ML
4 FPGA: Xilinx Virtex-5 XC5VLX110T Virtex-5 die photo A die is an unpackaged part!"#$%&'() 4
5 From die to PC board... Ball Grid Array (BGA) Flip-Chip Package Adhesive Epoxy* Copper Heatspreader Solder Ball Thermal Interface Material Underfill Epoxy Flip Chip Solder Bump Silicon ie Organic Build-Up Substrate!"#$%&'() 5
6 Tracing a die pad through a design... What a pad looks like on the die... What a pad looks like on an I/O Block (IOB) schematic... IFFO_IN PA IFFO_OUT T PAOUT O I OUTBUF INBUF IFFI_IN ug190 02_02130 Figure -2: Basic IOB iagram Which pad goes to which package pin?
7 Banks of I/O placed on chip floor plan BANK 40 I/O BANK 40 I/O BANK 40 I/O BANK 40 I/O Figure -3: BANK 20 I/O BANK 20 I/O CONFIG BANK 20 I/O BANK 20 I/O BANK 40 I/O BANK 40 I/O BANK 40 I/O BANK 40 I/O ug190 03_02130 Virtex-5 XC5VLX30 I/O Banks Colors on this package pinout map to banks. A B C E F G H J K L M N P R T U V W Y AA AB AC A AE AF A B C E F G H J K L M N P R T U V W Y AA AB AC A AE AF!"#$%&'() 7
8 Virtex-5 Top-own 8
9 Colors represent different types of resources: Logic Block RAM SP (ALUs) Clocking I/O Serial I/O + PCI A routing fabric runs throughout the chip to wire everything together.!"#$%&'() 9
10 Routing fabric requires many interconnect layers.!"#$%&'() 10
11 Logic Resources 11
12 Configurable Logic Blocks (CLBs) Slices define regular connections to the switching fabric, and to slices in CLBs above and below it on the die. COUT COUT CLB Slice(1) Switch Matrix Slice(0) CIN CIN UG190_5_01_12205 The LX110T has 17,280 slices. 12
13 X-Y naming convention for slices X0, X2,... are lower CLB slices. X1, X3,... are upper CLB slices. Y0, Y1,... are CLB column positions. COUT COUT COUT COUT CLB Slice X1Y1 CLB Slice X3Y1 Slice X0Y1 Slice X2Y1 CIN CIN CIN CIN CLB COUT Slice X1Y0 COUT CLB COUT Slice X3Y0 COUT Slice X0Y0 Slice X2Y0 Lower-left corner of the die. UG190_5_02_
14 Atoms: 5-input Look Up Tables (s) A 5 A[:2] (1) (0) (1). (0) A[:2] Computes any 5-input logic function. Timing is independent of function (0) (1) Flip-flops set during configuration. 14
15 Virtex-5 -s: Composition of 5-s A1 5 May be used as one -input ( out)... A A or as two 5-input S ( and 5) A WP245_03_05100 Figure 3: Block iagram of a Virtex-5 -Input The LX110T has 9,120 -s - delay is 0.9 ns Combinational logic (post configuration) 15
16 The simplest view of a slice SLI () Four -s ([:1]) A[:1] () (Optional) Four Flip-Flops (C[:1]) A[:1] (C) (C) (Optional) (B) Switching fabric may see combinational and registered outputs. (B[:1]) A[:1] (B) (A[:1]) (CLK) (Optional) (A) (A) A[:1] (Optional) An actual Virtex-5 slice adds many small features to this simplified diagram. We show them one by one... 1
17 Two 7-s per slice... SLI ([:1]) A[:1] F7BMUX (C[:1]) A[:1] (CMUX) (C) (Optional) Extra multiplexers (F7AMUX, F7BMUX) (CX) (CLK) (B[:1]) A[:1] F7AMUX Extra inputs (AX and CX) (AMUX) (A[:1]) A[:1] (A) (Optional) (AX) 17
18 Or one 8-s per slice... SLI ([:1]) A[:1] F7BMUX (C[:1]) (CX) A[:1] F8MUX (BMUX) Third multiplexer (F8MUX) (B[:1]) A[:1] F7AMUX (Optional) (B) Third input (BX) (A[:1]) A[:1] (AX) (BX) (CLK) UG Configuring the n of an n
19 Extra muxes to chose option... Inputs X O5 FE/LAT CLK MUX From eight 5-s... to one 8-. SR REV C Inputs CX O5 F7BMUX F8MUX FE/LAT CLK C CMUX C Combinational or registered outs. SR REV B Inputs BX O5 FE/LAT CLK SR REV B BMUX B Flip-flops unused by s can be used standalone. F7AMUX A Inputs A O5 AMUX FE/LAT AX CLK SR REV (X) CLK A SR REV UG190_5_25_05050 Flip-flops... 19
20 Slice flip-flop properties... Output CK FF FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV Each state element may be edge-triggered or latching. X CX SR BX CLK AX C Output B Output A Output CK CK CK CFF FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV BFF FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV AFF FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV C Reset Type Sync Async B A Clock enable, clock polarity, and set/reset lines in a slice are shared. Each state element may respond differently to set/ reset signal. Next: The vertical dimension... 20
21 Reminder: arithmetic addition... One-bit full adder Simplest multi-bit adder [Co,S] = A + B + Ci A, B, Ci: 1-bit number inputs. [Co,S]: 2-bit number output. + : Arithmetic addition. Ripple-carry adder 21
22 Virtex-5 vertical logic... From O5 From X S3 COUT (To Next Slice) I3 MUXCY Carry Chain Block (CARRY4) CO3 O3 MUX/* MUX We can map ripple-carry addition onto carry-chain block. (Optional) From C S2 MUXCY CO2 CMUX/C* O5 From C CX I2 O2 CMUX C (Optional) From B S1 MUXCY CO1 BMUX/B* O5 From B BX I1 O1 BMUX B (Optional) From A O5 From A AX CO0 S0 MUXCY O0 I0 CYINIT CIN 0 1 CIN (From Previous Slice) AMUX/A* AMUX A (Optional) * Can be used if unregistered/registered outputs are free. UG190_5_24_05050 The carry-chain block also supports the faster carry-save chain logic. 22
23 Putting it all together... a SLIL X A A1 ROM O5 COUT X CK Reset Type Sync Async FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV MUX The previous slides explain all SLIL features. CMUX C C5 C4 C3 C2 C1 CX B B5 B4 B3 B2 B1 BX A A1 AX SR CLK A A1 A A1 A A1 ROM ROM ROM O5 O5 O5 0/1 C CX B BX A AX CK CK CK FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV C C BMUX B B AMUX A A About 50% of the 17,280 slices in an LX110T are SLILs. The other slices are SLIMs, and have extra features. CIN UG190_5_04_
24 A Recall: 5- architecture... 5 A[:2] (1) (0) (1). (0) (0) (1) A[:2] 32 Flip-flops. Configured to 1 or 0. Some parts of a logic design need many flip-flops. SLIMs replace normal 5-s with circuits that can act like 5-s, but can alternatively use the 32 Flip-Flops as RAM, ROM, shift registers. 24
25 A SLIM -... Normal - inputs. Memory write address Memory data input A A1 WA1-WA WA7 WA8 I2 PRAM4/32 SPRAM4/32 SRL32 SRL1 O5 RAM I1 ROM MC31 Normal 5/- outputs. Memory data input. Control output for chaining s to make larger memories. A 1.1 Mb distributed RAM can be made if all SLIMs of an LX110T are used as RAM. 25
26 Many RAM configurations possible... A[7:0] WCLK WE 8 (CLK) (WE/) RAM25X1S I1 A[:1] WA[8:1] CLK WE SPRAM4 A (CX) Example configuration: Single-port 25b x 1, registered output. I1 SPRAM4 F7BMUX A complete list: 8 8 A[:1] WA[8:1] CLK WE I1 A[:1] WA[8:1] CLK WE SPRAM4 A (AX) A7 (BX) F8MUX O Output Registered Output (Optional)! Single-Port 32 x 1-bit RAM! ual-port 32 x 1-bit RAM! uad-port 32 x 2-bit RAM! Simple ual-port 32 x -bit RAM! Single-Port 4 x 1-bit RAM! ual-port 4 x 1-bit RAM! uad-port 4 x 1-bit RAM 8 I1 A[:1] WA[8:1] CLK WE Figure 5-14: SPRAM4 F7AMUX istributed RAM (RAM25X1S) UG190_5_14_05050! Simple ual-port 4 x 3-bit RAM! Single-Port 128 x 1-bit RAM! ual-port 128 x 1-bit RAM! Single-Port 25 x 1-bit RAM A 128 x 32b RAM has a 1.1ns access time. 2
27 SLIM shift register (one of many). SHIFTIN () 32-bit Shift Register WE SHIFTOUT(31) CLK Address (A[4:0]) 5 MUX UG190_5_1_05050 See Virtex-5 User Guide for an complete list of shift-register types. 27
28 SLIL vs SLIM... A I2 COUT X C CX B BX A AX I1 MC31 O5 UG190_5_03_04100 A1 I MUX C C CMUX B B BMUX A A AMUX Reset Type X WA1-WA WA7 WA8 PRAM4/32 SPRAM4/32 SRL32 SRL1 RAM ROM PRAM4/32 SPRAM4/32 SRL32 SRL1 RAM ROM PRAM4/32 SPRAM4/32 SRL32 SRL1 RAM ROM PRAM4/32 SPRAM4/32 SRL32 SRL1 RAM ROM FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV CK FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV CK FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV CK FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV CK CLK WSGEN CIN 0/1 WE Sync Async A I2 I1 MC31 O5 A1 C CI CX C5 C4 C3 C2 C1 A I2 I1 MC31 O5 A1 B BI BX B5 B4 B3 B2 B1 A I2 I1 MC31 O5 A1 A AI AX SR CLK WE A1 WA1-WA WA7 WA8 WA1-WA WA7 WA8 WA1-WA WA7 WA8 A ROM COUT X C CX B BX A AX O5 UG190_5_04_0320 A1 MUX C C CMUX B B BMUX A A AMUX X FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV CK FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV CK FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV CK FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV CK CIN 0/1 A ROM O5 A1 C CX C5 C4 C3 C2 C1 A ROM O5 A1 B BX B5 B4 B3 B2 B1 A ROM O5 A1 A AX SR CLK A1 Reset Type Sync Async SLIM SLIL SLIM adds memory features to s, + muxes. 28
29 To be continued... Throughout the semester, we will look at different Virtex-5 features in-depth. Switch fabric Block RAM SP (ALUs) Clocking I/O Serial I/O + PCI!"#$%&'() 29
30 The payoff for esign to the part...!%&$!"#$!""#$%&'$()*+,&-"#./* ).0*1$%2(3#&4. 57!'()*+,)-.'/(-01 2+(3-')1*45,1 $+(!7 #*.8*59 :.+')1*!'()*+,)-.' $+441*!'()*+,)-.' BC-4)A%.8-,5< &+<)-<E ;18-()1*37-<1 =>?=>2 5)5/(-01 2+(3-')1*45,1 $+(!7 %&$ "#$ 2!"##"$%&'"%()%*"+%,-.'% / 0123%,-.4'%5*%5$#"7849%:!%4;< / 04<<%,-.2'%%5*%5$#"78=9%:!%=;< 2 )$(>%?%'#@A"%8B%=%'#@A"%C5C"5*" 2 *"+%C$(E"''($F%)$(>%<;31% G:5C'H:IJ%#(%0;04%G:5C'H:IJ 2 0K<:IJ%8B%1<0%:IJ 2 022%8B%1?<%GL$M'#(*"%:5C' -'"%*"+%%2%,-.9%1%'#@A"%N""C"$%C5C"9%%0<O%>($"%:IJ9%?3O%P"##"$%C"$)($>@*E" 30
31 Class Organization 31
32 CS 194-: Pure project course. No exams. No homework. Mondays: Lectures teach topics useful for the project Project teams: 1-to-3 person groups. This Friday: setting project topics. 10-noon, 125 Cory (not 119 Cory!). Fridays: Project check-ups. 32
33 CS 150 is a hard prerequisite for CS194 Exceptions considered only for graduate students... 33
34 CS 194-: Project red-letter days. Specification esign Review Mon, Sept 29 Implementation esign Review Mon, Nov 3 Grade is based on revised versions of presentation slides ( PFs to Greg and John after presentation). Final Presentation Fri, ec 5 34
35 Text, Printing, Honor Code... Recommended Text: Computer Organization and esign, avid Patterson and John Hennessy. Printing: The first 200+ pages are free (count includes cover sheets). Then, $12 per 200 pages. Plan ahead... Account forms coming soon... We expect you to obey the EECS Policy on Academic ishonesty. See Course Info on website for info. Class web site coming soon... 35
36 Lab access, remote work, lab rules For card key access to 119/125 Cory: apply at 253 Cory. Let us know if this doesn t work yet... Also work remotely -- see Remote esktop info on Resources page. Eat/drink at round tables only, log equipment failures in log book (and TAs), don t share account, logoff after each session. Be crime/safety aware. 3
37 Next Monday s Lecture: Single-cycle CPU design 37
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